2 comedi/drivers/ni_tio.c
3 Support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments general purpose counters
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Thu Nov 16 09:50:32 EST 2006
34 This module is not used directly by end-users. Rather, it
35 is used by other drivers (for example ni_660x and ni_pcimio)
36 to provide support for NI's general purpose counters. It was
37 originally based on the counter code from ni_660x.c and
41 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
42 DAQ 6601/6602 User Manual (NI 322137B-01)
43 340934b.pdf DAQ-STC reference manual
48 Support use of both banks X and Y
51 #include "ni_tio_internal.h"
53 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
54 unsigned generic_clock_source);
55 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
57 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
58 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
59 MODULE_LICENSE("GPL");
61 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
66 case ni_gpct_variant_e_series:
69 case ni_gpct_variant_m_series:
70 return Gi_M_Series_Alternate_Sync_Bit;
72 case ni_gpct_variant_660x:
73 return Gi_660x_Alternate_Sync_Bit;
82 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
87 case ni_gpct_variant_e_series:
90 case ni_gpct_variant_m_series:
91 return Gi_M_Series_Prescale_X2_Bit;
93 case ni_gpct_variant_660x:
94 return Gi_660x_Prescale_X2_Bit;
103 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
108 case ni_gpct_variant_e_series:
111 case ni_gpct_variant_m_series:
112 return Gi_M_Series_Prescale_X8_Bit;
114 case ni_gpct_variant_660x:
115 return Gi_660x_Prescale_X8_Bit;
124 static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
129 case ni_gpct_variant_e_series:
132 case ni_gpct_variant_m_series:
133 return Gi_M_Series_HW_Arm_Select_Mask;
135 case ni_gpct_variant_660x:
136 return Gi_660x_HW_Arm_Select_Mask;
145 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
146 enum ni_660x_clock_source {
147 NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
148 NI_660x_Source_Pin_i_Clock = 0x1,
149 NI_660x_Next_Gate_Clock = 0xa,
150 NI_660x_Timebase_2_Clock = 0x12, /* 100KHz */
151 NI_660x_Next_TC_Clock = 0x13,
152 NI_660x_Timebase_3_Clock = 0x1e, /* 80MHz */
153 NI_660x_Logic_Low_Clock = 0x1f,
155 static const unsigned ni_660x_max_rtsi_channel = 6;
156 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
158 BUG_ON(n > ni_660x_max_rtsi_channel);
162 static const unsigned ni_660x_max_source_pin = 7;
163 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
165 BUG_ON(n > ni_660x_max_source_pin);
169 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
170 enum ni_m_series_clock_source {
171 NI_M_Series_Timebase_1_Clock = 0x0, /* 20MHz */
172 NI_M_Series_Timebase_2_Clock = 0x12, /* 100KHz */
173 NI_M_Series_Next_TC_Clock = 0x13,
174 NI_M_Series_Next_Gate_Clock = 0x14, /* when Gi_Src_SubSelect = 0 */
175 NI_M_Series_PXI_Star_Trigger_Clock = 0x14, /* when Gi_Src_SubSelect = 1 */
176 NI_M_Series_PXI10_Clock = 0x1d,
177 NI_M_Series_Timebase_3_Clock = 0x1e, /* 80MHz, when Gi_Src_SubSelect = 0 */
178 NI_M_Series_Analog_Trigger_Out_Clock = 0x1e, /* when Gi_Src_SubSelect = 1 */
179 NI_M_Series_Logic_Low_Clock = 0x1f,
181 static const unsigned ni_m_series_max_pfi_channel = 15;
182 static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
184 BUG_ON(n > ni_m_series_max_pfi_channel);
191 static const unsigned ni_m_series_max_rtsi_channel = 7;
192 static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
194 BUG_ON(n > ni_m_series_max_rtsi_channel);
201 enum ni_660x_gate_select {
202 NI_660x_Source_Pin_i_Gate_Select = 0x0,
203 NI_660x_Gate_Pin_i_Gate_Select = 0x1,
204 NI_660x_Next_SRC_Gate_Select = 0xa,
205 NI_660x_Next_Out_Gate_Select = 0x14,
206 NI_660x_Logic_Low_Gate_Select = 0x1f,
208 static const unsigned ni_660x_max_gate_pin = 7;
209 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
211 BUG_ON(n > ni_660x_max_gate_pin);
215 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
217 BUG_ON(n > ni_660x_max_rtsi_channel);
221 enum ni_m_series_gate_select {
222 NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
223 NI_M_Series_AI_START2_Gate_Select = 0x12,
224 NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
225 NI_M_Series_Next_Out_Gate_Select = 0x14,
226 NI_M_Series_AI_START1_Gate_Select = 0x1c,
227 NI_M_Series_Next_SRC_Gate_Select = 0x1d,
228 NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
229 NI_M_Series_Logic_Low_Gate_Select = 0x1f,
231 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
233 BUG_ON(n > ni_m_series_max_rtsi_channel);
239 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
241 BUG_ON(n > ni_m_series_max_pfi_channel);
247 static inline unsigned Gi_Source_Select_Bits(unsigned source)
249 return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
252 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
254 return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
257 enum ni_660x_second_gate_select {
258 NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
259 NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
260 NI_660x_Next_SRC_Second_Gate_Select = 0xa,
261 NI_660x_Next_Out_Second_Gate_Select = 0x14,
262 NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
263 NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
265 static const unsigned ni_660x_max_up_down_pin = 7;
266 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
268 BUG_ON(n > ni_660x_max_up_down_pin);
272 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
274 BUG_ON(n > ni_660x_max_rtsi_channel);
278 static const unsigned int counter_status_mask =
279 COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
281 static int __init ni_tio_init_module(void)
286 module_init(ni_tio_init_module);
288 static void __exit ni_tio_cleanup_module(void)
292 module_exit(ni_tio_cleanup_module);
294 struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device *dev,
295 void (*write_register) (struct
304 unsigned (*read_register)
305 (struct ni_gpct *counter,
306 enum ni_gpct_register reg),
307 enum ni_gpct_variant variant,
308 unsigned num_counters)
312 struct ni_gpct_device *counter_dev =
313 kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
314 if (counter_dev == NULL)
316 counter_dev->dev = dev;
317 counter_dev->write_register = write_register;
318 counter_dev->read_register = read_register;
319 counter_dev->variant = variant;
320 spin_lock_init(&counter_dev->regs_lock);
321 BUG_ON(num_counters == 0);
322 counter_dev->counters =
323 kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
324 if (counter_dev->counters == NULL) {
328 for (i = 0; i < num_counters; ++i) {
329 counter_dev->counters[i].counter_dev = counter_dev;
330 spin_lock_init(&counter_dev->counters[i].lock);
332 counter_dev->num_counters = num_counters;
335 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
337 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
339 if (counter_dev->counters == NULL)
341 kfree(counter_dev->counters);
344 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
346 static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
349 switch (counter_dev->variant) {
350 case ni_gpct_variant_e_series:
353 case ni_gpct_variant_m_series:
354 case ni_gpct_variant_660x:
364 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
366 write_register(counter, Gi_Reset_Bit(counter->counter_index),
367 NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
370 void ni_tio_init_counter(struct ni_gpct *counter)
372 struct ni_gpct_device *counter_dev = counter->counter_dev;
374 ni_tio_reset_count_and_disarm(counter);
375 /* initialize counter registers */
376 counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
378 write_register(counter,
380 regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
381 NITIO_Gi_Autoincrement_Reg(counter->counter_index));
382 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
383 ~0, Gi_Synchronize_Gate_Bit);
384 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
386 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
387 write_register(counter,
389 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
390 NITIO_Gi_LoadA_Reg(counter->counter_index));
391 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
392 write_register(counter,
394 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
395 NITIO_Gi_LoadB_Reg(counter->counter_index));
396 ni_tio_set_bits(counter,
397 NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
399 if (ni_tio_counting_mode_registers_present(counter_dev)) {
400 ni_tio_set_bits(counter,
401 NITIO_Gi_Counting_Mode_Reg(counter->
405 if (ni_tio_second_gate_registers_present(counter_dev)) {
407 regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
409 write_register(counter,
411 regs[NITIO_Gi_Second_Gate_Reg
412 (counter->counter_index)],
413 NITIO_Gi_Second_Gate_Reg(counter->
416 ni_tio_set_bits(counter,
417 NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
419 ni_tio_set_bits(counter,
420 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
423 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
425 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
427 unsigned int status = 0;
428 const unsigned bits = read_register(counter,
429 NITIO_Gxx_Status_Reg(counter->
431 if (bits & Gi_Armed_Bit(counter->counter_index)) {
432 status |= COMEDI_COUNTER_ARMED;
433 if (bits & Gi_Counting_Bit(counter->counter_index))
434 status |= COMEDI_COUNTER_COUNTING;
439 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
441 struct ni_gpct_device *counter_dev = counter->counter_dev;
442 const unsigned counting_mode_reg =
443 NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
444 static const uint64_t min_normal_sync_period_ps = 25000;
445 const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
446 ni_tio_generic_clock_src_select
449 if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
452 switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
453 case Gi_Counting_Mode_QuadratureX1_Bits:
454 case Gi_Counting_Mode_QuadratureX2_Bits:
455 case Gi_Counting_Mode_QuadratureX4_Bits:
456 case Gi_Counting_Mode_Sync_Source_Bits:
462 /* It's not clear what we should do if clock_period is unknown, so we are not
463 using the alt sync bit in that case, but allow the caller to decide by using the
464 force_alt_sync parameter. */
465 if (force_alt_sync ||
466 (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
467 ni_tio_set_bits(counter, counting_mode_reg,
468 Gi_Alternate_Sync_Bit(counter_dev->variant),
469 Gi_Alternate_Sync_Bit(counter_dev->variant));
471 ni_tio_set_bits(counter, counting_mode_reg,
472 Gi_Alternate_Sync_Bit(counter_dev->variant),
477 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
479 struct ni_gpct_device *counter_dev = counter->counter_dev;
480 unsigned mode_reg_mask;
481 unsigned mode_reg_values;
482 unsigned input_select_bits = 0;
483 /* these bits map directly on to the mode register */
484 static const unsigned mode_reg_direct_mask =
485 NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
486 NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
487 NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
488 NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
490 mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
491 mode_reg_values = mode & mode_reg_direct_mask;
492 switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
493 case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
495 case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
496 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
498 case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
499 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
500 mode_reg_mask |= Gi_Gating_Mode_Mask;
501 mode_reg_values |= Gi_Level_Gating_Bits;
506 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
507 mode_reg_mask, mode_reg_values);
509 if (ni_tio_counting_mode_registers_present(counter_dev)) {
510 unsigned counting_mode_bits = 0;
511 counting_mode_bits |=
512 (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
513 Gi_Counting_Mode_Mask;
514 counting_mode_bits |=
515 ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
516 Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
517 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
518 counting_mode_bits |= Gi_Index_Mode_Bit;
519 ni_tio_set_bits(counter,
520 NITIO_Gi_Counting_Mode_Reg(counter->
522 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
523 Gi_Index_Mode_Bit, counting_mode_bits);
524 ni_tio_set_sync_mode(counter, 0);
527 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
529 (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
532 if (mode & NI_GPCT_OR_GATE_BIT)
533 input_select_bits |= Gi_Or_Gate_Bit;
534 if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
535 input_select_bits |= Gi_Output_Polarity_Bit;
536 ni_tio_set_bits(counter,
537 NITIO_Gi_Input_Select_Reg(counter->counter_index),
538 Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
539 Gi_Output_Polarity_Bit, input_select_bits);
544 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
546 struct ni_gpct_device *counter_dev = counter->counter_dev;
548 unsigned command_transient_bits = 0;
551 switch (start_trigger) {
552 case NI_GPCT_ARM_IMMEDIATE:
553 command_transient_bits |= Gi_Arm_Bit;
555 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
556 command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
561 if (ni_tio_counting_mode_registers_present(counter_dev)) {
562 unsigned counting_mode_bits = 0;
564 switch (start_trigger) {
565 case NI_GPCT_ARM_IMMEDIATE:
566 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
569 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
570 /* pass-through the least significant bits so we can figure out what select later */
571 unsigned hw_arm_select_bits =
573 Gi_HW_Arm_Select_Shift) &
574 Gi_HW_Arm_Select_Mask
575 (counter_dev->variant);
577 counting_mode_bits |=
578 Gi_HW_Arm_Enable_Bit |
585 ni_tio_set_bits(counter,
586 NITIO_Gi_Counting_Mode_Reg
587 (counter->counter_index),
588 Gi_HW_Arm_Select_Mask
589 (counter_dev->variant) |
590 Gi_HW_Arm_Enable_Bit,
594 command_transient_bits |= Gi_Disarm_Bit;
596 ni_tio_set_bits_transient(counter,
597 NITIO_Gi_Command_Reg(counter->counter_index),
598 0, 0, command_transient_bits);
601 EXPORT_SYMBOL_GPL(ni_tio_arm);
603 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
605 unsigned ni_660x_clock;
607 const unsigned clock_select_bits =
608 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
610 switch (clock_select_bits) {
611 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
612 ni_660x_clock = NI_660x_Timebase_1_Clock;
614 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
615 ni_660x_clock = NI_660x_Timebase_2_Clock;
617 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
618 ni_660x_clock = NI_660x_Timebase_3_Clock;
620 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
621 ni_660x_clock = NI_660x_Logic_Low_Clock;
623 case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
624 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
626 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
627 ni_660x_clock = NI_660x_Next_Gate_Clock;
629 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
630 ni_660x_clock = NI_660x_Next_TC_Clock;
633 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
634 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
635 ni_660x_clock = NI_660x_RTSI_Clock(i);
639 if (i <= ni_660x_max_rtsi_channel)
641 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
642 if (clock_select_bits ==
643 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
644 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
648 if (i <= ni_660x_max_source_pin)
654 return Gi_Source_Select_Bits(ni_660x_clock);
657 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
659 unsigned ni_m_series_clock;
661 const unsigned clock_select_bits =
662 clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
663 switch (clock_select_bits) {
664 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
665 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
667 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
668 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
670 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
671 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
673 case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
674 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
676 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
677 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
679 case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
680 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
682 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
683 ni_m_series_clock = NI_M_Series_PXI10_Clock;
685 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
686 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
688 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
689 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
692 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
693 if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
694 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
698 if (i <= ni_m_series_max_rtsi_channel)
700 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
701 if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
702 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
706 if (i <= ni_m_series_max_pfi_channel)
708 printk(KERN_ERR "invalid clock source 0x%lx\n",
709 (unsigned long)clock_source);
711 ni_m_series_clock = 0;
714 return Gi_Source_Select_Bits(ni_m_series_clock);
717 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
718 unsigned int clock_source)
720 struct ni_gpct_device *counter_dev = counter->counter_dev;
721 const unsigned second_gate_reg =
722 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
724 if (counter_dev->variant != ni_gpct_variant_m_series)
726 switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
727 /* Gi_Source_Subselect is zero */
728 case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
729 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
730 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
732 /* Gi_Source_Subselect is one */
733 case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
734 case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
735 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
737 /* Gi_Source_Subselect doesn't matter */
742 write_register(counter, counter_dev->regs[second_gate_reg],
746 static int ni_tio_set_clock_src(struct ni_gpct *counter,
747 unsigned int clock_source,
748 unsigned int period_ns)
750 struct ni_gpct_device *counter_dev = counter->counter_dev;
751 unsigned input_select_bits = 0;
752 static const uint64_t pico_per_nano = 1000;
754 /*FIXME: validate clock source */
755 switch (counter_dev->variant) {
756 case ni_gpct_variant_660x:
757 input_select_bits |= ni_660x_source_select_bits(clock_source);
759 case ni_gpct_variant_e_series:
760 case ni_gpct_variant_m_series:
762 ni_m_series_source_select_bits(clock_source);
768 if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
769 input_select_bits |= Gi_Source_Polarity_Bit;
770 ni_tio_set_bits(counter,
771 NITIO_Gi_Input_Select_Reg(counter->counter_index),
772 Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
774 ni_tio_set_source_subselect(counter, clock_source);
775 if (ni_tio_counting_mode_registers_present(counter_dev)) {
776 const unsigned prescaling_mode =
777 clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
778 unsigned counting_mode_bits = 0;
780 switch (prescaling_mode) {
781 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
783 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
784 counting_mode_bits |=
785 Gi_Prescale_X2_Bit(counter_dev->variant);
787 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
788 counting_mode_bits |=
789 Gi_Prescale_X8_Bit(counter_dev->variant);
795 ni_tio_set_bits(counter,
796 NITIO_Gi_Counting_Mode_Reg(counter->
798 Gi_Prescale_X2_Bit(counter_dev->variant) |
799 Gi_Prescale_X8_Bit(counter_dev->variant),
802 counter->clock_period_ps = pico_per_nano * period_ns;
803 ni_tio_set_sync_mode(counter, 0);
807 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
809 struct ni_gpct_device *counter_dev = counter->counter_dev;
810 const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter,
811 NITIO_Gi_Counting_Mode_Reg
816 if (ni_tio_get_soft_copy(counter,
817 NITIO_Gi_Input_Select_Reg
818 (counter->counter_index)) &
819 Gi_Source_Polarity_Bit)
820 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
821 if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
822 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
823 if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
824 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
828 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
830 struct ni_gpct_device *counter_dev = counter->counter_dev;
831 const unsigned second_gate_reg =
832 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
833 unsigned clock_source = 0;
835 const unsigned input_select = (ni_tio_get_soft_copy(counter,
836 NITIO_Gi_Input_Select_Reg
837 (counter->counter_index))
838 & Gi_Source_Select_Mask) >>
839 Gi_Source_Select_Shift;
841 switch (input_select) {
842 case NI_M_Series_Timebase_1_Clock:
843 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
845 case NI_M_Series_Timebase_2_Clock:
846 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
848 case NI_M_Series_Timebase_3_Clock:
849 if (counter_dev->regs[second_gate_reg] &
850 Gi_Source_Subselect_Bit)
852 NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
854 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
856 case NI_M_Series_Logic_Low_Clock:
857 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
859 case NI_M_Series_Next_Gate_Clock:
860 if (counter_dev->regs[second_gate_reg] &
861 Gi_Source_Subselect_Bit)
862 clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
864 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
866 case NI_M_Series_PXI10_Clock:
867 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
869 case NI_M_Series_Next_TC_Clock:
870 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
873 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
874 if (input_select == NI_M_Series_RTSI_Clock(i)) {
875 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
879 if (i <= ni_m_series_max_rtsi_channel)
881 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
882 if (input_select == NI_M_Series_PFI_Clock(i)) {
883 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
887 if (i <= ni_m_series_max_pfi_channel)
892 clock_source |= ni_tio_clock_src_modifiers(counter);
896 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
898 unsigned clock_source = 0;
900 const unsigned input_select = (ni_tio_get_soft_copy(counter,
901 NITIO_Gi_Input_Select_Reg
902 (counter->counter_index))
903 & Gi_Source_Select_Mask) >>
904 Gi_Source_Select_Shift;
906 switch (input_select) {
907 case NI_660x_Timebase_1_Clock:
908 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
910 case NI_660x_Timebase_2_Clock:
911 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
913 case NI_660x_Timebase_3_Clock:
914 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
916 case NI_660x_Logic_Low_Clock:
917 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
919 case NI_660x_Source_Pin_i_Clock:
920 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
922 case NI_660x_Next_Gate_Clock:
923 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
925 case NI_660x_Next_TC_Clock:
926 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
929 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
930 if (input_select == NI_660x_RTSI_Clock(i)) {
931 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
935 if (i <= ni_660x_max_rtsi_channel)
937 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
938 if (input_select == NI_660x_Source_Pin_Clock(i)) {
940 NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
944 if (i <= ni_660x_max_source_pin)
949 clock_source |= ni_tio_clock_src_modifiers(counter);
953 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
955 switch (counter->counter_dev->variant) {
956 case ni_gpct_variant_e_series:
957 case ni_gpct_variant_m_series:
958 return ni_m_series_clock_src_select(counter);
960 case ni_gpct_variant_660x:
961 return ni_660x_clock_src_select(counter);
970 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
971 unsigned generic_clock_source)
973 uint64_t clock_period_ps;
975 switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
976 case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
977 clock_period_ps = 50000;
979 case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
980 clock_period_ps = 10000000;
982 case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
983 clock_period_ps = 12500;
985 case NI_GPCT_PXI10_CLOCK_SRC_BITS:
986 clock_period_ps = 100000;
989 /* clock period is specified by user with prescaling already taken into account. */
990 return counter->clock_period_ps;
994 switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
995 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
997 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
998 clock_period_ps *= 2;
1000 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1001 clock_period_ps *= 8;
1007 return clock_period_ps;
1010 static void ni_tio_get_clock_src(struct ni_gpct *counter,
1011 unsigned int *clock_source,
1012 unsigned int *period_ns)
1014 static const unsigned pico_per_nano = 1000;
1016 *clock_source = ni_tio_generic_clock_src_select(counter);
1017 temp64 = ni_tio_clock_period_ps(counter, *clock_source);
1018 do_div(temp64, pico_per_nano);
1019 *period_ns = temp64;
1022 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
1023 unsigned int gate_source)
1025 const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
1026 unsigned mode_values = 0;
1028 if (gate_source & CR_INVERT)
1029 mode_values |= Gi_Gate_Polarity_Bit;
1030 if (gate_source & CR_EDGE)
1031 mode_values |= Gi_Rising_Edge_Gating_Bits;
1033 mode_values |= Gi_Level_Gating_Bits;
1034 ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
1035 mode_mask, mode_values);
1038 static int ni_660x_set_first_gate(struct ni_gpct *counter,
1039 unsigned int gate_source)
1041 const unsigned selected_gate = CR_CHAN(gate_source);
1042 /* bits of selected_gate that may be meaningful to input select register */
1043 const unsigned selected_gate_mask = 0x1f;
1044 unsigned ni_660x_gate_select;
1047 switch (selected_gate) {
1048 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1049 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1051 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1052 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1053 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1054 case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1055 ni_660x_gate_select = selected_gate & selected_gate_mask;
1058 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1059 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1060 ni_660x_gate_select =
1061 selected_gate & selected_gate_mask;
1065 if (i <= ni_660x_max_rtsi_channel)
1067 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1068 if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
1069 ni_660x_gate_select =
1070 selected_gate & selected_gate_mask;
1074 if (i <= ni_660x_max_gate_pin)
1079 ni_tio_set_bits(counter,
1080 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1081 Gi_Gate_Select_Mask,
1082 Gi_Gate_Select_Bits(ni_660x_gate_select));
1086 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
1087 unsigned int gate_source)
1089 const unsigned selected_gate = CR_CHAN(gate_source);
1090 /* bits of selected_gate that may be meaningful to input select register */
1091 const unsigned selected_gate_mask = 0x1f;
1092 unsigned ni_m_series_gate_select;
1095 switch (selected_gate) {
1096 case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1097 case NI_GPCT_AI_START2_GATE_SELECT:
1098 case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1099 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1100 case NI_GPCT_AI_START1_GATE_SELECT:
1101 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1102 case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1103 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1104 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1107 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1108 if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1109 ni_m_series_gate_select =
1110 selected_gate & selected_gate_mask;
1114 if (i <= ni_m_series_max_rtsi_channel)
1116 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1117 if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
1118 ni_m_series_gate_select =
1119 selected_gate & selected_gate_mask;
1123 if (i <= ni_m_series_max_pfi_channel)
1128 ni_tio_set_bits(counter,
1129 NITIO_Gi_Input_Select_Reg(counter->counter_index),
1130 Gi_Gate_Select_Mask,
1131 Gi_Gate_Select_Bits(ni_m_series_gate_select));
1135 static int ni_660x_set_second_gate(struct ni_gpct *counter,
1136 unsigned int gate_source)
1138 struct ni_gpct_device *counter_dev = counter->counter_dev;
1139 const unsigned second_gate_reg =
1140 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1141 const unsigned selected_second_gate = CR_CHAN(gate_source);
1142 /* bits of second_gate that may be meaningful to second gate register */
1143 static const unsigned selected_second_gate_mask = 0x1f;
1144 unsigned ni_660x_second_gate_select;
1147 switch (selected_second_gate) {
1148 case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1149 case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1150 case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1151 case NI_GPCT_NEXT_OUT_GATE_SELECT:
1152 case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1153 ni_660x_second_gate_select =
1154 selected_second_gate & selected_second_gate_mask;
1156 case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1157 ni_660x_second_gate_select =
1158 NI_660x_Next_SRC_Second_Gate_Select;
1161 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1162 if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1163 ni_660x_second_gate_select =
1164 selected_second_gate &
1165 selected_second_gate_mask;
1169 if (i <= ni_660x_max_rtsi_channel)
1171 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1172 if (selected_second_gate ==
1173 NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1174 ni_660x_second_gate_select =
1175 selected_second_gate &
1176 selected_second_gate_mask;
1180 if (i <= ni_660x_max_up_down_pin)
1185 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1186 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1187 counter_dev->regs[second_gate_reg] |=
1188 Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
1189 write_register(counter, counter_dev->regs[second_gate_reg],
1194 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
1195 unsigned int gate_source)
1197 struct ni_gpct_device *counter_dev = counter->counter_dev;
1198 const unsigned second_gate_reg =
1199 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1200 const unsigned selected_second_gate = CR_CHAN(gate_source);
1201 /* bits of second_gate that may be meaningful to second gate register */
1202 static const unsigned selected_second_gate_mask = 0x1f;
1203 unsigned ni_m_series_second_gate_select;
1205 /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1206 the bits through for now. */
1207 switch (selected_second_gate) {
1209 ni_m_series_second_gate_select =
1210 selected_second_gate & selected_second_gate_mask;
1213 counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1214 counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1215 counter_dev->regs[second_gate_reg] |=
1216 Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1217 write_register(counter, counter_dev->regs[second_gate_reg],
1222 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
1223 unsigned int gate_source)
1225 struct ni_gpct_device *counter_dev = counter->counter_dev;
1226 const unsigned second_gate_reg =
1227 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1229 switch (gate_index) {
1231 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1232 ni_tio_set_bits(counter,
1233 NITIO_Gi_Mode_Reg(counter->
1235 Gi_Gating_Mode_Mask,
1236 Gi_Gating_Disabled_Bits);
1239 ni_tio_set_first_gate_modifiers(counter, gate_source);
1240 switch (counter_dev->variant) {
1241 case ni_gpct_variant_e_series:
1242 case ni_gpct_variant_m_series:
1243 return ni_m_series_set_first_gate(counter, gate_source);
1245 case ni_gpct_variant_660x:
1246 return ni_660x_set_first_gate(counter, gate_source);
1254 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1256 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1257 counter_dev->regs[second_gate_reg] &=
1258 ~Gi_Second_Gate_Mode_Bit;
1259 write_register(counter,
1260 counter_dev->regs[second_gate_reg],
1264 if (gate_source & CR_INVERT) {
1265 counter_dev->regs[second_gate_reg] |=
1266 Gi_Second_Gate_Polarity_Bit;
1268 counter_dev->regs[second_gate_reg] &=
1269 ~Gi_Second_Gate_Polarity_Bit;
1271 switch (counter_dev->variant) {
1272 case ni_gpct_variant_m_series:
1273 return ni_m_series_set_second_gate(counter,
1276 case ni_gpct_variant_660x:
1277 return ni_660x_set_second_gate(counter, gate_source);
1290 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1292 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1293 unsigned int source)
1295 struct ni_gpct_device *counter_dev = counter->counter_dev;
1297 if (counter_dev->variant == ni_gpct_variant_m_series) {
1298 unsigned int abz_reg, shift, mask;
1300 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1302 case NI_GPCT_SOURCE_ENCODER_A:
1305 case NI_GPCT_SOURCE_ENCODER_B:
1308 case NI_GPCT_SOURCE_ENCODER_Z:
1315 mask = 0x1f << shift;
1316 if (source > 0x1f) {
1320 counter_dev->regs[abz_reg] &= ~mask;
1321 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1322 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1323 /* printk("%s %x %d %d\n", __func__, counter_dev->regs[abz_reg], index, source); */
1329 static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
1330 ni_660x_gate_select)
1334 switch (ni_660x_gate_select) {
1335 case NI_660x_Source_Pin_i_Gate_Select:
1336 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1338 case NI_660x_Gate_Pin_i_Gate_Select:
1339 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1341 case NI_660x_Next_SRC_Gate_Select:
1342 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1344 case NI_660x_Next_Out_Gate_Select:
1345 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1347 case NI_660x_Logic_Low_Gate_Select:
1348 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1351 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1352 if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
1353 return NI_GPCT_RTSI_GATE_SELECT(i);
1357 if (i <= ni_660x_max_rtsi_channel)
1359 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1360 if (ni_660x_gate_select ==
1361 NI_660x_Gate_Pin_Gate_Select(i)) {
1362 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1366 if (i <= ni_660x_max_gate_pin)
1374 static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
1375 ni_m_series_gate_select)
1379 switch (ni_m_series_gate_select) {
1380 case NI_M_Series_Timestamp_Mux_Gate_Select:
1381 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1383 case NI_M_Series_AI_START2_Gate_Select:
1384 return NI_GPCT_AI_START2_GATE_SELECT;
1386 case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1387 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1389 case NI_M_Series_Next_Out_Gate_Select:
1390 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1392 case NI_M_Series_AI_START1_Gate_Select:
1393 return NI_GPCT_AI_START1_GATE_SELECT;
1395 case NI_M_Series_Next_SRC_Gate_Select:
1396 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1398 case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1399 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1401 case NI_M_Series_Logic_Low_Gate_Select:
1402 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1405 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1406 if (ni_m_series_gate_select ==
1407 NI_M_Series_RTSI_Gate_Select(i)) {
1408 return NI_GPCT_RTSI_GATE_SELECT(i);
1412 if (i <= ni_m_series_max_rtsi_channel)
1414 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1415 if (ni_m_series_gate_select ==
1416 NI_M_Series_PFI_Gate_Select(i)) {
1417 return NI_GPCT_PFI_GATE_SELECT(i);
1421 if (i <= ni_m_series_max_pfi_channel)
1429 static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
1430 ni_660x_gate_select)
1434 switch (ni_660x_gate_select) {
1435 case NI_660x_Source_Pin_i_Second_Gate_Select:
1436 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1438 case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1439 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1441 case NI_660x_Next_SRC_Second_Gate_Select:
1442 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1444 case NI_660x_Next_Out_Second_Gate_Select:
1445 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1447 case NI_660x_Selected_Gate_Second_Gate_Select:
1448 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1450 case NI_660x_Logic_Low_Second_Gate_Select:
1451 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1454 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1455 if (ni_660x_gate_select ==
1456 NI_660x_RTSI_Second_Gate_Select(i)) {
1457 return NI_GPCT_RTSI_GATE_SELECT(i);
1461 if (i <= ni_660x_max_rtsi_channel)
1463 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1464 if (ni_660x_gate_select ==
1465 NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
1466 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1470 if (i <= ni_660x_max_up_down_pin)
1478 static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
1479 ni_m_series_gate_select)
1481 /*FIXME: the second gate sources for the m series are undocumented, so we just return
1482 * the raw bits for now. */
1483 switch (ni_m_series_gate_select) {
1485 return ni_m_series_gate_select;
1491 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1492 unsigned int *gate_source)
1494 struct ni_gpct_device *counter_dev = counter->counter_dev;
1495 const unsigned mode_bits = ni_tio_get_soft_copy(counter,
1499 const unsigned second_gate_reg =
1500 NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1501 unsigned gate_select_bits;
1503 switch (gate_index) {
1505 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1506 Gi_Gating_Disabled_Bits) {
1507 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1511 (ni_tio_get_soft_copy(counter,
1512 NITIO_Gi_Input_Select_Reg
1513 (counter->counter_index)) &
1514 Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1516 switch (counter_dev->variant) {
1517 case ni_gpct_variant_e_series:
1518 case ni_gpct_variant_m_series:
1520 ni_m_series_first_gate_to_generic_gate_source
1523 case ni_gpct_variant_660x:
1525 ni_660x_first_gate_to_generic_gate_source
1532 if (mode_bits & Gi_Gate_Polarity_Bit)
1533 *gate_source |= CR_INVERT;
1534 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1535 *gate_source |= CR_EDGE;
1538 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1539 || (counter_dev->regs[second_gate_reg] &
1540 Gi_Second_Gate_Mode_Bit)
1542 *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1546 (counter_dev->regs[second_gate_reg] &
1547 Gi_Second_Gate_Select_Mask) >>
1548 Gi_Second_Gate_Select_Shift;
1550 switch (counter_dev->variant) {
1551 case ni_gpct_variant_e_series:
1552 case ni_gpct_variant_m_series:
1554 ni_m_series_second_gate_to_generic_gate_source
1557 case ni_gpct_variant_660x:
1559 ni_660x_second_gate_to_generic_gate_source
1566 if (counter_dev->regs[second_gate_reg] &
1567 Gi_Second_Gate_Polarity_Bit) {
1568 *gate_source |= CR_INVERT;
1570 /* second gate can't have edge/level mode set independently */
1571 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1572 *gate_source |= CR_EDGE;
1581 int ni_tio_insn_config(struct ni_gpct *counter,
1582 struct comedi_insn *insn, unsigned int *data)
1585 case INSN_CONFIG_SET_COUNTER_MODE:
1586 return ni_tio_set_counter_mode(counter, data[1]);
1588 case INSN_CONFIG_ARM:
1589 return ni_tio_arm(counter, 1, data[1]);
1591 case INSN_CONFIG_DISARM:
1592 ni_tio_arm(counter, 0, 0);
1595 case INSN_CONFIG_GET_COUNTER_STATUS:
1596 data[1] = ni_tio_counter_status(counter);
1597 data[2] = counter_status_mask;
1600 case INSN_CONFIG_SET_CLOCK_SRC:
1601 return ni_tio_set_clock_src(counter, data[1], data[2]);
1603 case INSN_CONFIG_GET_CLOCK_SRC:
1604 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1607 case INSN_CONFIG_SET_GATE_SRC:
1608 return ni_tio_set_gate_src(counter, data[1], data[2]);
1610 case INSN_CONFIG_GET_GATE_SRC:
1611 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1613 case INSN_CONFIG_SET_OTHER_SRC:
1614 return ni_tio_set_other_src(counter, data[1], data[2]);
1616 case INSN_CONFIG_RESET:
1617 ni_tio_reset_count_and_disarm(counter);
1625 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1627 int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
1630 struct ni_gpct_device *counter_dev = counter->counter_dev;
1631 const unsigned channel = CR_CHAN(insn->chanspec);
1632 unsigned first_read;
1633 unsigned second_read;
1634 unsigned correct_read;
1640 ni_tio_set_bits(counter,
1641 NITIO_Gi_Command_Reg(counter->counter_index),
1642 Gi_Save_Trace_Bit, 0);
1643 ni_tio_set_bits(counter,
1644 NITIO_Gi_Command_Reg(counter->counter_index),
1645 Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1646 /* The count doesn't get latched until the next clock edge, so it is possible the count
1647 may change (once) while we are reading. Since the read of the SW_Save_Reg isn't
1648 atomic (apparently even when it's a 32 bit register according to 660x docs),
1649 we need to read twice and make sure the reading hasn't changed. If it has,
1650 a third read will be correct since the count value will definitely have latched by then. */
1652 read_register(counter,
1653 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1655 read_register(counter,
1656 NITIO_Gi_SW_Save_Reg(counter->counter_index));
1657 if (first_read != second_read)
1659 read_register(counter,
1660 NITIO_Gi_SW_Save_Reg(counter->
1663 correct_read = first_read;
1664 data[0] = correct_read;
1670 regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
1675 regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
1680 EXPORT_SYMBOL_GPL(ni_tio_rinsn);
1682 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1684 const unsigned bits = read_register(counter,
1685 NITIO_Gxx_Status_Reg(counter->
1688 if (bits & Gi_Next_Load_Source_Bit(counter->counter_index))
1689 return NITIO_Gi_LoadB_Reg(counter->counter_index);
1691 return NITIO_Gi_LoadA_Reg(counter->counter_index);
1694 int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
1697 struct ni_gpct_device *counter_dev = counter->counter_dev;
1698 const unsigned channel = CR_CHAN(insn->chanspec);
1705 /* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */
1706 /* Don't disturb load source select, just use whichever load register is already selected. */
1707 load_reg = ni_tio_next_load_register(counter);
1708 write_register(counter, data[0], load_reg);
1709 ni_tio_set_bits_transient(counter,
1710 NITIO_Gi_Command_Reg(counter->
1713 /* restore state of load reg to whatever the user set last set it to */
1714 write_register(counter, counter_dev->regs[load_reg], load_reg);
1717 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
1719 write_register(counter, data[0],
1720 NITIO_Gi_LoadA_Reg(counter->counter_index));
1723 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
1725 write_register(counter, data[0],
1726 NITIO_Gi_LoadB_Reg(counter->counter_index));
1734 EXPORT_SYMBOL_GPL(ni_tio_winsn);