drivers/staging/comedi/drivers/ni_tio.c

   1 /*
   2   comedi/drivers/ni_tio.c
   3   Support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16 */
  17
  18 /*
  19 Driver: ni_tio
  20 Description: National Instruments general purpose counters
  21 Devices:
  22 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  23         Herman.Bruyninckx@mech.kuleuven.ac.be,
  24         Wim.Meeussen@mech.kuleuven.ac.be,
  25         Klaas.Gadeyne@mech.kuleuven.ac.be,
  26         Frank Mori Hess <fmhess@users.sourceforge.net>
  27 Updated: Thu Nov 16 09:50:32 EST 2006
  28 Status: works
  29
  30 This module is not used directly by end-users.  Rather, it
  31 is used by other drivers (for example ni_660x and ni_pcimio)
  32 to provide support for NI's general purpose counters.  It was
  33 originally based on the counter code from ni_660x.c and
  34 ni_mio_common.c.
  35
  36 References:
  37 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  38 DAQ 6601/6602 User Manual (NI 322137B-01)
  39 340934b.pdf  DAQ-STC reference manual
  40
  41 */
  42 /*
  43 TODO:
  44         Support use of both banks X and Y
  45 */
  46
  47 #include <linux/module.h>
  48 #include <linux/slab.h>
  49
  50 #include "ni_tio_internal.h"
  51
  52 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
  53                                        unsigned generic_clock_source);
  54 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter);
  55
  56 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
  57 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
  58 MODULE_LICENSE("GPL");
  59
  60 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Alternate_Sync_Bit(enum
  61                                                                    ni_gpct_variant
  62                                                                    variant)
  63 {
  64         switch (variant) {
  65         case ni_gpct_variant_e_series:
  66                 return 0;
  67                 break;
  68         case ni_gpct_variant_m_series:
  69                 return Gi_M_Series_Alternate_Sync_Bit;
  70                 break;
  71         case ni_gpct_variant_660x:
  72                 return Gi_660x_Alternate_Sync_Bit;
  73                 break;
  74         default:
  75                 BUG();
  76                 break;
  77         }
  78         return 0;
  79 }
  80
  81 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X2_Bit(enum
  82                                                                 ni_gpct_variant
  83                                                                 variant)
  84 {
  85         switch (variant) {
  86         case ni_gpct_variant_e_series:
  87                 return 0;
  88                 break;
  89         case ni_gpct_variant_m_series:
  90                 return Gi_M_Series_Prescale_X2_Bit;
  91                 break;
  92         case ni_gpct_variant_660x:
  93                 return Gi_660x_Prescale_X2_Bit;
  94                 break;
  95         default:
  96                 BUG();
  97                 break;
  98         }
  99         return 0;
 100 }
 101
 102 static inline enum Gi_Counting_Mode_Reg_Bits Gi_Prescale_X8_Bit(enum
 103                                                                 ni_gpct_variant
 104                                                                 variant)
 105 {
 106         switch (variant) {
 107         case ni_gpct_variant_e_series:
 108                 return 0;
 109                 break;
 110         case ni_gpct_variant_m_series:
 111                 return Gi_M_Series_Prescale_X8_Bit;
 112                 break;
 113         case ni_gpct_variant_660x:
 114                 return Gi_660x_Prescale_X8_Bit;
 115                 break;
 116         default:
 117                 BUG();
 118                 break;
 119         }
 120         return 0;
 121 }
 122
 123 static inline enum Gi_Counting_Mode_Reg_Bits Gi_HW_Arm_Select_Mask(enum
 124                                                                    ni_gpct_variant
 125                                                                    variant)
 126 {
 127         switch (variant) {
 128         case ni_gpct_variant_e_series:
 129                 return 0;
 130                 break;
 131         case ni_gpct_variant_m_series:
 132                 return Gi_M_Series_HW_Arm_Select_Mask;
 133                 break;
 134         case ni_gpct_variant_660x:
 135                 return Gi_660x_HW_Arm_Select_Mask;
 136                 break;
 137         default:
 138                 BUG();
 139                 break;
 140         }
 141         return 0;
 142 }
 143
 144 /* clock sources for ni_660x boards, get bits with Gi_Source_Select_Bits() */
 145 enum ni_660x_clock_source {
 146         NI_660x_Timebase_1_Clock = 0x0, /* 20MHz */
 147         NI_660x_Source_Pin_i_Clock = 0x1,
 148         NI_660x_Next_Gate_Clock = 0xa,
 149         NI_660x_Timebase_2_Clock = 0x12,        /* 100KHz */
 150         NI_660x_Next_TC_Clock = 0x13,
 151         NI_660x_Timebase_3_Clock = 0x1e,        /* 80MHz */
 152         NI_660x_Logic_Low_Clock = 0x1f,
 153 };
 154 static const unsigned ni_660x_max_rtsi_channel = 6;
 155 static inline unsigned NI_660x_RTSI_Clock(unsigned n)
 156 {
 157         BUG_ON(n > ni_660x_max_rtsi_channel);
 158         return 0xb + n;
 159 }
 160
 161 static const unsigned ni_660x_max_source_pin = 7;
 162 static inline unsigned NI_660x_Source_Pin_Clock(unsigned n)
 163 {
 164         BUG_ON(n > ni_660x_max_source_pin);
 165         return 0x2 + n;
 166 }
 167
 168 /* clock sources for ni e and m series boards, get bits with Gi_Source_Select_Bits() */
 169 enum ni_m_series_clock_source {
 170         NI_M_Series_Timebase_1_Clock = 0x0,     /* 20MHz */
 171         NI_M_Series_Timebase_2_Clock = 0x12,    /* 100KHz */
 172         NI_M_Series_Next_TC_Clock = 0x13,
 173         NI_M_Series_Next_Gate_Clock = 0x14,     /* when Gi_Src_SubSelect = 0 */
 174         NI_M_Series_PXI_Star_Trigger_Clock = 0x14,      /* when Gi_Src_SubSelect = 1 */
 175         NI_M_Series_PXI10_Clock = 0x1d,
 176         NI_M_Series_Timebase_3_Clock = 0x1e,    /* 80MHz, when Gi_Src_SubSelect = 0 */
 177         NI_M_Series_Analog_Trigger_Out_Clock = 0x1e,    /* when Gi_Src_SubSelect = 1 */
 178         NI_M_Series_Logic_Low_Clock = 0x1f,
 179 };
 180 static const unsigned ni_m_series_max_pfi_channel = 15;
 181 static inline unsigned NI_M_Series_PFI_Clock(unsigned n)
 182 {
 183         BUG_ON(n > ni_m_series_max_pfi_channel);
 184         if (n < 10)
 185                 return 1 + n;
 186         else
 187                 return 0xb + n;
 188 }
 189
 190 static const unsigned ni_m_series_max_rtsi_channel = 7;
 191 static inline unsigned NI_M_Series_RTSI_Clock(unsigned n)
 192 {
 193         BUG_ON(n > ni_m_series_max_rtsi_channel);
 194         if (n == 7)
 195                 return 0x1b;
 196         else
 197                 return 0xb + n;
 198 }
 199
 200 enum ni_660x_gate_select {
 201         NI_660x_Source_Pin_i_Gate_Select = 0x0,
 202         NI_660x_Gate_Pin_i_Gate_Select = 0x1,
 203         NI_660x_Next_SRC_Gate_Select = 0xa,
 204         NI_660x_Next_Out_Gate_Select = 0x14,
 205         NI_660x_Logic_Low_Gate_Select = 0x1f,
 206 };
 207 static const unsigned ni_660x_max_gate_pin = 7;
 208 static inline unsigned NI_660x_Gate_Pin_Gate_Select(unsigned n)
 209 {
 210         BUG_ON(n > ni_660x_max_gate_pin);
 211         return 0x2 + n;
 212 }
 213
 214 static inline unsigned NI_660x_RTSI_Gate_Select(unsigned n)
 215 {
 216         BUG_ON(n > ni_660x_max_rtsi_channel);
 217         return 0xb + n;
 218 }
 219
 220 enum ni_m_series_gate_select {
 221         NI_M_Series_Timestamp_Mux_Gate_Select = 0x0,
 222         NI_M_Series_AI_START2_Gate_Select = 0x12,
 223         NI_M_Series_PXI_Star_Trigger_Gate_Select = 0x13,
 224         NI_M_Series_Next_Out_Gate_Select = 0x14,
 225         NI_M_Series_AI_START1_Gate_Select = 0x1c,
 226         NI_M_Series_Next_SRC_Gate_Select = 0x1d,
 227         NI_M_Series_Analog_Trigger_Out_Gate_Select = 0x1e,
 228         NI_M_Series_Logic_Low_Gate_Select = 0x1f,
 229 };
 230 static inline unsigned NI_M_Series_RTSI_Gate_Select(unsigned n)
 231 {
 232         BUG_ON(n > ni_m_series_max_rtsi_channel);
 233         if (n == 7)
 234                 return 0x1b;
 235         return 0xb + n;
 236 }
 237
 238 static inline unsigned NI_M_Series_PFI_Gate_Select(unsigned n)
 239 {
 240         BUG_ON(n > ni_m_series_max_pfi_channel);
 241         if (n < 10)
 242                 return 1 + n;
 243         return 0xb + n;
 244 }
 245
 246 static inline unsigned Gi_Source_Select_Bits(unsigned source)
 247 {
 248         return (source << Gi_Source_Select_Shift) & Gi_Source_Select_Mask;
 249 }
 250
 251 static inline unsigned Gi_Gate_Select_Bits(unsigned gate_select)
 252 {
 253         return (gate_select << Gi_Gate_Select_Shift) & Gi_Gate_Select_Mask;
 254 }
 255
 256 enum ni_660x_second_gate_select {
 257         NI_660x_Source_Pin_i_Second_Gate_Select = 0x0,
 258         NI_660x_Up_Down_Pin_i_Second_Gate_Select = 0x1,
 259         NI_660x_Next_SRC_Second_Gate_Select = 0xa,
 260         NI_660x_Next_Out_Second_Gate_Select = 0x14,
 261         NI_660x_Selected_Gate_Second_Gate_Select = 0x1e,
 262         NI_660x_Logic_Low_Second_Gate_Select = 0x1f,
 263 };
 264 static const unsigned ni_660x_max_up_down_pin = 7;
 265 static inline unsigned NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned n)
 266 {
 267         BUG_ON(n > ni_660x_max_up_down_pin);
 268         return 0x2 + n;
 269 }
 270
 271 static inline unsigned NI_660x_RTSI_Second_Gate_Select(unsigned n)
 272 {
 273         BUG_ON(n > ni_660x_max_rtsi_channel);
 274         return 0xb + n;
 275 }
 276
 277 static const unsigned int counter_status_mask =
 278         COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
 279
 280 static int __init ni_tio_init_module(void)
 281 {
 282         return 0;
 283 }
 284
 285 module_init(ni_tio_init_module);
 286
 287 static void __exit ni_tio_cleanup_module(void)
 288 {
 289 }
 290
 291 module_exit(ni_tio_cleanup_module);
 292
 293 struct ni_gpct_device *ni_gpct_device_construct(struct comedi_device *dev,
 294                                                 void (*write_register) (struct
 295                                                                         ni_gpct
 296                                                                         *
 297                                                                         counter,
 298                                                                         unsigned
 299                                                                         bits,
 300                                                                         enum
 301                                                                         ni_gpct_register
 302                                                                         reg),
 303                                                 unsigned (*read_register)
 304                                                 (struct ni_gpct *counter,
 305                                                  enum ni_gpct_register reg),
 306                                                 enum ni_gpct_variant variant,
 307                                                 unsigned num_counters)
 308 {
 309         unsigned i;
 310
 311         struct ni_gpct_device *counter_dev =
 312             kzalloc(sizeof(struct ni_gpct_device), GFP_KERNEL);
 313         if (counter_dev == NULL)
 314                 return NULL;
 315         counter_dev->dev = dev;
 316         counter_dev->write_register = write_register;
 317         counter_dev->read_register = read_register;
 318         counter_dev->variant = variant;
 319         spin_lock_init(&counter_dev->regs_lock);
 320         BUG_ON(num_counters == 0);
 321         counter_dev->counters =
 322             kzalloc(sizeof(struct ni_gpct) * num_counters, GFP_KERNEL);
 323         if (counter_dev->counters == NULL) {
 324                 kfree(counter_dev);
 325                 return NULL;
 326         }
 327         for (i = 0; i < num_counters; ++i) {
 328                 counter_dev->counters[i].counter_dev = counter_dev;
 329                 spin_lock_init(&counter_dev->counters[i].lock);
 330         }
 331         counter_dev->num_counters = num_counters;
 332         return counter_dev;
 333 }
 334 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
 335
 336 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
 337 {
 338         if (counter_dev->counters == NULL)
 339                 return;
 340         kfree(counter_dev->counters);
 341         kfree(counter_dev);
 342 }
 343 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
 344
 345 static int ni_tio_second_gate_registers_present(const struct ni_gpct_device
 346                                                 *counter_dev)
 347 {
 348         switch (counter_dev->variant) {
 349         case ni_gpct_variant_e_series:
 350                 return 0;
 351                 break;
 352         case ni_gpct_variant_m_series:
 353         case ni_gpct_variant_660x:
 354                 return 1;
 355                 break;
 356         default:
 357                 BUG();
 358                 break;
 359         }
 360         return 0;
 361 }
 362
 363 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 364 {
 365         write_register(counter, Gi_Reset_Bit(counter->counter_index),
 366                        NITIO_Gxx_Joint_Reset_Reg(counter->counter_index));
 367 }
 368
 369 void ni_tio_init_counter(struct ni_gpct *counter)
 370 {
 371         struct ni_gpct_device *counter_dev = counter->counter_dev;
 372
 373         ni_tio_reset_count_and_disarm(counter);
 374         /* initialize counter registers */
 375         counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] =
 376             0x0;
 377         write_register(counter,
 378                        counter_dev->
 379                        regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)],
 380                        NITIO_Gi_Autoincrement_Reg(counter->counter_index));
 381         ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
 382                         ~0, Gi_Synchronize_Gate_Bit);
 383         ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0,
 384                         0);
 385         counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0;
 386         write_register(counter,
 387                        counter_dev->
 388                        regs[NITIO_Gi_LoadA_Reg(counter->counter_index)],
 389                        NITIO_Gi_LoadA_Reg(counter->counter_index));
 390         counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0;
 391         write_register(counter,
 392                        counter_dev->
 393                        regs[NITIO_Gi_LoadB_Reg(counter->counter_index)],
 394                        NITIO_Gi_LoadB_Reg(counter->counter_index));
 395         ni_tio_set_bits(counter,
 396                         NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0,
 397                         0);
 398         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 399                 ni_tio_set_bits(counter,
 400                                 NITIO_Gi_Counting_Mode_Reg(counter->
 401                                                            counter_index), ~0,
 402                                 0);
 403         }
 404         if (ni_tio_second_gate_registers_present(counter_dev)) {
 405                 counter_dev->
 406                     regs[NITIO_Gi_Second_Gate_Reg(counter->counter_index)] =
 407                     0x0;
 408                 write_register(counter,
 409                                counter_dev->
 410                                regs[NITIO_Gi_Second_Gate_Reg
 411                                     (counter->counter_index)],
 412                                NITIO_Gi_Second_Gate_Reg(counter->
 413                                                         counter_index));
 414         }
 415         ni_tio_set_bits(counter,
 416                         NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0,
 417                         0x0);
 418         ni_tio_set_bits(counter,
 419                         NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
 420                         ~0, 0x0);
 421 }
 422 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
 423
 424 static unsigned int ni_tio_counter_status(struct ni_gpct *counter)
 425 {
 426         unsigned int status = 0;
 427         const unsigned bits = read_register(counter,
 428                                             NITIO_Gxx_Status_Reg(counter->
 429                                                                  counter_index));
 430         if (bits & Gi_Armed_Bit(counter->counter_index)) {
 431                 status |= COMEDI_COUNTER_ARMED;
 432                 if (bits & Gi_Counting_Bit(counter->counter_index))
 433                         status |= COMEDI_COUNTER_COUNTING;
 434         }
 435         return status;
 436 }
 437
 438 static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 439 {
 440         struct ni_gpct_device *counter_dev = counter->counter_dev;
 441         const unsigned counting_mode_reg =
 442             NITIO_Gi_Counting_Mode_Reg(counter->counter_index);
 443         static const uint64_t min_normal_sync_period_ps = 25000;
 444         const uint64_t clock_period_ps = ni_tio_clock_period_ps(counter,
 445                                                                 ni_tio_generic_clock_src_select
 446                                                                 (counter));
 447
 448         if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
 449                 return;
 450
 451         switch (ni_tio_get_soft_copy(counter, counting_mode_reg) & Gi_Counting_Mode_Mask) {
 452         case Gi_Counting_Mode_QuadratureX1_Bits:
 453         case Gi_Counting_Mode_QuadratureX2_Bits:
 454         case Gi_Counting_Mode_QuadratureX4_Bits:
 455         case Gi_Counting_Mode_Sync_Source_Bits:
 456                 force_alt_sync = 1;
 457                 break;
 458         default:
 459                 break;
 460         }
 461         /* It's not clear what we should do if clock_period is unknown, so we are not
 462            using the alt sync bit in that case, but allow the caller to decide by using the
 463            force_alt_sync parameter. */
 464         if (force_alt_sync ||
 465             (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
 466                 ni_tio_set_bits(counter, counting_mode_reg,
 467                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 468                                 Gi_Alternate_Sync_Bit(counter_dev->variant));
 469         } else {
 470                 ni_tio_set_bits(counter, counting_mode_reg,
 471                                 Gi_Alternate_Sync_Bit(counter_dev->variant),
 472                                 0x0);
 473         }
 474 }
 475
 476 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 477 {
 478         struct ni_gpct_device *counter_dev = counter->counter_dev;
 479         unsigned mode_reg_mask;
 480         unsigned mode_reg_values;
 481         unsigned input_select_bits = 0;
 482         /* these bits map directly on to the mode register */
 483         static const unsigned mode_reg_direct_mask =
 484             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 485             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 486             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 487             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 488
 489         mode_reg_mask = mode_reg_direct_mask | Gi_Reload_Source_Switching_Bit;
 490         mode_reg_values = mode & mode_reg_direct_mask;
 491         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 492         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 493                 break;
 494         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 495                 mode_reg_values |= Gi_Reload_Source_Switching_Bit;
 496                 break;
 497         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 498                 input_select_bits |= Gi_Gate_Select_Load_Source_Bit;
 499                 mode_reg_mask |= Gi_Gating_Mode_Mask;
 500                 mode_reg_values |= Gi_Level_Gating_Bits;
 501                 break;
 502         default:
 503                 break;
 504         }
 505         ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
 506                         mode_reg_mask, mode_reg_values);
 507
 508         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 509                 unsigned counting_mode_bits = 0;
 510                 counting_mode_bits |=
 511                     (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
 512                     Gi_Counting_Mode_Mask;
 513                 counting_mode_bits |=
 514                     ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
 515                      Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
 516                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 517                         counting_mode_bits |= Gi_Index_Mode_Bit;
 518                 ni_tio_set_bits(counter,
 519                                 NITIO_Gi_Counting_Mode_Reg(counter->
 520                                                            counter_index),
 521                                 Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
 522                                 Gi_Index_Mode_Bit, counting_mode_bits);
 523                 ni_tio_set_sync_mode(counter, 0);
 524         }
 525
 526         ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
 527                         Gi_Up_Down_Mask,
 528                         (mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT) <<
 529                         Gi_Up_Down_Shift);
 530
 531         if (mode & NI_GPCT_OR_GATE_BIT)
 532                 input_select_bits |= Gi_Or_Gate_Bit;
 533         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 534                 input_select_bits |= Gi_Output_Polarity_Bit;
 535         ni_tio_set_bits(counter,
 536                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
 537                         Gi_Gate_Select_Load_Source_Bit | Gi_Or_Gate_Bit |
 538                         Gi_Output_Polarity_Bit, input_select_bits);
 539
 540         return 0;
 541 }
 542
 543 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 544 {
 545         struct ni_gpct_device *counter_dev = counter->counter_dev;
 546
 547         unsigned command_transient_bits = 0;
 548
 549         if (arm) {
 550                 switch (start_trigger) {
 551                 case NI_GPCT_ARM_IMMEDIATE:
 552                         command_transient_bits |= Gi_Arm_Bit;
 553                         break;
 554                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 555                         command_transient_bits |= Gi_Arm_Bit | Gi_Arm_Copy_Bit;
 556                         break;
 557                 default:
 558                         break;
 559                 }
 560                 if (ni_tio_counting_mode_registers_present(counter_dev)) {
 561                         unsigned counting_mode_bits = 0;
 562
 563                         switch (start_trigger) {
 564                         case NI_GPCT_ARM_IMMEDIATE:
 565                         case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 566                                 break;
 567                         default:
 568                                 if (start_trigger & NI_GPCT_ARM_UNKNOWN) {
 569                                         /* pass-through the least significant bits so we can figure out what select later */
 570                                         unsigned hw_arm_select_bits =
 571                                             (start_trigger <<
 572                                              Gi_HW_Arm_Select_Shift) &
 573                                             Gi_HW_Arm_Select_Mask
 574                                             (counter_dev->variant);
 575
 576                                         counting_mode_bits |=
 577                                             Gi_HW_Arm_Enable_Bit |
 578                                             hw_arm_select_bits;
 579                                 } else {
 580                                         return -EINVAL;
 581                                 }
 582                                 break;
 583                         }
 584                         ni_tio_set_bits(counter,
 585                                         NITIO_Gi_Counting_Mode_Reg
 586                                         (counter->counter_index),
 587                                         Gi_HW_Arm_Select_Mask
 588                                         (counter_dev->variant) |
 589                                         Gi_HW_Arm_Enable_Bit,
 590                                         counting_mode_bits);
 591                 }
 592         } else {
 593                 command_transient_bits |= Gi_Disarm_Bit;
 594         }
 595         ni_tio_set_bits_transient(counter,
 596                                   NITIO_Gi_Command_Reg(counter->counter_index),
 597                                   0, 0, command_transient_bits);
 598         return 0;
 599 }
 600 EXPORT_SYMBOL_GPL(ni_tio_arm);
 601
 602 static unsigned ni_660x_source_select_bits(unsigned int clock_source)
 603 {
 604         unsigned ni_660x_clock;
 605         unsigned i;
 606         const unsigned clock_select_bits =
 607             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 608
 609         switch (clock_select_bits) {
 610         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 611                 ni_660x_clock = NI_660x_Timebase_1_Clock;
 612                 break;
 613         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 614                 ni_660x_clock = NI_660x_Timebase_2_Clock;
 615                 break;
 616         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 617                 ni_660x_clock = NI_660x_Timebase_3_Clock;
 618                 break;
 619         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 620                 ni_660x_clock = NI_660x_Logic_Low_Clock;
 621                 break;
 622         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 623                 ni_660x_clock = NI_660x_Source_Pin_i_Clock;
 624                 break;
 625         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 626                 ni_660x_clock = NI_660x_Next_Gate_Clock;
 627                 break;
 628         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 629                 ni_660x_clock = NI_660x_Next_TC_Clock;
 630                 break;
 631         default:
 632                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
 633                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 634                                 ni_660x_clock = NI_660x_RTSI_Clock(i);
 635                                 break;
 636                         }
 637                 }
 638                 if (i <= ni_660x_max_rtsi_channel)
 639                         break;
 640                 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
 641                         if (clock_select_bits ==
 642                             NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 643                                 ni_660x_clock = NI_660x_Source_Pin_Clock(i);
 644                                 break;
 645                         }
 646                 }
 647                 if (i <= ni_660x_max_source_pin)
 648                         break;
 649                 ni_660x_clock = 0;
 650                 BUG();
 651                 break;
 652         }
 653         return Gi_Source_Select_Bits(ni_660x_clock);
 654 }
 655
 656 static unsigned ni_m_series_source_select_bits(unsigned int clock_source)
 657 {
 658         unsigned ni_m_series_clock;
 659         unsigned i;
 660         const unsigned clock_select_bits =
 661             clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 662         switch (clock_select_bits) {
 663         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 664                 ni_m_series_clock = NI_M_Series_Timebase_1_Clock;
 665                 break;
 666         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 667                 ni_m_series_clock = NI_M_Series_Timebase_2_Clock;
 668                 break;
 669         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 670                 ni_m_series_clock = NI_M_Series_Timebase_3_Clock;
 671                 break;
 672         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 673                 ni_m_series_clock = NI_M_Series_Logic_Low_Clock;
 674                 break;
 675         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 676                 ni_m_series_clock = NI_M_Series_Next_Gate_Clock;
 677                 break;
 678         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 679                 ni_m_series_clock = NI_M_Series_Next_TC_Clock;
 680                 break;
 681         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 682                 ni_m_series_clock = NI_M_Series_PXI10_Clock;
 683                 break;
 684         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 685                 ni_m_series_clock = NI_M_Series_PXI_Star_Trigger_Clock;
 686                 break;
 687         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 688                 ni_m_series_clock = NI_M_Series_Analog_Trigger_Out_Clock;
 689                 break;
 690         default:
 691                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
 692                         if (clock_select_bits == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 693                                 ni_m_series_clock = NI_M_Series_RTSI_Clock(i);
 694                                 break;
 695                         }
 696                 }
 697                 if (i <= ni_m_series_max_rtsi_channel)
 698                         break;
 699                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
 700                         if (clock_select_bits == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 701                                 ni_m_series_clock = NI_M_Series_PFI_Clock(i);
 702                                 break;
 703                         }
 704                 }
 705                 if (i <= ni_m_series_max_pfi_channel)
 706                         break;
 707                 printk(KERN_ERR "invalid clock source 0x%lx\n",
 708                        (unsigned long)clock_source);
 709                 BUG();
 710                 ni_m_series_clock = 0;
 711                 break;
 712         }
 713         return Gi_Source_Select_Bits(ni_m_series_clock);
 714 };
 715
 716 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 717                                         unsigned int clock_source)
 718 {
 719         struct ni_gpct_device *counter_dev = counter->counter_dev;
 720         const unsigned second_gate_reg =
 721             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
 722
 723         if (counter_dev->variant != ni_gpct_variant_m_series)
 724                 return;
 725         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 726                 /* Gi_Source_Subselect is zero */
 727         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 728         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 729                 counter_dev->regs[second_gate_reg] &= ~Gi_Source_Subselect_Bit;
 730                 break;
 731                 /* Gi_Source_Subselect is one */
 732         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 733         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 734                 counter_dev->regs[second_gate_reg] |= Gi_Source_Subselect_Bit;
 735                 break;
 736                 /* Gi_Source_Subselect doesn't matter */
 737         default:
 738                 return;
 739                 break;
 740         }
 741         write_register(counter, counter_dev->regs[second_gate_reg],
 742                        second_gate_reg);
 743 }
 744
 745 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 746                                 unsigned int clock_source,
 747                                 unsigned int period_ns)
 748 {
 749         struct ni_gpct_device *counter_dev = counter->counter_dev;
 750         unsigned input_select_bits = 0;
 751         static const uint64_t pico_per_nano = 1000;
 752
 753 /*FIXME: validate clock source */
 754         switch (counter_dev->variant) {
 755         case ni_gpct_variant_660x:
 756                 input_select_bits |= ni_660x_source_select_bits(clock_source);
 757                 break;
 758         case ni_gpct_variant_e_series:
 759         case ni_gpct_variant_m_series:
 760                 input_select_bits |=
 761                     ni_m_series_source_select_bits(clock_source);
 762                 break;
 763         default:
 764                 BUG();
 765                 break;
 766         }
 767         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 768                 input_select_bits |= Gi_Source_Polarity_Bit;
 769         ni_tio_set_bits(counter,
 770                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
 771                         Gi_Source_Select_Mask | Gi_Source_Polarity_Bit,
 772                         input_select_bits);
 773         ni_tio_set_source_subselect(counter, clock_source);
 774         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 775                 const unsigned prescaling_mode =
 776                     clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK;
 777                 unsigned counting_mode_bits = 0;
 778
 779                 switch (prescaling_mode) {
 780                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 781                         break;
 782                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 783                         counting_mode_bits |=
 784                             Gi_Prescale_X2_Bit(counter_dev->variant);
 785                         break;
 786                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 787                         counting_mode_bits |=
 788                             Gi_Prescale_X8_Bit(counter_dev->variant);
 789                         break;
 790                 default:
 791                         return -EINVAL;
 792                         break;
 793                 }
 794                 ni_tio_set_bits(counter,
 795                                 NITIO_Gi_Counting_Mode_Reg(counter->
 796                                                            counter_index),
 797                                 Gi_Prescale_X2_Bit(counter_dev->variant) |
 798                                 Gi_Prescale_X8_Bit(counter_dev->variant),
 799                                 counting_mode_bits);
 800         }
 801         counter->clock_period_ps = pico_per_nano * period_ns;
 802         ni_tio_set_sync_mode(counter, 0);
 803         return 0;
 804 }
 805
 806 static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 807 {
 808         struct ni_gpct_device *counter_dev = counter->counter_dev;
 809         const unsigned counting_mode_bits = ni_tio_get_soft_copy(counter,
 810                                                                  NITIO_Gi_Counting_Mode_Reg
 811                                                                  (counter->
 812                                                                   counter_index));
 813         unsigned bits = 0;
 814
 815         if (ni_tio_get_soft_copy(counter,
 816                                  NITIO_Gi_Input_Select_Reg
 817                                  (counter->counter_index)) &
 818             Gi_Source_Polarity_Bit)
 819                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 820         if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
 821                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 822         if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
 823                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 824         return bits;
 825 }
 826
 827 static unsigned ni_m_series_clock_src_select(const struct ni_gpct *counter)
 828 {
 829         struct ni_gpct_device *counter_dev = counter->counter_dev;
 830         const unsigned second_gate_reg =
 831             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
 832         unsigned clock_source = 0;
 833         unsigned i;
 834         const unsigned input_select = (ni_tio_get_soft_copy(counter,
 835                                                             NITIO_Gi_Input_Select_Reg
 836                                                             (counter->counter_index))
 837                                        & Gi_Source_Select_Mask) >>
 838             Gi_Source_Select_Shift;
 839
 840         switch (input_select) {
 841         case NI_M_Series_Timebase_1_Clock:
 842                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 843                 break;
 844         case NI_M_Series_Timebase_2_Clock:
 845                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 846                 break;
 847         case NI_M_Series_Timebase_3_Clock:
 848                 if (counter_dev->regs[second_gate_reg] &
 849                     Gi_Source_Subselect_Bit)
 850                         clock_source =
 851                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 852                 else
 853                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 854                 break;
 855         case NI_M_Series_Logic_Low_Clock:
 856                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 857                 break;
 858         case NI_M_Series_Next_Gate_Clock:
 859                 if (counter_dev->regs[second_gate_reg] &
 860                     Gi_Source_Subselect_Bit)
 861                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 862                 else
 863                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 864                 break;
 865         case NI_M_Series_PXI10_Clock:
 866                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 867                 break;
 868         case NI_M_Series_Next_TC_Clock:
 869                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 870                 break;
 871         default:
 872                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
 873                         if (input_select == NI_M_Series_RTSI_Clock(i)) {
 874                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 875                                 break;
 876                         }
 877                 }
 878                 if (i <= ni_m_series_max_rtsi_channel)
 879                         break;
 880                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
 881                         if (input_select == NI_M_Series_PFI_Clock(i)) {
 882                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 883                                 break;
 884                         }
 885                 }
 886                 if (i <= ni_m_series_max_pfi_channel)
 887                         break;
 888                 BUG();
 889                 break;
 890         }
 891         clock_source |= ni_tio_clock_src_modifiers(counter);
 892         return clock_source;
 893 }
 894
 895 static unsigned ni_660x_clock_src_select(const struct ni_gpct *counter)
 896 {
 897         unsigned clock_source = 0;
 898         unsigned i;
 899         const unsigned input_select = (ni_tio_get_soft_copy(counter,
 900                                                             NITIO_Gi_Input_Select_Reg
 901                                                             (counter->counter_index))
 902                                        & Gi_Source_Select_Mask) >>
 903             Gi_Source_Select_Shift;
 904
 905         switch (input_select) {
 906         case NI_660x_Timebase_1_Clock:
 907                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 908                 break;
 909         case NI_660x_Timebase_2_Clock:
 910                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 911                 break;
 912         case NI_660x_Timebase_3_Clock:
 913                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 914                 break;
 915         case NI_660x_Logic_Low_Clock:
 916                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 917                 break;
 918         case NI_660x_Source_Pin_i_Clock:
 919                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 920                 break;
 921         case NI_660x_Next_Gate_Clock:
 922                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 923                 break;
 924         case NI_660x_Next_TC_Clock:
 925                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 926                 break;
 927         default:
 928                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
 929                         if (input_select == NI_660x_RTSI_Clock(i)) {
 930                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 931                                 break;
 932                         }
 933                 }
 934                 if (i <= ni_660x_max_rtsi_channel)
 935                         break;
 936                 for (i = 0; i <= ni_660x_max_source_pin; ++i) {
 937                         if (input_select == NI_660x_Source_Pin_Clock(i)) {
 938                                 clock_source =
 939                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 940                                 break;
 941                         }
 942                 }
 943                 if (i <= ni_660x_max_source_pin)
 944                         break;
 945                 BUG();
 946                 break;
 947         }
 948         clock_source |= ni_tio_clock_src_modifiers(counter);
 949         return clock_source;
 950 }
 951
 952 static unsigned ni_tio_generic_clock_src_select(const struct ni_gpct *counter)
 953 {
 954         switch (counter->counter_dev->variant) {
 955         case ni_gpct_variant_e_series:
 956         case ni_gpct_variant_m_series:
 957                 return ni_m_series_clock_src_select(counter);
 958                 break;
 959         case ni_gpct_variant_660x:
 960                 return ni_660x_clock_src_select(counter);
 961                 break;
 962         default:
 963                 BUG();
 964                 break;
 965         }
 966         return 0;
 967 }
 968
 969 static uint64_t ni_tio_clock_period_ps(const struct ni_gpct *counter,
 970                                        unsigned generic_clock_source)
 971 {
 972         uint64_t clock_period_ps;
 973
 974         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 975         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 976                 clock_period_ps = 50000;
 977                 break;
 978         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 979                 clock_period_ps = 10000000;
 980                 break;
 981         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 982                 clock_period_ps = 12500;
 983                 break;
 984         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 985                 clock_period_ps = 100000;
 986                 break;
 987         default:
 988                 /* clock period is specified by user with prescaling already taken into account. */
 989                 return counter->clock_period_ps;
 990                 break;
 991         }
 992
 993         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 994         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 995                 break;
 996         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 997                 clock_period_ps *= 2;
 998                 break;
 999         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
1000                 clock_period_ps *= 8;
1001                 break;
1002         default:
1003                 BUG();
1004                 break;
1005         }
1006         return clock_period_ps;
1007 }
1008
1009 static void ni_tio_get_clock_src(struct ni_gpct *counter,
1010                                  unsigned int *clock_source,
1011                                  unsigned int *period_ns)
1012 {
1013         static const unsigned pico_per_nano = 1000;
1014         uint64_t temp64;
1015         *clock_source = ni_tio_generic_clock_src_select(counter);
1016         temp64 = ni_tio_clock_period_ps(counter, *clock_source);
1017         do_div(temp64, pico_per_nano);
1018         *period_ns = temp64;
1019 }
1020
1021 static void ni_tio_set_first_gate_modifiers(struct ni_gpct *counter,
1022                                             unsigned int gate_source)
1023 {
1024         const unsigned mode_mask = Gi_Gate_Polarity_Bit | Gi_Gating_Mode_Mask;
1025         unsigned mode_values = 0;
1026
1027         if (gate_source & CR_INVERT)
1028                 mode_values |= Gi_Gate_Polarity_Bit;
1029         if (gate_source & CR_EDGE)
1030                 mode_values |= Gi_Rising_Edge_Gating_Bits;
1031         else
1032                 mode_values |= Gi_Level_Gating_Bits;
1033         ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index),
1034                         mode_mask, mode_values);
1035 }
1036
1037 static int ni_660x_set_first_gate(struct ni_gpct *counter,
1038                                   unsigned int gate_source)
1039 {
1040         const unsigned selected_gate = CR_CHAN(gate_source);
1041         /* bits of selected_gate that may be meaningful to input select register */
1042         const unsigned selected_gate_mask = 0x1f;
1043         unsigned ni_660x_gate_select;
1044         unsigned i;
1045
1046         switch (selected_gate) {
1047         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1048                 ni_660x_gate_select = NI_660x_Next_SRC_Gate_Select;
1049                 break;
1050         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1051         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1052         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1053         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
1054                 ni_660x_gate_select = selected_gate & selected_gate_mask;
1055                 break;
1056         default:
1057                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1058                         if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1059                                 ni_660x_gate_select =
1060                                     selected_gate & selected_gate_mask;
1061                                 break;
1062                         }
1063                 }
1064                 if (i <= ni_660x_max_rtsi_channel)
1065                         break;
1066                 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1067                         if (selected_gate == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
1068                                 ni_660x_gate_select =
1069                                     selected_gate & selected_gate_mask;
1070                                 break;
1071                         }
1072                 }
1073                 if (i <= ni_660x_max_gate_pin)
1074                         break;
1075                 return -EINVAL;
1076                 break;
1077         }
1078         ni_tio_set_bits(counter,
1079                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
1080                         Gi_Gate_Select_Mask,
1081                         Gi_Gate_Select_Bits(ni_660x_gate_select));
1082         return 0;
1083 }
1084
1085 static int ni_m_series_set_first_gate(struct ni_gpct *counter,
1086                                       unsigned int gate_source)
1087 {
1088         const unsigned selected_gate = CR_CHAN(gate_source);
1089         /* bits of selected_gate that may be meaningful to input select register */
1090         const unsigned selected_gate_mask = 0x1f;
1091         unsigned ni_m_series_gate_select;
1092         unsigned i;
1093
1094         switch (selected_gate) {
1095         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
1096         case NI_GPCT_AI_START2_GATE_SELECT:
1097         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
1098         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1099         case NI_GPCT_AI_START1_GATE_SELECT:
1100         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1101         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
1102         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1103                 ni_m_series_gate_select = selected_gate & selected_gate_mask;
1104                 break;
1105         default:
1106                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1107                         if (selected_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1108                                 ni_m_series_gate_select =
1109                                     selected_gate & selected_gate_mask;
1110                                 break;
1111                         }
1112                 }
1113                 if (i <= ni_m_series_max_rtsi_channel)
1114                         break;
1115                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1116                         if (selected_gate == NI_GPCT_PFI_GATE_SELECT(i)) {
1117                                 ni_m_series_gate_select =
1118                                     selected_gate & selected_gate_mask;
1119                                 break;
1120                         }
1121                 }
1122                 if (i <= ni_m_series_max_pfi_channel)
1123                         break;
1124                 return -EINVAL;
1125                 break;
1126         }
1127         ni_tio_set_bits(counter,
1128                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
1129                         Gi_Gate_Select_Mask,
1130                         Gi_Gate_Select_Bits(ni_m_series_gate_select));
1131         return 0;
1132 }
1133
1134 static int ni_660x_set_second_gate(struct ni_gpct *counter,
1135                                    unsigned int gate_source)
1136 {
1137         struct ni_gpct_device *counter_dev = counter->counter_dev;
1138         const unsigned second_gate_reg =
1139             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1140         const unsigned selected_second_gate = CR_CHAN(gate_source);
1141         /* bits of second_gate that may be meaningful to second gate register */
1142         static const unsigned selected_second_gate_mask = 0x1f;
1143         unsigned ni_660x_second_gate_select;
1144         unsigned i;
1145
1146         switch (selected_second_gate) {
1147         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
1148         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
1149         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
1150         case NI_GPCT_NEXT_OUT_GATE_SELECT:
1151         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
1152                 ni_660x_second_gate_select =
1153                     selected_second_gate & selected_second_gate_mask;
1154                 break;
1155         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
1156                 ni_660x_second_gate_select =
1157                     NI_660x_Next_SRC_Second_Gate_Select;
1158                 break;
1159         default:
1160                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1161                         if (selected_second_gate == NI_GPCT_RTSI_GATE_SELECT(i)) {
1162                                 ni_660x_second_gate_select =
1163                                     selected_second_gate &
1164                                     selected_second_gate_mask;
1165                                 break;
1166                         }
1167                 }
1168                 if (i <= ni_660x_max_rtsi_channel)
1169                         break;
1170                 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1171                         if (selected_second_gate ==
1172                             NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1173                                 ni_660x_second_gate_select =
1174                                     selected_second_gate &
1175                                     selected_second_gate_mask;
1176                                 break;
1177                         }
1178                 }
1179                 if (i <= ni_660x_max_up_down_pin)
1180                         break;
1181                 return -EINVAL;
1182                 break;
1183         }
1184         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1185         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1186         counter_dev->regs[second_gate_reg] |=
1187             Gi_Second_Gate_Select_Bits(ni_660x_second_gate_select);
1188         write_register(counter, counter_dev->regs[second_gate_reg],
1189                        second_gate_reg);
1190         return 0;
1191 }
1192
1193 static int ni_m_series_set_second_gate(struct ni_gpct *counter,
1194                                        unsigned int gate_source)
1195 {
1196         struct ni_gpct_device *counter_dev = counter->counter_dev;
1197         const unsigned second_gate_reg =
1198             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1199         const unsigned selected_second_gate = CR_CHAN(gate_source);
1200         /* bits of second_gate that may be meaningful to second gate register */
1201         static const unsigned selected_second_gate_mask = 0x1f;
1202         unsigned ni_m_series_second_gate_select;
1203
1204         /* FIXME: We don't know what the m-series second gate codes are, so we'll just pass
1205            the bits through for now. */
1206         switch (selected_second_gate) {
1207         default:
1208                 ni_m_series_second_gate_select =
1209                     selected_second_gate & selected_second_gate_mask;
1210                 break;
1211         }
1212         counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
1213         counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
1214         counter_dev->regs[second_gate_reg] |=
1215             Gi_Second_Gate_Select_Bits(ni_m_series_second_gate_select);
1216         write_register(counter, counter_dev->regs[second_gate_reg],
1217                        second_gate_reg);
1218         return 0;
1219 }
1220
1221 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
1222                         unsigned int gate_source)
1223 {
1224         struct ni_gpct_device *counter_dev = counter->counter_dev;
1225         const unsigned second_gate_reg =
1226             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1227
1228         switch (gate_index) {
1229         case 0:
1230                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1231                         ni_tio_set_bits(counter,
1232                                         NITIO_Gi_Mode_Reg(counter->
1233                                                           counter_index),
1234                                         Gi_Gating_Mode_Mask,
1235                                         Gi_Gating_Disabled_Bits);
1236                         return 0;
1237                 }
1238                 ni_tio_set_first_gate_modifiers(counter, gate_source);
1239                 switch (counter_dev->variant) {
1240                 case ni_gpct_variant_e_series:
1241                 case ni_gpct_variant_m_series:
1242                         return ni_m_series_set_first_gate(counter, gate_source);
1243                         break;
1244                 case ni_gpct_variant_660x:
1245                         return ni_660x_set_first_gate(counter, gate_source);
1246                         break;
1247                 default:
1248                         BUG();
1249                         break;
1250                 }
1251                 break;
1252         case 1:
1253                 if (ni_tio_second_gate_registers_present(counter_dev) == 0)
1254                         return -EINVAL;
1255                 if (CR_CHAN(gate_source) == NI_GPCT_DISABLED_GATE_SELECT) {
1256                         counter_dev->regs[second_gate_reg] &=
1257                             ~Gi_Second_Gate_Mode_Bit;
1258                         write_register(counter,
1259                                        counter_dev->regs[second_gate_reg],
1260                                        second_gate_reg);
1261                         return 0;
1262                 }
1263                 if (gate_source & CR_INVERT) {
1264                         counter_dev->regs[second_gate_reg] |=
1265                             Gi_Second_Gate_Polarity_Bit;
1266                 } else {
1267                         counter_dev->regs[second_gate_reg] &=
1268                             ~Gi_Second_Gate_Polarity_Bit;
1269                 }
1270                 switch (counter_dev->variant) {
1271                 case ni_gpct_variant_m_series:
1272                         return ni_m_series_set_second_gate(counter,
1273                                                            gate_source);
1274                         break;
1275                 case ni_gpct_variant_660x:
1276                         return ni_660x_set_second_gate(counter, gate_source);
1277                         break;
1278                 default:
1279                         BUG();
1280                         break;
1281                 }
1282                 break;
1283         default:
1284                 return -EINVAL;
1285                 break;
1286         }
1287         return 0;
1288 }
1289 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1290
1291 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned index,
1292                                 unsigned int source)
1293 {
1294         struct ni_gpct_device *counter_dev = counter->counter_dev;
1295
1296         if (counter_dev->variant == ni_gpct_variant_m_series) {
1297                 unsigned int abz_reg, shift, mask;
1298
1299                 abz_reg = NITIO_Gi_ABZ_Reg(counter->counter_index);
1300                 switch (index) {
1301                 case NI_GPCT_SOURCE_ENCODER_A:
1302                         shift = 10;
1303                         break;
1304                 case NI_GPCT_SOURCE_ENCODER_B:
1305                         shift = 5;
1306                         break;
1307                 case NI_GPCT_SOURCE_ENCODER_Z:
1308                         shift = 0;
1309                         break;
1310                 default:
1311                         return -EINVAL;
1312                         break;
1313                 }
1314                 mask = 0x1f << shift;
1315                 if (source > 0x1f) {
1316                         /* Disable gate */
1317                         source = 0x1f;
1318                 }
1319                 counter_dev->regs[abz_reg] &= ~mask;
1320                 counter_dev->regs[abz_reg] |= (source << shift) & mask;
1321                 write_register(counter, counter_dev->regs[abz_reg], abz_reg);
1322 /* printk("%s %x %d %d\n", __func__, counter_dev->regs[abz_reg], index, source); */
1323                 return 0;
1324         }
1325         return -EINVAL;
1326 }
1327
1328 static unsigned ni_660x_first_gate_to_generic_gate_source(unsigned
1329                                                           ni_660x_gate_select)
1330 {
1331         unsigned i;
1332
1333         switch (ni_660x_gate_select) {
1334         case NI_660x_Source_Pin_i_Gate_Select:
1335                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1336                 break;
1337         case NI_660x_Gate_Pin_i_Gate_Select:
1338                 return NI_GPCT_GATE_PIN_i_GATE_SELECT;
1339                 break;
1340         case NI_660x_Next_SRC_Gate_Select:
1341                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1342                 break;
1343         case NI_660x_Next_Out_Gate_Select:
1344                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1345                 break;
1346         case NI_660x_Logic_Low_Gate_Select:
1347                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1348                 break;
1349         default:
1350                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1351                         if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
1352                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1353                                 break;
1354                         }
1355                 }
1356                 if (i <= ni_660x_max_rtsi_channel)
1357                         break;
1358                 for (i = 0; i <= ni_660x_max_gate_pin; ++i) {
1359                         if (ni_660x_gate_select ==
1360                             NI_660x_Gate_Pin_Gate_Select(i)) {
1361                                 return NI_GPCT_GATE_PIN_GATE_SELECT(i);
1362                                 break;
1363                         }
1364                 }
1365                 if (i <= ni_660x_max_gate_pin)
1366                         break;
1367                 BUG();
1368                 break;
1369         }
1370         return 0;
1371 };
1372
1373 static unsigned ni_m_series_first_gate_to_generic_gate_source(unsigned
1374                                                               ni_m_series_gate_select)
1375 {
1376         unsigned i;
1377
1378         switch (ni_m_series_gate_select) {
1379         case NI_M_Series_Timestamp_Mux_Gate_Select:
1380                 return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1381                 break;
1382         case NI_M_Series_AI_START2_Gate_Select:
1383                 return NI_GPCT_AI_START2_GATE_SELECT;
1384                 break;
1385         case NI_M_Series_PXI_Star_Trigger_Gate_Select:
1386                 return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1387                 break;
1388         case NI_M_Series_Next_Out_Gate_Select:
1389                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1390                 break;
1391         case NI_M_Series_AI_START1_Gate_Select:
1392                 return NI_GPCT_AI_START1_GATE_SELECT;
1393                 break;
1394         case NI_M_Series_Next_SRC_Gate_Select:
1395                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1396                 break;
1397         case NI_M_Series_Analog_Trigger_Out_Gate_Select:
1398                 return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1399                 break;
1400         case NI_M_Series_Logic_Low_Gate_Select:
1401                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1402                 break;
1403         default:
1404                 for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
1405                         if (ni_m_series_gate_select ==
1406                             NI_M_Series_RTSI_Gate_Select(i)) {
1407                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1408                                 break;
1409                         }
1410                 }
1411                 if (i <= ni_m_series_max_rtsi_channel)
1412                         break;
1413                 for (i = 0; i <= ni_m_series_max_pfi_channel; ++i) {
1414                         if (ni_m_series_gate_select ==
1415                             NI_M_Series_PFI_Gate_Select(i)) {
1416                                 return NI_GPCT_PFI_GATE_SELECT(i);
1417                                 break;
1418                         }
1419                 }
1420                 if (i <= ni_m_series_max_pfi_channel)
1421                         break;
1422                 BUG();
1423                 break;
1424         }
1425         return 0;
1426 };
1427
1428 static unsigned ni_660x_second_gate_to_generic_gate_source(unsigned
1429                                                            ni_660x_gate_select)
1430 {
1431         unsigned i;
1432
1433         switch (ni_660x_gate_select) {
1434         case NI_660x_Source_Pin_i_Second_Gate_Select:
1435                 return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1436                 break;
1437         case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
1438                 return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1439                 break;
1440         case NI_660x_Next_SRC_Second_Gate_Select:
1441                 return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1442                 break;
1443         case NI_660x_Next_Out_Second_Gate_Select:
1444                 return NI_GPCT_NEXT_OUT_GATE_SELECT;
1445                 break;
1446         case NI_660x_Selected_Gate_Second_Gate_Select:
1447                 return NI_GPCT_SELECTED_GATE_GATE_SELECT;
1448                 break;
1449         case NI_660x_Logic_Low_Second_Gate_Select:
1450                 return NI_GPCT_LOGIC_LOW_GATE_SELECT;
1451                 break;
1452         default:
1453                 for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
1454                         if (ni_660x_gate_select ==
1455                             NI_660x_RTSI_Second_Gate_Select(i)) {
1456                                 return NI_GPCT_RTSI_GATE_SELECT(i);
1457                                 break;
1458                         }
1459                 }
1460                 if (i <= ni_660x_max_rtsi_channel)
1461                         break;
1462                 for (i = 0; i <= ni_660x_max_up_down_pin; ++i) {
1463                         if (ni_660x_gate_select ==
1464                             NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
1465                                 return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1466                                 break;
1467                         }
1468                 }
1469                 if (i <= ni_660x_max_up_down_pin)
1470                         break;
1471                 BUG();
1472                 break;
1473         }
1474         return 0;
1475 };
1476
1477 static unsigned ni_m_series_second_gate_to_generic_gate_source(unsigned
1478                                                                ni_m_series_gate_select)
1479 {
1480         /*FIXME: the second gate sources for the m series are undocumented, so we just return
1481          * the raw bits for now. */
1482         switch (ni_m_series_gate_select) {
1483         default:
1484                 return ni_m_series_gate_select;
1485                 break;
1486         }
1487         return 0;
1488 };
1489
1490 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned gate_index,
1491                                unsigned int *gate_source)
1492 {
1493         struct ni_gpct_device *counter_dev = counter->counter_dev;
1494         const unsigned mode_bits = ni_tio_get_soft_copy(counter,
1495                                                         NITIO_Gi_Mode_Reg
1496                                                         (counter->
1497                                                          counter_index));
1498         const unsigned second_gate_reg =
1499             NITIO_Gi_Second_Gate_Reg(counter->counter_index);
1500         unsigned gate_select_bits;
1501
1502         switch (gate_index) {
1503         case 0:
1504                 if ((mode_bits & Gi_Gating_Mode_Mask) ==
1505                     Gi_Gating_Disabled_Bits) {
1506                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1507                         return 0;
1508                 } else {
1509                         gate_select_bits =
1510                             (ni_tio_get_soft_copy(counter,
1511                                                   NITIO_Gi_Input_Select_Reg
1512                                                   (counter->counter_index)) &
1513                              Gi_Gate_Select_Mask) >> Gi_Gate_Select_Shift;
1514                 }
1515                 switch (counter_dev->variant) {
1516                 case ni_gpct_variant_e_series:
1517                 case ni_gpct_variant_m_series:
1518                         *gate_source =
1519                             ni_m_series_first_gate_to_generic_gate_source
1520                             (gate_select_bits);
1521                         break;
1522                 case ni_gpct_variant_660x:
1523                         *gate_source =
1524                             ni_660x_first_gate_to_generic_gate_source
1525                             (gate_select_bits);
1526                         break;
1527                 default:
1528                         BUG();
1529                         break;
1530                 }
1531                 if (mode_bits & Gi_Gate_Polarity_Bit)
1532                         *gate_source |= CR_INVERT;
1533                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1534                         *gate_source |= CR_EDGE;
1535                 break;
1536         case 1:
1537                 if ((mode_bits & Gi_Gating_Mode_Mask) == Gi_Gating_Disabled_Bits
1538                     || (counter_dev->regs[second_gate_reg] &
1539                         Gi_Second_Gate_Mode_Bit)
1540                     == 0) {
1541                         *gate_source = NI_GPCT_DISABLED_GATE_SELECT;
1542                         return 0;
1543                 } else {
1544                         gate_select_bits =
1545                             (counter_dev->regs[second_gate_reg] &
1546                              Gi_Second_Gate_Select_Mask) >>
1547                             Gi_Second_Gate_Select_Shift;
1548                 }
1549                 switch (counter_dev->variant) {
1550                 case ni_gpct_variant_e_series:
1551                 case ni_gpct_variant_m_series:
1552                         *gate_source =
1553                             ni_m_series_second_gate_to_generic_gate_source
1554                             (gate_select_bits);
1555                         break;
1556                 case ni_gpct_variant_660x:
1557                         *gate_source =
1558                             ni_660x_second_gate_to_generic_gate_source
1559                             (gate_select_bits);
1560                         break;
1561                 default:
1562                         BUG();
1563                         break;
1564                 }
1565                 if (counter_dev->regs[second_gate_reg] &
1566                     Gi_Second_Gate_Polarity_Bit) {
1567                         *gate_source |= CR_INVERT;
1568                 }
1569                 /* second gate can't have edge/level mode set independently */
1570                 if ((mode_bits & Gi_Gating_Mode_Mask) != Gi_Level_Gating_Bits)
1571                         *gate_source |= CR_EDGE;
1572                 break;
1573         default:
1574                 return -EINVAL;
1575                 break;
1576         }
1577         return 0;
1578 }
1579
1580 int ni_tio_insn_config(struct ni_gpct *counter,
1581                        struct comedi_insn *insn, unsigned int *data)
1582 {
1583         switch (data[0]) {
1584         case INSN_CONFIG_SET_COUNTER_MODE:
1585                 return ni_tio_set_counter_mode(counter, data[1]);
1586                 break;
1587         case INSN_CONFIG_ARM:
1588                 return ni_tio_arm(counter, 1, data[1]);
1589                 break;
1590         case INSN_CONFIG_DISARM:
1591                 ni_tio_arm(counter, 0, 0);
1592                 return 0;
1593                 break;
1594         case INSN_CONFIG_GET_COUNTER_STATUS:
1595                 data[1] = ni_tio_counter_status(counter);
1596                 data[2] = counter_status_mask;
1597                 return 0;
1598                 break;
1599         case INSN_CONFIG_SET_CLOCK_SRC:
1600                 return ni_tio_set_clock_src(counter, data[1], data[2]);
1601                 break;
1602         case INSN_CONFIG_GET_CLOCK_SRC:
1603                 ni_tio_get_clock_src(counter, &data[1], &data[2]);
1604                 return 0;
1605                 break;
1606         case INSN_CONFIG_SET_GATE_SRC:
1607                 return ni_tio_set_gate_src(counter, data[1], data[2]);
1608                 break;
1609         case INSN_CONFIG_GET_GATE_SRC:
1610                 return ni_tio_get_gate_src(counter, data[1], &data[2]);
1611                 break;
1612         case INSN_CONFIG_SET_OTHER_SRC:
1613                 return ni_tio_set_other_src(counter, data[1], data[2]);
1614                 break;
1615         case INSN_CONFIG_RESET:
1616                 ni_tio_reset_count_and_disarm(counter);
1617                 return 0;
1618                 break;
1619         default:
1620                 break;
1621         }
1622         return -EINVAL;
1623 }
1624 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1625
1626 int ni_tio_rinsn(struct ni_gpct *counter, struct comedi_insn *insn,
1627                  unsigned int *data)
1628 {
1629         struct ni_gpct_device *counter_dev = counter->counter_dev;
1630         const unsigned channel = CR_CHAN(insn->chanspec);
1631         unsigned first_read;
1632         unsigned second_read;
1633         unsigned correct_read;
1634
1635         if (insn->n < 1)
1636                 return 0;
1637         switch (channel) {
1638         case 0:
1639                 ni_tio_set_bits(counter,
1640                                 NITIO_Gi_Command_Reg(counter->counter_index),
1641                                 Gi_Save_Trace_Bit, 0);
1642                 ni_tio_set_bits(counter,
1643                                 NITIO_Gi_Command_Reg(counter->counter_index),
1644                                 Gi_Save_Trace_Bit, Gi_Save_Trace_Bit);
1645                 /* The count doesn't get latched until the next clock edge, so it is possible the count
1646                    may change (once) while we are reading.  Since the read of the SW_Save_Reg isn't
1647                    atomic (apparently even when it's a 32 bit register according to 660x docs),
1648                    we need to read twice and make sure the reading hasn't changed.  If it has,
1649                    a third read will be correct since the count value will definitely have latched by then. */
1650                 first_read =
1651                     read_register(counter,
1652                                   NITIO_Gi_SW_Save_Reg(counter->counter_index));
1653                 second_read =
1654                     read_register(counter,
1655                                   NITIO_Gi_SW_Save_Reg(counter->counter_index));
1656                 if (first_read != second_read)
1657                         correct_read =
1658                             read_register(counter,
1659                                           NITIO_Gi_SW_Save_Reg(counter->
1660                                                                counter_index));
1661                 else
1662                         correct_read = first_read;
1663                 data[0] = correct_read;
1664                 return 0;
1665                 break;
1666         case 1:
1667                 data[0] =
1668                     counter_dev->
1669                     regs[NITIO_Gi_LoadA_Reg(counter->counter_index)];
1670                 break;
1671         case 2:
1672                 data[0] =
1673                     counter_dev->
1674                     regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
1675                 break;
1676         }
1677         return 0;
1678 }
1679 EXPORT_SYMBOL_GPL(ni_tio_rinsn);
1680
1681 static unsigned ni_tio_next_load_register(struct ni_gpct *counter)
1682 {
1683         const unsigned bits = read_register(counter,
1684                                             NITIO_Gxx_Status_Reg(counter->
1685                                                                  counter_index));
1686
1687         if (bits & Gi_Next_Load_Source_Bit(counter->counter_index))
1688                 return NITIO_Gi_LoadB_Reg(counter->counter_index);
1689         else
1690                 return NITIO_Gi_LoadA_Reg(counter->counter_index);
1691 }
1692
1693 int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn,
1694                  unsigned int *data)
1695 {
1696         struct ni_gpct_device *counter_dev = counter->counter_dev;
1697         const unsigned channel = CR_CHAN(insn->chanspec);
1698         unsigned load_reg;
1699
1700         if (insn->n < 1)
1701                 return 0;
1702         switch (channel) {
1703         case 0:
1704                 /* Unsafe if counter is armed.  Should probably check status and return -EBUSY if armed. */
1705                 /* Don't disturb load source select, just use whichever load register is already selected. */
1706                 load_reg = ni_tio_next_load_register(counter);
1707                 write_register(counter, data[0], load_reg);
1708                 ni_tio_set_bits_transient(counter,
1709                                           NITIO_Gi_Command_Reg(counter->
1710                                                                counter_index),
1711                                           0, 0, Gi_Load_Bit);
1712                 /* restore state of load reg to whatever the user set last set it to */
1713                 write_register(counter, counter_dev->regs[load_reg], load_reg);
1714                 break;
1715         case 1:
1716                 counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] =
1717                     data[0];
1718                 write_register(counter, data[0],
1719                                NITIO_Gi_LoadA_Reg(counter->counter_index));
1720                 break;
1721         case 2:
1722                 counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] =
1723                     data[0];
1724                 write_register(counter, data[0],
1725                                NITIO_Gi_LoadB_Reg(counter->counter_index));
1726                 break;
1727         default:
1728                 return -EINVAL;
1729                 break;
1730         }
1731         return 0;
1732 }
1733 EXPORT_SYMBOL_GPL(ni_tio_winsn);