2 drivers/ni_tio_internal.h
3 Header file for NI general purpose counter support code (ni_tio.c and
6 COMEDI - Linux Control and Measurement Device Interface
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
19 #ifndef _COMEDI_NI_TIO_INTERNAL_H
20 #define _COMEDI_NI_TIO_INTERNAL_H
24 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
27 switch (counter_index) {
29 return NITIO_G0_Autoincrement_Reg;
32 return NITIO_G1_Autoincrement_Reg;
35 return NITIO_G2_Autoincrement_Reg;
38 return NITIO_G3_Autoincrement_Reg;
47 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
49 switch (counter_index) {
51 return NITIO_G0_Command_Reg;
54 return NITIO_G1_Command_Reg;
57 return NITIO_G2_Command_Reg;
60 return NITIO_G3_Command_Reg;
69 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
72 switch (counter_index) {
74 return NITIO_G0_Counting_Mode_Reg;
77 return NITIO_G1_Counting_Mode_Reg;
80 return NITIO_G2_Counting_Mode_Reg;
83 return NITIO_G3_Counting_Mode_Reg;
92 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
95 switch (counter_index) {
97 return NITIO_G0_Input_Select_Reg;
100 return NITIO_G1_Input_Select_Reg;
103 return NITIO_G2_Input_Select_Reg;
106 return NITIO_G3_Input_Select_Reg;
115 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
118 switch (counter_index) {
121 return NITIO_G01_Joint_Reset_Reg;
125 return NITIO_G23_Joint_Reset_Reg;
134 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
137 switch (counter_index) {
140 return NITIO_G01_Joint_Status1_Reg;
144 return NITIO_G23_Joint_Status1_Reg;
153 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
156 switch (counter_index) {
159 return NITIO_G01_Joint_Status2_Reg;
163 return NITIO_G23_Joint_Status2_Reg;
172 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
174 switch (counter_index) {
177 return NITIO_G01_Status_Reg;
181 return NITIO_G23_Status_Reg;
190 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
192 switch (counter_index) {
194 return NITIO_G0_LoadA_Reg;
197 return NITIO_G1_LoadA_Reg;
200 return NITIO_G2_LoadA_Reg;
203 return NITIO_G3_LoadA_Reg;
212 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
214 switch (counter_index) {
216 return NITIO_G0_LoadB_Reg;
219 return NITIO_G1_LoadB_Reg;
222 return NITIO_G2_LoadB_Reg;
225 return NITIO_G3_LoadB_Reg;
234 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
236 switch (counter_index) {
238 return NITIO_G0_Mode_Reg;
241 return NITIO_G1_Mode_Reg;
244 return NITIO_G2_Mode_Reg;
247 return NITIO_G3_Mode_Reg;
256 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
258 switch (counter_index) {
260 return NITIO_G0_SW_Save_Reg;
263 return NITIO_G1_SW_Save_Reg;
266 return NITIO_G2_SW_Save_Reg;
269 return NITIO_G3_SW_Save_Reg;
278 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
280 switch (counter_index) {
282 return NITIO_G0_Second_Gate_Reg;
285 return NITIO_G1_Second_Gate_Reg;
288 return NITIO_G2_Second_Gate_Reg;
291 return NITIO_G3_Second_Gate_Reg;
300 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
302 switch (counter_index) {
304 return NITIO_G0_DMA_Config_Reg;
307 return NITIO_G1_DMA_Config_Reg;
310 return NITIO_G2_DMA_Config_Reg;
313 return NITIO_G3_DMA_Config_Reg;
322 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
324 switch (counter_index) {
326 return NITIO_G0_DMA_Status_Reg;
329 return NITIO_G1_DMA_Status_Reg;
332 return NITIO_G2_DMA_Status_Reg;
335 return NITIO_G3_DMA_Status_Reg;
344 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
346 switch (counter_index) {
348 return NITIO_G0_ABZ_Reg;
351 return NITIO_G1_ABZ_Reg;
360 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(
363 switch (counter_index) {
365 return NITIO_G0_Interrupt_Acknowledge_Reg;
368 return NITIO_G1_Interrupt_Acknowledge_Reg;
371 return NITIO_G2_Interrupt_Acknowledge_Reg;
374 return NITIO_G3_Interrupt_Acknowledge_Reg;
383 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
385 switch (counter_index) {
387 return NITIO_G0_Status_Reg;
390 return NITIO_G1_Status_Reg;
393 return NITIO_G2_Status_Reg;
396 return NITIO_G3_Status_Reg;
405 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(
408 switch (counter_index) {
410 return NITIO_G0_Interrupt_Enable_Reg;
413 return NITIO_G1_Interrupt_Enable_Reg;
416 return NITIO_G2_Interrupt_Enable_Reg;
419 return NITIO_G3_Interrupt_Enable_Reg;
428 enum Gi_Auto_Increment_Reg_Bits {
429 Gi_Auto_Increment_Mask = 0xff
432 #define Gi_Up_Down_Shift 5
433 enum Gi_Command_Reg_Bits {
435 Gi_Save_Trace_Bit = 0x2,
437 Gi_Disarm_Bit = 0x10,
438 Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
439 Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
440 Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
441 Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
442 Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
443 Gi_Write_Switch_Bit = 0x80,
444 Gi_Synchronize_Gate_Bit = 0x100,
445 Gi_Little_Big_Endian_Bit = 0x200,
446 Gi_Bank_Switch_Start_Bit = 0x400,
447 Gi_Bank_Switch_Mode_Bit = 0x800,
448 Gi_Bank_Switch_Enable_Bit = 0x1000,
449 Gi_Arm_Copy_Bit = 0x2000,
450 Gi_Save_Trace_Copy_Bit = 0x4000,
451 Gi_Disarm_Copy_Bit = 0x8000
454 #define Gi_Index_Phase_Bitshift 5
455 #define Gi_HW_Arm_Select_Shift 8
456 enum Gi_Counting_Mode_Reg_Bits {
457 Gi_Counting_Mode_Mask = 0x7,
458 Gi_Counting_Mode_Normal_Bits = 0x0,
459 Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
460 Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
461 Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
462 Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
463 Gi_Counting_Mode_Sync_Source_Bits = 0x6,
464 Gi_Index_Mode_Bit = 0x10,
465 Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
466 Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
467 Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
468 Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
469 Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
470 /* from m-series example code, not documented in 660x register level
472 Gi_HW_Arm_Enable_Bit = 0x80,
473 /* from m-series example code, not documented in 660x register level
475 Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
476 Gi_660x_Prescale_X8_Bit = 0x1000,
477 Gi_M_Series_Prescale_X8_Bit = 0x2000,
478 Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
479 /* must be set for clocks over 40MHz, which includes synchronous
480 * counting and quadrature modes */
481 Gi_660x_Alternate_Sync_Bit = 0x2000,
482 Gi_M_Series_Alternate_Sync_Bit = 0x4000,
483 /* from m-series example code, not documented in 660x register level
485 Gi_660x_Prescale_X2_Bit = 0x4000,
486 Gi_M_Series_Prescale_X2_Bit = 0x8000,
489 #define Gi_Source_Select_Shift 2
490 #define Gi_Gate_Select_Shift 7
491 enum Gi_Input_Select_Bits {
492 Gi_Read_Acknowledges_Irq = 0x1, /* not present on 660x */
493 Gi_Write_Acknowledges_Irq = 0x2, /* not present on 660x */
494 Gi_Source_Select_Mask = 0x7c,
495 Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
496 Gi_Gate_Select_Load_Source_Bit = 0x1000,
497 Gi_Or_Gate_Bit = 0x2000,
498 Gi_Output_Polarity_Bit = 0x4000, /* set to invert */
499 Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
503 Gi_Gating_Mode_Mask = 0x3,
504 Gi_Gating_Disabled_Bits = 0x0,
505 Gi_Level_Gating_Bits = 0x1,
506 Gi_Rising_Edge_Gating_Bits = 0x2,
507 Gi_Falling_Edge_Gating_Bits = 0x3,
508 Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with
509 * rising edge gating mode */
510 Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
511 Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
512 Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
513 Gi_Edge_Gate_Starts_Bits = 0x10,
514 Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
515 Gi_Stop_Mode_Mask = 0x60,
516 Gi_Stop_on_Gate_Bits = 0x00,
517 Gi_Stop_on_Gate_or_TC_Bits = 0x20,
518 Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
519 Gi_Load_Source_Select_Bit = 0x80,
520 Gi_Output_Mode_Mask = 0x300,
521 Gi_Output_TC_Pulse_Bits = 0x100,
522 Gi_Output_TC_Toggle_Bits = 0x200,
523 Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
524 Gi_Counting_Once_Mask = 0xc00,
525 Gi_No_Hardware_Disarm_Bits = 0x000,
526 Gi_Disarm_at_TC_Bits = 0x400,
527 Gi_Disarm_at_Gate_Bits = 0x800,
528 Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
529 Gi_Loading_On_TC_Bit = 0x1000,
530 Gi_Gate_Polarity_Bit = 0x2000,
531 Gi_Loading_On_Gate_Bit = 0x4000,
532 Gi_Reload_Source_Switching_Bit = 0x8000
535 #define Gi_Second_Gate_Select_Shift 7
536 /*FIXME: m-series has a second gate subselect bit */
537 /*FIXME: m-series second gate sources are undocumented (by NI)*/
538 enum Gi_Second_Gate_Bits {
539 Gi_Second_Gate_Mode_Bit = 0x1,
540 Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
541 Gi_Second_Gate_Polarity_Bit = 0x2000,
542 Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */
543 Gi_Source_Subselect_Bit = 0x8000 /* m-series only */
545 static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
547 return (second_gate_select << Gi_Second_Gate_Select_Shift) &
548 Gi_Second_Gate_Select_Mask;
551 enum Gxx_Status_Bits {
554 G0_Counting_Bit = 0x4,
555 G1_Counting_Bit = 0x8,
556 G0_Next_Load_Source_Bit = 0x10,
557 G1_Next_Load_Source_Bit = 0x20,
558 G0_Stale_Data_Bit = 0x40,
559 G1_Stale_Data_Bit = 0x80,
560 G0_Armed_Bit = 0x100,
561 G1_Armed_Bit = 0x200,
562 G0_No_Load_Between_Gates_Bit = 0x400,
563 G1_No_Load_Between_Gates_Bit = 0x800,
564 G0_TC_Error_Bit = 0x1000,
565 G1_TC_Error_Bit = 0x2000,
566 G0_Gate_Error_Bit = 0x4000,
567 G1_Gate_Error_Bit = 0x8000
569 static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
571 if (counter_index % 2)
572 return G1_Counting_Bit;
573 return G0_Counting_Bit;
576 static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
578 if (counter_index % 2)
583 static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
586 if (counter_index % 2)
587 return G1_Next_Load_Source_Bit;
588 return G0_Next_Load_Source_Bit;
591 static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
593 if (counter_index % 2)
594 return G1_Stale_Data_Bit;
595 return G0_Stale_Data_Bit;
598 static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
600 if (counter_index % 2)
601 return G1_TC_Error_Bit;
602 return G0_TC_Error_Bit;
605 static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
607 if (counter_index % 2)
608 return G1_Gate_Error_Bit;
609 return G0_Gate_Error_Bit;
612 /* joint reset register bits */
613 static inline unsigned Gi_Reset_Bit(unsigned counter_index)
615 return 0x1 << (2 + (counter_index % 2));
618 enum Gxx_Joint_Status2_Bits {
621 G0_HW_Save_Bit = 0x1000,
622 G1_HW_Save_Bit = 0x2000,
623 G0_Permanent_Stale_Bit = 0x4000,
624 G1_Permanent_Stale_Bit = 0x8000
626 static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
629 if (counter_index % 2)
630 return G1_Permanent_Stale_Bit;
631 return G0_Permanent_Stale_Bit;
634 enum Gi_DMA_Config_Reg_Bits {
635 Gi_DMA_Enable_Bit = 0x1,
636 Gi_DMA_Write_Bit = 0x2,
640 enum Gi_DMA_Status_Reg_Bits {
641 Gi_DMA_Readbank_Bit = 0x2000,
642 Gi_DRQ_Error_Bit = 0x4000,
643 Gi_DRQ_Status_Bit = 0x8000
646 enum G02_Interrupt_Acknowledge_Bits {
647 G0_Gate_Error_Confirm_Bit = 0x20,
648 G0_TC_Error_Confirm_Bit = 0x40
650 enum G13_Interrupt_Acknowledge_Bits {
651 G1_Gate_Error_Confirm_Bit = 0x2,
652 G1_TC_Error_Confirm_Bit = 0x4
654 static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
656 if (counter_index % 2)
657 return G1_Gate_Error_Confirm_Bit;
658 return G0_Gate_Error_Confirm_Bit;
661 static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
663 if (counter_index % 2)
664 return G1_TC_Error_Confirm_Bit;
665 return G0_TC_Error_Confirm_Bit;
668 /* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
669 enum Gxx_Interrupt_Acknowledge_Bits {
670 Gi_TC_Interrupt_Ack_Bit = 0x4000,
671 Gi_Gate_Interrupt_Ack_Bit = 0x8000
674 enum Gi_Status_Bits {
675 Gi_Gate_Interrupt_Bit = 0x4,
677 Gi_Interrupt_Bit = 0x8000
680 enum G02_Interrupt_Enable_Bits {
681 G0_TC_Interrupt_Enable_Bit = 0x40,
682 G0_Gate_Interrupt_Enable_Bit = 0x100
684 enum G13_Interrupt_Enable_Bits {
685 G1_TC_Interrupt_Enable_Bit = 0x200,
686 G1_Gate_Interrupt_Enable_Bit = 0x400
688 static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
692 if (counter_index % 2)
693 bit = G1_Gate_Interrupt_Enable_Bit;
695 bit = G0_Gate_Interrupt_Enable_Bit;
699 static inline void write_register(struct ni_gpct *counter, unsigned bits,
700 enum ni_gpct_register reg)
702 BUG_ON(reg >= NITIO_Num_Registers);
703 counter->counter_dev->write_register(counter, bits, reg);
706 static inline unsigned read_register(struct ni_gpct *counter,
707 enum ni_gpct_register reg)
709 BUG_ON(reg >= NITIO_Num_Registers);
710 return counter->counter_dev->read_register(counter, reg);
713 static inline int ni_tio_counting_mode_registers_present(const struct
717 switch (counter_dev->variant) {
718 case ni_gpct_variant_e_series:
721 case ni_gpct_variant_m_series:
722 case ni_gpct_variant_660x:
732 static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
733 enum ni_gpct_register
734 register_index, unsigned bit_mask,
736 unsigned transient_bit_values)
738 struct ni_gpct_device *counter_dev = counter->counter_dev;
741 BUG_ON(register_index >= NITIO_Num_Registers);
742 spin_lock_irqsave(&counter_dev->regs_lock, flags);
743 counter_dev->regs[register_index] &= ~bit_mask;
744 counter_dev->regs[register_index] |= (bit_values & bit_mask);
745 write_register(counter,
746 counter_dev->regs[register_index] | transient_bit_values,
749 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
752 /* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
753 * twiddled in interrupt context, or whose software copy may be read in
756 static inline void ni_tio_set_bits(struct ni_gpct *counter,
757 enum ni_gpct_register register_index,
758 unsigned bit_mask, unsigned bit_values)
760 ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
764 /* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
765 whose bits might be modified in interrupt context, or whose software copy
766 might need to be read in interrupt context.
768 static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
769 enum ni_gpct_register
772 struct ni_gpct_device *counter_dev = counter->counter_dev;
776 BUG_ON(register_index >= NITIO_Num_Registers);
777 spin_lock_irqsave(&counter_dev->regs_lock, flags);
778 value = counter_dev->regs[register_index];
779 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
783 int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
784 int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
785 unsigned int gate_source);
787 #endif /* _COMEDI_NI_TIO_INTERNAL_H */