drivers/staging/comedi/drivers/ni_tiocmd.c

   1 /*
   2   comedi/drivers/ni_tiocmd.c
   3   Command support for NI general purpose counters
   4
   5   Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6
   7   This program is free software; you can redistribute it and/or modify
   8   it under the terms of the GNU General Public License as published by
   9   the Free Software Foundation; either version 2 of the License, or
  10   (at your option) any later version.
  11
  12   This program is distributed in the hope that it will be useful,
  13   but WITHOUT ANY WARRANTY; without even the implied warranty of
  14   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15   GNU General Public License for more details.
  16
  17   You should have received a copy of the GNU General Public License
  18   along with this program; if not, write to the Free Software
  19   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23 Driver: ni_tiocmd
  24 Description: National Instruments general purpose counters command support
  25 Devices:
  26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  27         Herman.Bruyninckx@mech.kuleuven.ac.be,
  28         Wim.Meeussen@mech.kuleuven.ac.be,
  29         Klaas.Gadeyne@mech.kuleuven.ac.be,
  30         Frank Mori Hess <fmhess@users.sourceforge.net>
  31 Updated: Fri, 11 Apr 2008 12:32:35 +0100
  32 Status: works
  33
  34 This module is not used directly by end-users.  Rather, it
  35 is used by other drivers (for example ni_660x and ni_pcimio)
  36 to provide command support for NI's general purpose counters.
  37 It was originally split out of ni_tio.c to stop the 'ni_tio'
  38 module depending on the 'mite' module.
  39
  40 References:
  41 DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  42 DAQ 6601/6602 User Manual (NI 322137B-01)
  43 340934b.pdf  DAQ-STC reference manual
  44
  45 */
  46 /*
  47 TODO:
  48         Support use of both banks X and Y
  49 */
  50
  51 #include "comedi_fc.h"
  52 #include "ni_tio_internal.h"
  53 #include "mite.h"
  54
  55 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
  56 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
  57 MODULE_LICENSE("GPL");
  58
  59 static void ni_tio_configure_dma(struct ni_gpct *counter, short enable,
  60                                  short read_not_write)
  61 {
  62         struct ni_gpct_device *counter_dev = counter->counter_dev;
  63         unsigned input_select_bits = 0;
  64
  65         if (enable) {
  66                 if (read_not_write)
  67                         input_select_bits |= Gi_Read_Acknowledges_Irq;
  68                 else
  69                         input_select_bits |= Gi_Write_Acknowledges_Irq;
  70         }
  71         ni_tio_set_bits(counter,
  72                         NITIO_Gi_Input_Select_Reg(counter->counter_index),
  73                         Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq,
  74                         input_select_bits);
  75         switch (counter_dev->variant) {
  76         case ni_gpct_variant_e_series:
  77                 break;
  78         case ni_gpct_variant_m_series:
  79         case ni_gpct_variant_660x:
  80                 {
  81                         unsigned gi_dma_config_bits = 0;
  82
  83                         if (enable) {
  84                                 gi_dma_config_bits |= Gi_DMA_Enable_Bit;
  85                                 gi_dma_config_bits |= Gi_DMA_Int_Bit;
  86                         }
  87                         if (read_not_write == 0)
  88                                 gi_dma_config_bits |= Gi_DMA_Write_Bit;
  89                         ni_tio_set_bits(counter,
  90                                         NITIO_Gi_DMA_Config_Reg(counter->
  91                                                                 counter_index),
  92                                         Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
  93                                         Gi_DMA_Write_Bit, gi_dma_config_bits);
  94                 }
  95                 break;
  96         }
  97 }
  98
  99 static int ni_tio_input_inttrig(struct comedi_device *dev,
 100                                 struct comedi_subdevice *s,
 101                                 unsigned int trignum)
 102 {
 103         unsigned long flags;
 104         int retval = 0;
 105         struct ni_gpct *counter = s->private;
 106
 107         BUG_ON(counter == NULL);
 108         if (trignum != 0)
 109                 return -EINVAL;
 110
 111         spin_lock_irqsave(&counter->lock, flags);
 112         if (counter->mite_chan)
 113                 mite_dma_arm(counter->mite_chan);
 114         else
 115                 retval = -EIO;
 116         spin_unlock_irqrestore(&counter->lock, flags);
 117         if (retval < 0)
 118                 return retval;
 119         retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 120         s->async->inttrig = NULL;
 121
 122         return retval;
 123 }
 124
 125 static int ni_tio_input_cmd(struct ni_gpct *counter, struct comedi_async *async)
 126 {
 127         struct ni_gpct_device *counter_dev = counter->counter_dev;
 128         struct comedi_cmd *cmd = &async->cmd;
 129         int retval = 0;
 130
 131         /* write alloc the entire buffer */
 132         comedi_buf_write_alloc(async, async->prealloc_bufsz);
 133         counter->mite_chan->dir = COMEDI_INPUT;
 134         switch (counter_dev->variant) {
 135         case ni_gpct_variant_m_series:
 136         case ni_gpct_variant_660x:
 137                 mite_prep_dma(counter->mite_chan, 32, 32);
 138                 break;
 139         case ni_gpct_variant_e_series:
 140                 mite_prep_dma(counter->mite_chan, 16, 32);
 141                 break;
 142         default:
 143                 BUG();
 144                 break;
 145         }
 146         ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
 147                         Gi_Save_Trace_Bit, 0);
 148         ni_tio_configure_dma(counter, 1, 1);
 149         switch (cmd->start_src) {
 150         case TRIG_NOW:
 151                 async->inttrig = NULL;
 152                 mite_dma_arm(counter->mite_chan);
 153                 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 154                 break;
 155         case TRIG_INT:
 156                 async->inttrig = &ni_tio_input_inttrig;
 157                 break;
 158         case TRIG_EXT:
 159                 async->inttrig = NULL;
 160                 mite_dma_arm(counter->mite_chan);
 161                 retval = ni_tio_arm(counter, 1, cmd->start_arg);
 162         case TRIG_OTHER:
 163                 async->inttrig = NULL;
 164                 mite_dma_arm(counter->mite_chan);
 165                 break;
 166         default:
 167                 BUG();
 168                 break;
 169         }
 170         return retval;
 171 }
 172
 173 static int ni_tio_output_cmd(struct ni_gpct *counter,
 174                              struct comedi_async *async)
 175 {
 176         printk(KERN_ERR "ni_tio: output commands not yet implemented.\n");
 177         return -ENOTSUPP;
 178
 179         counter->mite_chan->dir = COMEDI_OUTPUT;
 180         mite_prep_dma(counter->mite_chan, 32, 32);
 181         ni_tio_configure_dma(counter, 1, 0);
 182         mite_dma_arm(counter->mite_chan);
 183         return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
 184 }
 185
 186 static int ni_tio_cmd_setup(struct ni_gpct *counter, struct comedi_async *async)
 187 {
 188         struct comedi_cmd *cmd = &async->cmd;
 189         int set_gate_source = 0;
 190         unsigned gate_source;
 191         int retval = 0;
 192
 193         if (cmd->scan_begin_src == TRIG_EXT) {
 194                 set_gate_source = 1;
 195                 gate_source = cmd->scan_begin_arg;
 196         } else if (cmd->convert_src == TRIG_EXT) {
 197                 set_gate_source = 1;
 198                 gate_source = cmd->convert_arg;
 199         }
 200         if (set_gate_source)
 201                 retval = ni_tio_set_gate_src(counter, 0, gate_source);
 202         if (cmd->flags & TRIG_WAKE_EOS) {
 203                 ni_tio_set_bits(counter,
 204                                 NITIO_Gi_Interrupt_Enable_Reg(counter->
 205                                                               counter_index),
 206                                 Gi_Gate_Interrupt_Enable_Bit(counter->
 207                                                              counter_index),
 208                                 Gi_Gate_Interrupt_Enable_Bit(counter->
 209                                                              counter_index));
 210         }
 211         return retval;
 212 }
 213
 214 int ni_tio_cmd(struct ni_gpct *counter, struct comedi_async *async)
 215 {
 216         struct comedi_cmd *cmd = &async->cmd;
 217         int retval = 0;
 218         unsigned long flags;
 219
 220         spin_lock_irqsave(&counter->lock, flags);
 221         if (counter->mite_chan == NULL) {
 222                 printk(KERN_ERR "ni_tio: commands only supported with DMA.  Interrupt-driven commands not yet implemented.\n");
 223                 retval = -EIO;
 224         } else {
 225                 retval = ni_tio_cmd_setup(counter, async);
 226                 if (retval == 0) {
 227                         if (cmd->flags & CMDF_WRITE)
 228                                 retval = ni_tio_output_cmd(counter, async);
 229                         else
 230                                 retval = ni_tio_input_cmd(counter, async);
 231                 }
 232         }
 233         spin_unlock_irqrestore(&counter->lock, flags);
 234         return retval;
 235 }
 236 EXPORT_SYMBOL_GPL(ni_tio_cmd);
 237
 238 int ni_tio_cmdtest(struct ni_gpct *counter, struct comedi_cmd *cmd)
 239 {
 240         int err = 0;
 241         unsigned int sources;
 242
 243         /* Step 1 : check if triggers are trivially valid */
 244
 245         sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
 246         if (ni_tio_counting_mode_registers_present(counter->counter_dev))
 247                 sources |= TRIG_EXT;
 248         err |= cfc_check_trigger_src(&cmd->start_src, sources);
 249
 250         err |= cfc_check_trigger_src(&cmd->scan_begin_src,
 251                                         TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
 252         err |= cfc_check_trigger_src(&cmd->convert_src,
 253                                         TRIG_NOW | TRIG_EXT | TRIG_OTHER);
 254         err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 255         err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 256
 257         if (err)
 258                 return 1;
 259
 260         /* Step 2a : make sure trigger sources are unique */
 261
 262         err |= cfc_check_trigger_is_unique(cmd->start_src);
 263         err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
 264         err |= cfc_check_trigger_is_unique(cmd->convert_src);
 265
 266         /* Step 2b : and mutually compatible */
 267
 268         if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
 269                 err |= -EINVAL;
 270
 271         if (err)
 272                 return 2;
 273
 274         /* step 3: make sure arguments are trivially compatible */
 275         if (cmd->start_src != TRIG_EXT) {
 276                 if (cmd->start_arg != 0) {
 277                         cmd->start_arg = 0;
 278                         err++;
 279                 }
 280         }
 281         if (cmd->scan_begin_src != TRIG_EXT) {
 282                 if (cmd->scan_begin_arg) {
 283                         cmd->scan_begin_arg = 0;
 284                         err++;
 285                 }
 286         }
 287         if (cmd->convert_src != TRIG_EXT) {
 288                 if (cmd->convert_arg) {
 289                         cmd->convert_arg = 0;
 290                         err++;
 291                 }
 292         }
 293
 294         if (cmd->scan_end_arg != cmd->chanlist_len) {
 295                 cmd->scan_end_arg = cmd->chanlist_len;
 296                 err++;
 297         }
 298
 299         if (cmd->stop_src == TRIG_NONE) {
 300                 if (cmd->stop_arg != 0) {
 301                         cmd->stop_arg = 0;
 302                         err++;
 303                 }
 304         }
 305
 306         if (err)
 307                 return 3;
 308
 309         /* step 4: fix up any arguments */
 310
 311         if (err)
 312                 return 4;
 313
 314         return 0;
 315 }
 316 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
 317
 318 int ni_tio_cancel(struct ni_gpct *counter)
 319 {
 320         unsigned long flags;
 321
 322         ni_tio_arm(counter, 0, 0);
 323         spin_lock_irqsave(&counter->lock, flags);
 324         if (counter->mite_chan)
 325                 mite_dma_disarm(counter->mite_chan);
 326         spin_unlock_irqrestore(&counter->lock, flags);
 327         ni_tio_configure_dma(counter, 0, 0);
 328
 329         ni_tio_set_bits(counter,
 330                         NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
 331                         Gi_Gate_Interrupt_Enable_Bit(counter->counter_index),
 332                         0x0);
 333         return 0;
 334 }
 335 EXPORT_SYMBOL_GPL(ni_tio_cancel);
 336
 337         /* During buffered input counter operation for e-series, the gate
 338            interrupt is acked automatically by the dma controller, due to the
 339            Gi_Read/Write_Acknowledges_IRQ bits in the input select register.  */
 340 static int should_ack_gate(struct ni_gpct *counter)
 341 {
 342         unsigned long flags;
 343         int retval = 0;
 344
 345         switch (counter->counter_dev->variant) {
 346         case ni_gpct_variant_m_series:
 347         /*  not sure if 660x really supports gate
 348             interrupts (the bits are not listed
 349             in register-level manual) */
 350         case ni_gpct_variant_660x:
 351                 return 1;
 352                 break;
 353         case ni_gpct_variant_e_series:
 354                 spin_lock_irqsave(&counter->lock, flags);
 355                 {
 356                         if (counter->mite_chan == NULL ||
 357                             counter->mite_chan->dir != COMEDI_INPUT ||
 358                             (mite_done(counter->mite_chan))) {
 359                                 retval = 1;
 360                         }
 361                 }
 362                 spin_unlock_irqrestore(&counter->lock, flags);
 363                 break;
 364         }
 365         return retval;
 366 }
 367
 368 void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
 369                                     int *tc_error, int *perm_stale_data,
 370                                     int *stale_data)
 371 {
 372         const unsigned short gxx_status = read_register(counter,
 373                                                         NITIO_Gxx_Status_Reg
 374                                                         (counter->
 375                                                          counter_index));
 376         const unsigned short gi_status = read_register(counter,
 377                                                        NITIO_Gi_Status_Reg
 378                                                        (counter->
 379                                                         counter_index));
 380         unsigned ack = 0;
 381
 382         if (gate_error)
 383                 *gate_error = 0;
 384         if (tc_error)
 385                 *tc_error = 0;
 386         if (perm_stale_data)
 387                 *perm_stale_data = 0;
 388         if (stale_data)
 389                 *stale_data = 0;
 390
 391         if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
 392                 ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
 393                 if (gate_error) {
 394                         /*660x don't support automatic acknowledgement
 395                           of gate interrupt via dma read/write
 396                            and report bogus gate errors */
 397                         if (counter->counter_dev->variant !=
 398                             ni_gpct_variant_660x) {
 399                                 *gate_error = 1;
 400                         }
 401                 }
 402         }
 403         if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
 404                 ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
 405                 if (tc_error)
 406                         *tc_error = 1;
 407         }
 408         if (gi_status & Gi_TC_Bit)
 409                 ack |= Gi_TC_Interrupt_Ack_Bit;
 410         if (gi_status & Gi_Gate_Interrupt_Bit) {
 411                 if (should_ack_gate(counter))
 412                         ack |= Gi_Gate_Interrupt_Ack_Bit;
 413         }
 414         if (ack)
 415                 write_register(counter, ack,
 416                                NITIO_Gi_Interrupt_Acknowledge_Reg
 417                                (counter->counter_index));
 418         if (ni_tio_get_soft_copy
 419             (counter,
 420              NITIO_Gi_Mode_Reg(counter->counter_index)) &
 421             Gi_Loading_On_Gate_Bit) {
 422                 if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
 423                         if (stale_data)
 424                                 *stale_data = 1;
 425                 }
 426                 if (read_register(counter,
 427                                   NITIO_Gxx_Joint_Status2_Reg
 428                                   (counter->counter_index)) &
 429                     Gi_Permanent_Stale_Bit(counter->counter_index)) {
 430                         printk(KERN_INFO "%s: Gi_Permanent_Stale_Data detected.\n",
 431                                __func__);
 432                         if (perm_stale_data)
 433                                 *perm_stale_data = 1;
 434                 }
 435         }
 436 }
 437 EXPORT_SYMBOL_GPL(ni_tio_acknowledge_and_confirm);
 438
 439 void ni_tio_handle_interrupt(struct ni_gpct *counter,
 440                              struct comedi_subdevice *s)
 441 {
 442         unsigned gpct_mite_status;
 443         unsigned long flags;
 444         int gate_error;
 445         int tc_error;
 446         int perm_stale_data;
 447
 448         ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
 449                                        &perm_stale_data, NULL);
 450         if (gate_error) {
 451                 printk(KERN_NOTICE "%s: Gi_Gate_Error detected.\n", __func__);
 452                 s->async->events |= COMEDI_CB_OVERFLOW;
 453         }
 454         if (perm_stale_data)
 455                 s->async->events |= COMEDI_CB_ERROR;
 456         switch (counter->counter_dev->variant) {
 457         case ni_gpct_variant_m_series:
 458         case ni_gpct_variant_660x:
 459                 if (read_register(counter,
 460                                 NITIO_Gi_DMA_Status_Reg
 461                                 (counter->counter_index)) & Gi_DRQ_Error_Bit) {
 462                         printk(KERN_NOTICE "%s: Gi_DRQ_Error detected.\n",
 463                                                         __func__);
 464                         s->async->events |= COMEDI_CB_OVERFLOW;
 465                 }
 466                 break;
 467         case ni_gpct_variant_e_series:
 468                 break;
 469         }
 470         spin_lock_irqsave(&counter->lock, flags);
 471         if (counter->mite_chan == NULL) {
 472                 spin_unlock_irqrestore(&counter->lock, flags);
 473                 return;
 474         }
 475         gpct_mite_status = mite_get_status(counter->mite_chan);
 476         if (gpct_mite_status & CHSR_LINKC) {
 477                 writel(CHOR_CLRLC,
 478                        counter->mite_chan->mite->mite_io_addr +
 479                        MITE_CHOR(counter->mite_chan->channel));
 480         }
 481         mite_sync_input_dma(counter->mite_chan, s->async);
 482         spin_unlock_irqrestore(&counter->lock, flags);
 483 }
 484 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
 485
 486 void ni_tio_set_mite_channel(struct ni_gpct *counter,
 487                              struct mite_channel *mite_chan)
 488 {
 489         unsigned long flags;
 490
 491         spin_lock_irqsave(&counter->lock, flags);
 492         counter->mite_chan = mite_chan;
 493         spin_unlock_irqrestore(&counter->lock, flags);
 494 }
 495 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
 496
 497 static int __init ni_tiocmd_init_module(void)
 498 {
 499         return 0;
 500 }
 501
 502 module_init(ni_tiocmd_init_module);
 503
 504 static void __exit ni_tiocmd_cleanup_module(void)
 505 {
 506 }
 507
 508 module_exit(ni_tiocmd_cleanup_module);