2 comedi/drivers/ni_tiocmd.c
3 Command support for NI general purpose counters
5 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: National Instruments general purpose counters command support
26 Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
27 Herman.Bruyninckx@mech.kuleuven.ac.be,
28 Wim.Meeussen@mech.kuleuven.ac.be,
29 Klaas.Gadeyne@mech.kuleuven.ac.be,
30 Frank Mori Hess <fmhess@users.sourceforge.net>
31 Updated: Fri, 11 Apr 2008 12:32:35 +0100
34 This module is not used directly by end-users. Rather, it
35 is used by other drivers (for example ni_660x and ni_pcimio)
36 to provide command support for NI's general purpose counters.
37 It was originally split out of ni_tio.c to stop the 'ni_tio'
38 module depending on the 'mite' module.
41 DAQ 660x Register-Level Programmer Manual (NI 370505A-01)
42 DAQ 6601/6602 User Manual (NI 322137B-01)
43 340934b.pdf DAQ-STC reference manual
48 Support use of both banks X and Y
51 #include "comedi_fc.h"
52 #include "ni_tio_internal.h"
55 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
56 MODULE_DESCRIPTION("Comedi command support for NI general-purpose counters");
57 MODULE_LICENSE("GPL");
59 static void ni_tio_configure_dma(struct ni_gpct *counter, short enable,
62 struct ni_gpct_device *counter_dev = counter->counter_dev;
63 unsigned input_select_bits = 0;
67 input_select_bits |= Gi_Read_Acknowledges_Irq;
69 input_select_bits |= Gi_Write_Acknowledges_Irq;
71 ni_tio_set_bits(counter,
72 NITIO_Gi_Input_Select_Reg(counter->counter_index),
73 Gi_Read_Acknowledges_Irq | Gi_Write_Acknowledges_Irq,
75 switch (counter_dev->variant) {
76 case ni_gpct_variant_e_series:
78 case ni_gpct_variant_m_series:
79 case ni_gpct_variant_660x:
81 unsigned gi_dma_config_bits = 0;
84 gi_dma_config_bits |= Gi_DMA_Enable_Bit;
85 gi_dma_config_bits |= Gi_DMA_Int_Bit;
87 if (read_not_write == 0)
88 gi_dma_config_bits |= Gi_DMA_Write_Bit;
89 ni_tio_set_bits(counter,
90 NITIO_Gi_DMA_Config_Reg(counter->
92 Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
93 Gi_DMA_Write_Bit, gi_dma_config_bits);
99 static int ni_tio_input_inttrig(struct comedi_device *dev,
100 struct comedi_subdevice *s,
101 unsigned int trignum)
105 struct ni_gpct *counter = s->private;
107 BUG_ON(counter == NULL);
111 spin_lock_irqsave(&counter->lock, flags);
112 if (counter->mite_chan)
113 mite_dma_arm(counter->mite_chan);
116 spin_unlock_irqrestore(&counter->lock, flags);
119 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
120 s->async->inttrig = NULL;
125 static int ni_tio_input_cmd(struct ni_gpct *counter, struct comedi_async *async)
127 struct ni_gpct_device *counter_dev = counter->counter_dev;
128 struct comedi_cmd *cmd = &async->cmd;
131 /* write alloc the entire buffer */
132 comedi_buf_write_alloc(async, async->prealloc_bufsz);
133 counter->mite_chan->dir = COMEDI_INPUT;
134 switch (counter_dev->variant) {
135 case ni_gpct_variant_m_series:
136 case ni_gpct_variant_660x:
137 mite_prep_dma(counter->mite_chan, 32, 32);
139 case ni_gpct_variant_e_series:
140 mite_prep_dma(counter->mite_chan, 16, 32);
146 ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index),
147 Gi_Save_Trace_Bit, 0);
148 ni_tio_configure_dma(counter, 1, 1);
149 switch (cmd->start_src) {
151 async->inttrig = NULL;
152 mite_dma_arm(counter->mite_chan);
153 retval = ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
156 async->inttrig = &ni_tio_input_inttrig;
159 async->inttrig = NULL;
160 mite_dma_arm(counter->mite_chan);
161 retval = ni_tio_arm(counter, 1, cmd->start_arg);
163 async->inttrig = NULL;
164 mite_dma_arm(counter->mite_chan);
173 static int ni_tio_output_cmd(struct ni_gpct *counter,
174 struct comedi_async *async)
176 printk(KERN_ERR "ni_tio: output commands not yet implemented.\n");
179 counter->mite_chan->dir = COMEDI_OUTPUT;
180 mite_prep_dma(counter->mite_chan, 32, 32);
181 ni_tio_configure_dma(counter, 1, 0);
182 mite_dma_arm(counter->mite_chan);
183 return ni_tio_arm(counter, 1, NI_GPCT_ARM_IMMEDIATE);
186 static int ni_tio_cmd_setup(struct ni_gpct *counter, struct comedi_async *async)
188 struct comedi_cmd *cmd = &async->cmd;
189 int set_gate_source = 0;
190 unsigned gate_source;
193 if (cmd->scan_begin_src == TRIG_EXT) {
195 gate_source = cmd->scan_begin_arg;
196 } else if (cmd->convert_src == TRIG_EXT) {
198 gate_source = cmd->convert_arg;
201 retval = ni_tio_set_gate_src(counter, 0, gate_source);
202 if (cmd->flags & TRIG_WAKE_EOS) {
203 ni_tio_set_bits(counter,
204 NITIO_Gi_Interrupt_Enable_Reg(counter->
206 Gi_Gate_Interrupt_Enable_Bit(counter->
208 Gi_Gate_Interrupt_Enable_Bit(counter->
214 int ni_tio_cmd(struct ni_gpct *counter, struct comedi_async *async)
216 struct comedi_cmd *cmd = &async->cmd;
220 spin_lock_irqsave(&counter->lock, flags);
221 if (counter->mite_chan == NULL) {
222 printk(KERN_ERR "ni_tio: commands only supported with DMA. Interrupt-driven commands not yet implemented.\n");
225 retval = ni_tio_cmd_setup(counter, async);
227 if (cmd->flags & CMDF_WRITE)
228 retval = ni_tio_output_cmd(counter, async);
230 retval = ni_tio_input_cmd(counter, async);
233 spin_unlock_irqrestore(&counter->lock, flags);
236 EXPORT_SYMBOL_GPL(ni_tio_cmd);
238 int ni_tio_cmdtest(struct ni_gpct *counter, struct comedi_cmd *cmd)
241 unsigned int sources;
243 /* Step 1 : check if triggers are trivially valid */
245 sources = TRIG_NOW | TRIG_INT | TRIG_OTHER;
246 if (ni_tio_counting_mode_registers_present(counter->counter_dev))
248 err |= cfc_check_trigger_src(&cmd->start_src, sources);
250 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
251 TRIG_FOLLOW | TRIG_EXT | TRIG_OTHER);
252 err |= cfc_check_trigger_src(&cmd->convert_src,
253 TRIG_NOW | TRIG_EXT | TRIG_OTHER);
254 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
255 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
260 /* Step 2a : make sure trigger sources are unique */
262 err |= cfc_check_trigger_is_unique(cmd->start_src);
263 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
264 err |= cfc_check_trigger_is_unique(cmd->convert_src);
266 /* Step 2b : and mutually compatible */
268 if (cmd->convert_src != TRIG_NOW && cmd->scan_begin_src != TRIG_FOLLOW)
274 /* step 3: make sure arguments are trivially compatible */
275 if (cmd->start_src != TRIG_EXT) {
276 if (cmd->start_arg != 0) {
281 if (cmd->scan_begin_src != TRIG_EXT) {
282 if (cmd->scan_begin_arg) {
283 cmd->scan_begin_arg = 0;
287 if (cmd->convert_src != TRIG_EXT) {
288 if (cmd->convert_arg) {
289 cmd->convert_arg = 0;
294 if (cmd->scan_end_arg != cmd->chanlist_len) {
295 cmd->scan_end_arg = cmd->chanlist_len;
299 if (cmd->stop_src == TRIG_NONE) {
300 if (cmd->stop_arg != 0) {
309 /* step 4: fix up any arguments */
316 EXPORT_SYMBOL_GPL(ni_tio_cmdtest);
318 int ni_tio_cancel(struct ni_gpct *counter)
322 ni_tio_arm(counter, 0, 0);
323 spin_lock_irqsave(&counter->lock, flags);
324 if (counter->mite_chan)
325 mite_dma_disarm(counter->mite_chan);
326 spin_unlock_irqrestore(&counter->lock, flags);
327 ni_tio_configure_dma(counter, 0, 0);
329 ni_tio_set_bits(counter,
330 NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index),
331 Gi_Gate_Interrupt_Enable_Bit(counter->counter_index),
335 EXPORT_SYMBOL_GPL(ni_tio_cancel);
337 /* During buffered input counter operation for e-series, the gate
338 interrupt is acked automatically by the dma controller, due to the
339 Gi_Read/Write_Acknowledges_IRQ bits in the input select register. */
340 static int should_ack_gate(struct ni_gpct *counter)
345 switch (counter->counter_dev->variant) {
346 case ni_gpct_variant_m_series:
347 /* not sure if 660x really supports gate
348 interrupts (the bits are not listed
349 in register-level manual) */
350 case ni_gpct_variant_660x:
353 case ni_gpct_variant_e_series:
354 spin_lock_irqsave(&counter->lock, flags);
356 if (counter->mite_chan == NULL ||
357 counter->mite_chan->dir != COMEDI_INPUT ||
358 (mite_done(counter->mite_chan))) {
362 spin_unlock_irqrestore(&counter->lock, flags);
368 void ni_tio_acknowledge_and_confirm(struct ni_gpct *counter, int *gate_error,
369 int *tc_error, int *perm_stale_data,
372 const unsigned short gxx_status = read_register(counter,
376 const unsigned short gi_status = read_register(counter,
387 *perm_stale_data = 0;
391 if (gxx_status & Gi_Gate_Error_Bit(counter->counter_index)) {
392 ack |= Gi_Gate_Error_Confirm_Bit(counter->counter_index);
394 /*660x don't support automatic acknowledgement
395 of gate interrupt via dma read/write
396 and report bogus gate errors */
397 if (counter->counter_dev->variant !=
398 ni_gpct_variant_660x) {
403 if (gxx_status & Gi_TC_Error_Bit(counter->counter_index)) {
404 ack |= Gi_TC_Error_Confirm_Bit(counter->counter_index);
408 if (gi_status & Gi_TC_Bit)
409 ack |= Gi_TC_Interrupt_Ack_Bit;
410 if (gi_status & Gi_Gate_Interrupt_Bit) {
411 if (should_ack_gate(counter))
412 ack |= Gi_Gate_Interrupt_Ack_Bit;
415 write_register(counter, ack,
416 NITIO_Gi_Interrupt_Acknowledge_Reg
417 (counter->counter_index));
418 if (ni_tio_get_soft_copy
420 NITIO_Gi_Mode_Reg(counter->counter_index)) &
421 Gi_Loading_On_Gate_Bit) {
422 if (gxx_status & Gi_Stale_Data_Bit(counter->counter_index)) {
426 if (read_register(counter,
427 NITIO_Gxx_Joint_Status2_Reg
428 (counter->counter_index)) &
429 Gi_Permanent_Stale_Bit(counter->counter_index)) {
430 printk(KERN_INFO "%s: Gi_Permanent_Stale_Data detected.\n",
433 *perm_stale_data = 1;
437 EXPORT_SYMBOL_GPL(ni_tio_acknowledge_and_confirm);
439 void ni_tio_handle_interrupt(struct ni_gpct *counter,
440 struct comedi_subdevice *s)
442 unsigned gpct_mite_status;
448 ni_tio_acknowledge_and_confirm(counter, &gate_error, &tc_error,
449 &perm_stale_data, NULL);
451 printk(KERN_NOTICE "%s: Gi_Gate_Error detected.\n", __func__);
452 s->async->events |= COMEDI_CB_OVERFLOW;
455 s->async->events |= COMEDI_CB_ERROR;
456 switch (counter->counter_dev->variant) {
457 case ni_gpct_variant_m_series:
458 case ni_gpct_variant_660x:
459 if (read_register(counter,
460 NITIO_Gi_DMA_Status_Reg
461 (counter->counter_index)) & Gi_DRQ_Error_Bit) {
462 printk(KERN_NOTICE "%s: Gi_DRQ_Error detected.\n",
464 s->async->events |= COMEDI_CB_OVERFLOW;
467 case ni_gpct_variant_e_series:
470 spin_lock_irqsave(&counter->lock, flags);
471 if (counter->mite_chan == NULL) {
472 spin_unlock_irqrestore(&counter->lock, flags);
475 gpct_mite_status = mite_get_status(counter->mite_chan);
476 if (gpct_mite_status & CHSR_LINKC) {
478 counter->mite_chan->mite->mite_io_addr +
479 MITE_CHOR(counter->mite_chan->channel));
481 mite_sync_input_dma(counter->mite_chan, s->async);
482 spin_unlock_irqrestore(&counter->lock, flags);
484 EXPORT_SYMBOL_GPL(ni_tio_handle_interrupt);
486 void ni_tio_set_mite_channel(struct ni_gpct *counter,
487 struct mite_channel *mite_chan)
491 spin_lock_irqsave(&counter->lock, flags);
492 counter->mite_chan = mite_chan;
493 spin_unlock_irqrestore(&counter->lock, flags);
495 EXPORT_SYMBOL_GPL(ni_tio_set_mite_channel);
497 static int __init ni_tiocmd_init_module(void)
502 module_init(ni_tiocmd_init_module);
504 static void __exit ni_tiocmd_cleanup_module(void)
508 module_exit(ni_tiocmd_cleanup_module);