2 comedi/drivers/rtd520.c
3 Comedi driver for Real Time Devices (RTD) PCI4520/DM7520
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2001 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 Description: Real Time Devices PCI4520/DM7520
26 Devices: [Real Time Devices] DM7520HR-1 (rtd520), DM7520HR-8,
28 Status: Works. Only tested on DM7520-8. Not SMP safe.
30 Configuration options:
31 [0] - PCI bus of device (optional)
32 If bus / slot is not specified, the first available PCI
34 [1] - PCI slot of device (optional)
37 Created by Dan Christian, NASA Ames Research Center.
39 The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
41 8/16 12 bit ADC with FIFO and channel gain table
42 8 bits high speed digital out (for external MUX) (or 8 in or 8 out)
43 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO)
44 2 12 bit DACs with FIFOs
48 timers: ADC sample, pacer, burst, about, delay, DA1, DA2
50 3 user timer/counters (8254)
53 The DM7520 has slightly fewer features (fewer gain steps).
55 These boards can support external multiplexors and multi-board
56 synchronization, but this driver doesn't support that.
58 Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm
59 Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf
60 Example source: http://www.rtdusa.com/examples/dm/dm7520.zip
61 Call them and ask for the register level manual.
62 PCI chip: http://www.plxtech.com/products/io/pci9080
65 This board is memory mapped. There is some IO stuff, but it isn't needed.
67 I use a pretty loose naming style within the driver (rtd_blah).
68 All externally visible names should be rtd520_blah.
69 I use camelCase for structures (and inside them).
70 I may also use upper CamelCase for function names (old habit).
72 This board is somewhat related to the RTD PCI4400 board.
74 I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and
75 das1800, since they have the best documented code. Driver
76 cb_pcidas64.c uses the same DMA controller.
78 As far as I can tell, the About interrupt doesn't work if Sample is
79 also enabled. It turns out that About really isn't needed, since
80 we always count down samples read.
82 There was some timer/counter code, but it didn't follow the right API.
89 Analog-In supports instruction and command mode.
91 With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
92 (single channel, 64K read buffer). I get random system lockups when
93 using DMA with ALI-15xx based systems. I haven't been able to test
94 any other chipsets. The lockups happen soon after the start of an
95 acquistion, not in the middle of a long run.
97 Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2
98 (with a 256K read buffer).
100 Digital-IO and Analog-Out only support instruction mode.
104 #include <linux/pci.h>
105 #include <linux/delay.h>
106 #include <linux/interrupt.h>
108 #include "../comedidev.h"
110 #include "comedi_fc.h"
114 /*======================================================================
115 Driver specific stuff (tunable)
116 ======================================================================*/
118 /* We really only need 2 buffers. More than that means being much
119 smarter about knowing which ones are full. */
120 #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */
122 /* Target period for periodic transfers. This sets the user read latency. */
123 /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */
124 /* If this is too low, efficiency is poor */
125 #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */
127 /* Set a practical limit on how long a list to support (affects memory use) */
128 /* The board support a channel list up to the FIFO length (1K or 8K) */
129 #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */
131 /* tuning for ai/ao instruction done polling */
133 #define WAIT_QUIETLY /* as nothing, spin on done bit */
134 #define RTD_ADC_TIMEOUT 66000 /* 2 msec at 33mhz bus rate */
135 #define RTD_DAC_TIMEOUT 66000
136 #define RTD_DMA_TIMEOUT 33000 /* 1 msec */
138 /* by delaying, power and electrical noise are reduced somewhat */
139 #define WAIT_QUIETLY udelay(1)
140 #define RTD_ADC_TIMEOUT 2000 /* in usec */
141 #define RTD_DAC_TIMEOUT 2000 /* in usec */
142 #define RTD_DMA_TIMEOUT 1000 /* in usec */
145 /*======================================================================
147 ======================================================================*/
149 #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */
150 #define RTD_CLOCK_BASE 125 /* clock period in ns */
152 /* Note: these speed are slower than the spec, but fit the counter resolution*/
153 #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */
154 /* max speed if we don't have to wait for settling */
155 #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */
157 #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */
158 /* min speed when only 1 channel (no burst counter) */
159 #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */
161 /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */
162 #define DMA_MODE_BITS (\
163 PLX_LOCAL_BUS_16_WIDE_BITS \
164 | PLX_DMA_EN_READYIN_BIT \
165 | PLX_DMA_LOCAL_BURST_EN_BIT \
167 | PLX_DMA_INTR_PCI_BIT \
168 | PLX_LOCAL_ADDR_CONST_BIT \
169 | PLX_DEMAND_MODE_BIT)
171 #define DMA_TRANSFER_BITS (\
172 /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \
173 /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \
174 /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI)
176 /*======================================================================
177 Comedi specific stuff
178 ======================================================================*/
181 * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128)
183 static const struct comedi_lrange rtd_ai_7520_range = {
185 /* +-5V input range gain steps */
192 /* +-10V input range gain steps */
197 BIP_RANGE(10.0 / 16),
198 BIP_RANGE(10.0 / 32),
199 /* +10V input range gain steps */
204 UNI_RANGE(10.0 / 16),
205 UNI_RANGE(10.0 / 32),
209 /* PCI4520 has two more gains (6 more entries) */
210 static const struct comedi_lrange rtd_ai_4520_range = {
212 /* +-5V input range gain steps */
220 BIP_RANGE(5.0 / 128),
221 /* +-10V input range gain steps */
226 BIP_RANGE(10.0 / 16),
227 BIP_RANGE(10.0 / 32),
228 BIP_RANGE(10.0 / 64),
229 BIP_RANGE(10.0 / 128),
230 /* +10V input range gain steps */
235 UNI_RANGE(10.0 / 16),
236 UNI_RANGE(10.0 / 32),
237 UNI_RANGE(10.0 / 64),
238 UNI_RANGE(10.0 / 128),
242 /* Table order matches range values */
243 static const struct comedi_lrange rtd_ao_range = {
259 int range10Start; /* start of +-10V range */
260 int rangeUniStart; /* start of +10V range */
261 const struct comedi_lrange *ai_range;
264 static const struct rtdBoard rtd520Boards[] = {
269 .ai_range = &rtd_ai_7520_range,
275 .ai_range = &rtd_ai_4520_range,
280 This structure is for data unique to this hardware driver.
281 This is also unique for each board in the system.
284 /* memory mapped board structures */
289 long aiCount; /* total transfer size (samples) */
290 int transCount; /* # to transfer data. 0->1/2FIFO */
291 int flags; /* flag event modes */
293 /* channel list info */
294 /* chanBipolar tracks whether a channel is bipolar (and needs +2048) */
295 unsigned char chanBipolar[RTD_MAX_CHANLIST / 8]; /* bit array */
298 unsigned int aoValue[2]; /* Used for AO read back */
300 /* timer gate (when enabled) */
301 u8 utcGate[4]; /* 1 extra allows simple range check */
303 /* shadow registers affect other registers, but can't be read back */
304 /* The macros below update these on writes */
305 u16 intMask; /* interrupt mask */
306 u16 intClearMask; /* interrupt clear mask */
307 u8 utcCtrl[4]; /* crtl mode for 3 utc + read back */
308 u8 dioStatus; /* could be read back (dio0Ctrl) */
312 /* bit defines for "flags" */
313 #define SEND_EOS 0x01 /* send End Of Scan events */
314 #define DMA0_ACTIVE 0x02 /* DMA0 is active */
315 #define DMA1_ACTIVE 0x04 /* DMA1 is active */
317 /* Macros for accessing channel list bit array */
318 #define CHAN_ARRAY_TEST(array, index) \
319 (((array)[(index)/8] >> ((index) & 0x7)) & 0x1)
320 #define CHAN_ARRAY_SET(array, index) \
321 (((array)[(index)/8] |= 1 << ((index) & 0x7)))
322 #define CHAN_ARRAY_CLEAR(array, index) \
323 (((array)[(index)/8] &= ~(1 << ((index) & 0x7))))
326 Given a desired period and the clock period (both in ns),
327 return the proper counter value (divider-1).
328 Sets the original period to be the true value.
329 Note: you have to check if the value is larger than the counter range!
331 static int rtd_ns_to_timer_base(unsigned int *nanosec,
332 int round_mode, int base)
336 switch (round_mode) {
337 case TRIG_ROUND_NEAREST:
339 divider = (*nanosec + base / 2) / base;
341 case TRIG_ROUND_DOWN:
342 divider = (*nanosec) / base;
345 divider = (*nanosec + base - 1) / base;
349 divider = 2; /* min is divide by 2 */
351 /* Note: we don't check for max, because different timers
352 have different ranges */
354 *nanosec = base * divider;
355 return divider - 1; /* countdown is divisor+1 */
359 Given a desired period (in ns),
360 return the proper counter value (divider-1) for the internal clock.
361 Sets the original period to be the true value.
363 static int rtd_ns_to_timer(unsigned int *ns, int round_mode)
365 return rtd_ns_to_timer_base(ns, round_mode, RTD_CLOCK_BASE);
369 Convert a single comedi channel-gain entry to a RTD520 table entry
371 static unsigned short rtdConvertChanGain(struct comedi_device *dev,
372 unsigned int comediChan, int chanIndex)
373 { /* index in channel list */
374 const struct rtdBoard *thisboard = comedi_board(dev);
375 struct rtdPrivate *devpriv = dev->private;
376 unsigned int chan, range, aref;
377 unsigned short r = 0;
379 chan = CR_CHAN(comediChan);
380 range = CR_RANGE(comediChan);
381 aref = CR_AREF(comediChan);
385 /* Note: we also setup the channel list bipolar flag array */
386 if (range < thisboard->range10Start) {
389 r |= (range & 0x7) << 4;
390 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
391 } else if (range < thisboard->rangeUniStart) {
394 r |= ((range - thisboard->range10Start) & 0x7) << 4;
395 CHAN_ARRAY_SET(devpriv->chanBipolar, chanIndex);
399 r |= ((range - thisboard->rangeUniStart) & 0x7) << 4;
400 CHAN_ARRAY_CLEAR(devpriv->chanBipolar, chanIndex);
404 case AREF_GROUND: /* on-board ground */
408 r |= 0x80; /* ref external analog common */
412 r |= 0x400; /* differential inputs */
415 case AREF_OTHER: /* ??? */
418 /*printk ("chan=%d r=%d a=%d -> 0x%x\n",
419 chan, range, aref, r); */
424 Setup the channel-gain table from a comedi list
426 static void rtd_load_channelgain_list(struct comedi_device *dev,
427 unsigned int n_chan, unsigned int *list)
429 struct rtdPrivate *devpriv = dev->private;
431 if (n_chan > 1) { /* setup channel gain table */
434 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
435 writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
436 for (ii = 0; ii < n_chan; ii++) {
437 writel(rtdConvertChanGain(dev, list[ii], ii),
438 devpriv->las0 + LAS0_CGT_WRITE);
440 } else { /* just use the channel gain latch */
441 writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
442 writel(rtdConvertChanGain(dev, list[0], 0),
443 devpriv->las0 + LAS0_CGL_WRITE);
447 /* determine fifo size by doing adc conversions until the fifo half
448 empty status flag clears */
449 static int rtd520_probe_fifo_depth(struct comedi_device *dev)
451 struct rtdPrivate *devpriv = dev->private;
452 unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
454 static const unsigned limit = 0x2000;
455 unsigned fifo_size = 0;
457 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
458 rtd_load_channelgain_list(dev, 1, &chanspec);
459 /* ADC conversion trigger source: SOFTWARE */
460 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
461 /* convert samples */
462 for (i = 0; i < limit; ++i) {
463 unsigned fifo_status;
464 /* trigger conversion */
465 writew(0, devpriv->las0 + LAS0_ADC);
467 fifo_status = readl(devpriv->las0 + LAS0_ADC);
468 if ((fifo_status & FS_ADC_HEMPTY) == 0) {
474 dev_info(dev->class_dev, "failed to probe fifo size.\n");
477 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
478 if (fifo_size != 0x400 && fifo_size != 0x2000) {
479 dev_info(dev->class_dev,
480 "unexpected fifo size of %i, expected 1024 or 8192.\n",
488 "instructions" read/write data in "one-shot" or "software-triggered"
489 mode (simplest case).
490 This doesn't use interrupts.
492 Note, we don't do any settling delays. Use a instruction list to
493 select, delay, then read.
495 static int rtd_ai_rinsn(struct comedi_device *dev,
496 struct comedi_subdevice *s, struct comedi_insn *insn,
499 struct rtdPrivate *devpriv = dev->private;
503 /* clear any old fifo data */
504 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
506 /* write channel to multiplexer and clear channel gain table */
507 rtd_load_channelgain_list(dev, 1, &insn->chanspec);
509 /* ADC conversion trigger source: SOFTWARE */
510 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
512 /* convert n samples */
513 for (n = 0; n < insn->n; n++) {
515 /* trigger conversion */
516 writew(0, devpriv->las0 + LAS0_ADC);
518 for (ii = 0; ii < RTD_ADC_TIMEOUT; ++ii) {
519 stat = readl(devpriv->las0 + LAS0_ADC);
520 if (stat & FS_ADC_NOT_EMPTY) /* 1 -> not empty */
524 if (ii >= RTD_ADC_TIMEOUT)
528 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
529 /*printk ("rtd520: Got 0x%x after %d usec\n", d, ii+1); */
530 d = d >> 3; /* low 3 bits are marker lines */
531 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, 0))
532 /* convert to comedi unsigned data */
538 /* return the number of samples read/written */
543 Get what we know is there.... Fast!
544 This uses 1/2 the bus cycles of read_dregs (below).
546 The manual claims that we can do a lword read, but it doesn't work here.
548 static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s,
551 struct rtdPrivate *devpriv = dev->private;
554 for (ii = 0; ii < count; ii++) {
558 if (0 == devpriv->aiCount) { /* done */
559 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
563 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
564 d = d >> 3; /* low 3 bits are marker lines */
565 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
566 /* convert to comedi unsigned data */
571 if (!comedi_buf_put(s->async, sample))
574 if (devpriv->aiCount > 0) /* < 0, means read forever */
581 unknown amout of data is waiting in fifo.
583 static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
585 struct rtdPrivate *devpriv = dev->private;
587 while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
589 s16 d = readw(devpriv->las1 + LAS1_ADC_FIFO);
591 if (0 == devpriv->aiCount) { /* done */
592 continue; /* read rest */
595 d = d >> 3; /* low 3 bits are marker lines */
596 if (CHAN_ARRAY_TEST(devpriv->chanBipolar, s->async->cur_chan)) {
597 /* convert to comedi unsigned data */
602 if (!comedi_buf_put(s->async, sample))
605 if (devpriv->aiCount > 0) /* < 0, means read forever */
612 Handle all rtd520 interrupts.
613 Runs atomically and is never re-entered.
614 This is a "slow handler"; other interrupts may be active.
615 The data conversion may someday happen in a "bottom half".
617 static irqreturn_t rtd_interrupt(int irq, /* interrupt number (ignored) */
619 { /* our data *//* cpu context (ignored) */
620 struct comedi_device *dev = d;
621 struct comedi_subdevice *s = &dev->subdevices[0];
622 struct rtdPrivate *devpriv = dev->private;
630 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
631 /* check for FIFO full, this automatically halts the ADC! */
632 if (!(fifoStatus & FS_ADC_NOT_FULL)) /* 0 -> full */
635 status = readw(devpriv->las0 + LAS0_IT);
636 /* if interrupt was not caused by our board, or handled above */
640 if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */
642 * since the priority interrupt controller may have queued
643 * a sample counter interrupt, even though we have already
644 * finished, we must handle the possibility that there is
647 if (!(fifoStatus & FS_ADC_HEMPTY)) {
649 if (ai_read_n(dev, s, devpriv->fifoLen / 2) < 0)
652 if (0 == devpriv->aiCount)
655 comedi_event(dev, s);
656 } else if (devpriv->transCount > 0) {
657 if (fifoStatus & FS_ADC_NOT_EMPTY) {
659 if (ai_read_n(dev, s, devpriv->transCount) < 0)
662 if (0 == devpriv->aiCount)
665 comedi_event(dev, s);
670 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
674 /* clear the interrupt */
675 devpriv->intClearMask = status;
676 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
677 readw(devpriv->las0 + LAS0_CLEAR);
681 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
682 s->async->events |= COMEDI_CB_ERROR;
683 devpriv->aiCount = 0; /* stop and don't transfer any more */
684 /* fall into transferDone */
687 /* pacer stop source: SOFTWARE */
688 writel(0, devpriv->las0 + LAS0_PACER_STOP);
689 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
690 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
691 devpriv->intMask = 0;
692 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
694 if (devpriv->aiCount > 0) { /* there shouldn't be anything left */
695 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
696 ai_read_dregs(dev, s); /* read anything left in FIFO */
699 s->async->events |= COMEDI_CB_EOA; /* signal end to comedi */
700 comedi_event(dev, s);
702 /* clear the interrupt */
703 status = readw(devpriv->las0 + LAS0_IT);
704 devpriv->intClearMask = status;
705 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
706 readw(devpriv->las0 + LAS0_CLEAR);
708 fifoStatus = readl(devpriv->las0 + LAS0_ADC);
709 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
715 cmdtest tests a particular command to see if it is valid.
716 Using the cmdtest ioctl, a user can create a valid cmd
717 and then have it executed by the cmd ioctl (asynchronously).
719 cmdtest returns 1,2,3,4 or 0, depending on which tests
723 static int rtd_ai_cmdtest(struct comedi_device *dev,
724 struct comedi_subdevice *s, struct comedi_cmd *cmd)
729 /* Step 1 : check if triggers are trivially valid */
731 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
732 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
733 TRIG_TIMER | TRIG_EXT);
734 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT);
735 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
736 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
741 /* Step 2a : make sure trigger sources are unique */
743 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
744 err |= cfc_check_trigger_is_unique(cmd->convert_src);
745 err |= cfc_check_trigger_is_unique(cmd->stop_src);
747 /* Step 2b : and mutually compatible */
752 /* Step 3: check if arguments are trivially valid */
754 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
756 if (cmd->scan_begin_src == TRIG_TIMER) {
757 /* Note: these are time periods, not actual rates */
758 if (1 == cmd->chanlist_len) { /* no scanning */
759 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
761 rtd_ns_to_timer(&cmd->scan_begin_arg,
765 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
767 rtd_ns_to_timer(&cmd->scan_begin_arg,
772 if (cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
774 rtd_ns_to_timer(&cmd->scan_begin_arg,
778 if (cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
780 rtd_ns_to_timer(&cmd->scan_begin_arg,
786 /* external trigger */
787 /* should be level/edge, hi/lo specification here */
788 /* should specify multiple external triggers */
789 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
792 if (cmd->convert_src == TRIG_TIMER) {
793 if (1 == cmd->chanlist_len) { /* no scanning */
794 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
796 rtd_ns_to_timer(&cmd->convert_arg,
800 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
802 rtd_ns_to_timer(&cmd->convert_arg,
807 if (cfc_check_trigger_arg_min(&cmd->convert_arg,
809 rtd_ns_to_timer(&cmd->convert_arg,
813 if (cfc_check_trigger_arg_max(&cmd->convert_arg,
815 rtd_ns_to_timer(&cmd->convert_arg,
821 /* external trigger */
823 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
826 if (cmd->stop_src == TRIG_COUNT) {
827 /* TODO check for rounding error due to counter wrap */
830 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
837 /* step 4: fix up any arguments */
839 if (cmd->chanlist_len > RTD_MAX_CHANLIST) {
840 cmd->chanlist_len = RTD_MAX_CHANLIST;
843 if (cmd->scan_begin_src == TRIG_TIMER) {
844 tmp = cmd->scan_begin_arg;
845 rtd_ns_to_timer(&cmd->scan_begin_arg,
846 cmd->flags & TRIG_ROUND_MASK);
847 if (tmp != cmd->scan_begin_arg)
851 if (cmd->convert_src == TRIG_TIMER) {
852 tmp = cmd->convert_arg;
853 rtd_ns_to_timer(&cmd->convert_arg,
854 cmd->flags & TRIG_ROUND_MASK);
855 if (tmp != cmd->convert_arg)
858 if (cmd->scan_begin_src == TRIG_TIMER
859 && (cmd->scan_begin_arg
860 < (cmd->convert_arg * cmd->scan_end_arg))) {
861 cmd->scan_begin_arg =
862 cmd->convert_arg * cmd->scan_end_arg;
874 Execute a analog in command with many possible triggering options.
875 The data get stored in the async structure of the subdevice.
876 This is usually done by an interrupt handler.
877 Userland gets to the data using read calls.
879 static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
881 struct rtdPrivate *devpriv = dev->private;
882 struct comedi_cmd *cmd = &s->async->cmd;
885 /* stop anything currently running */
886 /* pacer stop source: SOFTWARE */
887 writel(0, devpriv->las0 + LAS0_PACER_STOP);
888 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
889 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
890 devpriv->intMask = 0;
891 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
892 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
893 writel(0, devpriv->las0 + LAS0_OVERRUN);
895 /* start configuration */
896 /* load channel list and reset CGT */
897 rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
899 /* setup the common case and override if needed */
900 if (cmd->chanlist_len > 1) {
901 /* pacer start source: SOFTWARE */
902 writel(0, devpriv->las0 + LAS0_PACER_START);
903 /* burst trigger source: PACER */
904 writel(1, devpriv->las0 + LAS0_BURST_START);
905 /* ADC conversion trigger source: BURST */
906 writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
907 } else { /* single channel */
908 /* pacer start source: SOFTWARE */
909 writel(0, devpriv->las0 + LAS0_PACER_START);
910 /* ADC conversion trigger source: PACER */
911 writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
913 writel((devpriv->fifoLen / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
915 if (TRIG_TIMER == cmd->scan_begin_src) {
916 /* scan_begin_arg is in nanoseconds */
917 /* find out how many samples to wait before transferring */
918 if (cmd->flags & TRIG_WAKE_EOS) {
920 * this may generate un-sustainable interrupt rates
921 * the application is responsible for doing the
924 devpriv->transCount = cmd->chanlist_len;
925 devpriv->flags |= SEND_EOS;
927 /* arrange to transfer data periodically */
930 (TRANS_TARGET_PERIOD * cmd->chanlist_len) /
932 if (devpriv->transCount < cmd->chanlist_len) {
933 /* transfer after each scan (and avoid 0) */
934 devpriv->transCount = cmd->chanlist_len;
935 } else { /* make a multiple of scan length */
936 devpriv->transCount =
937 (devpriv->transCount +
938 cmd->chanlist_len - 1)
940 devpriv->transCount *= cmd->chanlist_len;
942 devpriv->flags |= SEND_EOS;
944 if (devpriv->transCount >= (devpriv->fifoLen / 2)) {
945 /* out of counter range, use 1/2 fifo instead */
946 devpriv->transCount = 0;
947 devpriv->flags &= ~SEND_EOS;
949 /* interrupt for each transfer */
950 writel((devpriv->transCount - 1) & 0xffff,
951 devpriv->las0 + LAS0_ACNT);
953 } else { /* unknown timing, just use 1/2 FIFO */
954 devpriv->transCount = 0;
955 devpriv->flags &= ~SEND_EOS;
957 /* pacer clock source: INTERNAL 8MHz */
958 writel(1, devpriv->las0 + LAS0_PACER_SELECT);
959 /* just interrupt, don't stop */
960 writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
962 /* BUG??? these look like enumerated values, but they are bit fields */
964 /* First, setup when to stop */
965 switch (cmd->stop_src) {
966 case TRIG_COUNT: /* stop after N scans */
967 devpriv->aiCount = cmd->stop_arg * cmd->chanlist_len;
968 if ((devpriv->transCount > 0)
969 && (devpriv->transCount > devpriv->aiCount)) {
970 devpriv->transCount = devpriv->aiCount;
974 case TRIG_NONE: /* stop when cancel is called */
975 devpriv->aiCount = -1; /* read forever */
980 switch (cmd->scan_begin_src) {
981 case TRIG_TIMER: /* periodic scanning */
982 timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
984 /* set PACER clock */
985 writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
990 /* pacer start source: EXTERNAL */
991 writel(1, devpriv->las0 + LAS0_PACER_START);
995 /* Sample timing within a scan */
996 switch (cmd->convert_src) {
997 case TRIG_TIMER: /* periodic */
998 if (cmd->chanlist_len > 1) {
999 /* only needed for multi-channel */
1000 timer = rtd_ns_to_timer(&cmd->convert_arg,
1001 TRIG_ROUND_NEAREST);
1002 /* setup BURST clock */
1003 writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
1008 case TRIG_EXT: /* external */
1009 /* burst trigger source: EXTERNAL */
1010 writel(2, devpriv->las0 + LAS0_BURST_START);
1013 /* end configuration */
1015 /* This doesn't seem to work. There is no way to clear an interrupt
1016 that the priority controller has queued! */
1017 devpriv->intClearMask = ~0;
1018 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1019 readw(devpriv->las0 + LAS0_CLEAR);
1021 /* TODO: allow multiple interrupt sources */
1022 if (devpriv->transCount > 0) { /* transfer every N samples */
1023 devpriv->intMask = IRQM_ADC_ABOUT_CNT;
1024 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1025 } else { /* 1/2 FIFO transfers */
1026 devpriv->intMask = IRQM_ADC_ABOUT_CNT;
1027 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1030 /* BUG: start_src is ASSUMED to be TRIG_NOW */
1031 /* BUG? it seems like things are running before the "start" */
1032 readl(devpriv->las0 + LAS0_PACER); /* start pacer */
1037 Stop a running data acquisition.
1039 static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1041 struct rtdPrivate *devpriv = dev->private;
1045 /* pacer stop source: SOFTWARE */
1046 writel(0, devpriv->las0 + LAS0_PACER_STOP);
1047 writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
1048 writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
1049 devpriv->intMask = 0;
1050 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1051 devpriv->aiCount = 0; /* stop and don't transfer any more */
1052 status = readw(devpriv->las0 + LAS0_IT);
1053 overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
1058 Output one (or more) analog values to a single port as fast as possible.
1060 static int rtd_ao_winsn(struct comedi_device *dev,
1061 struct comedi_subdevice *s, struct comedi_insn *insn,
1064 struct rtdPrivate *devpriv = dev->private;
1066 int chan = CR_CHAN(insn->chanspec);
1067 int range = CR_RANGE(insn->chanspec);
1069 /* Configure the output range (table index matches the range values) */
1070 writew(range & 7, devpriv->las0 +
1071 ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
1073 /* Writing a list of values to an AO channel is probably not
1074 * very useful, but that's how the interface is defined. */
1075 for (i = 0; i < insn->n; ++i) {
1076 int val = data[i] << 3;
1077 int stat = 0; /* initialize to avoid bogus warning */
1080 /* VERIFY: comedi range and offset conversions */
1082 if ((range > 1) /* bipolar */
1083 && (data[i] < 2048)) {
1084 /* offset and sign extend */
1085 val = (((int)data[i]) - 2048) << 3;
1086 } else { /* unipolor */
1090 /* a typical programming sequence */
1091 writew(val, devpriv->las1 +
1092 ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
1093 writew(0, devpriv->las0 +
1094 ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
1096 devpriv->aoValue[chan] = data[i]; /* save for read back */
1098 for (ii = 0; ii < RTD_DAC_TIMEOUT; ++ii) {
1099 stat = readl(devpriv->las0 + LAS0_ADC);
1100 /* 1 -> not empty */
1101 if (stat & ((0 == chan) ? FS_DAC1_NOT_EMPTY :
1106 if (ii >= RTD_DAC_TIMEOUT)
1110 /* return the number of samples read/written */
1114 /* AO subdevices should have a read insn as well as a write insn.
1115 * Usually this means copying a value stored in devpriv. */
1116 static int rtd_ao_rinsn(struct comedi_device *dev,
1117 struct comedi_subdevice *s, struct comedi_insn *insn,
1120 struct rtdPrivate *devpriv = dev->private;
1122 int chan = CR_CHAN(insn->chanspec);
1124 for (i = 0; i < insn->n; i++)
1125 data[i] = devpriv->aoValue[chan];
1132 Write a masked set of bits and the read back the port.
1133 We track what the bits should be (i.e. we don't read the port first).
1135 DIO devices are slightly special. Although it is possible to
1136 * implement the insn_read/insn_write interface, it is much more
1137 * useful to applications if you implement the insn_bits interface.
1138 * This allows packed reading/writing of the DIO channels. The
1139 * comedi core can convert between insn_bits and insn_read/write
1141 static int rtd_dio_insn_bits(struct comedi_device *dev,
1142 struct comedi_subdevice *s,
1143 struct comedi_insn *insn, unsigned int *data)
1145 struct rtdPrivate *devpriv = dev->private;
1147 /* The insn data is a mask in data[0] and the new data
1148 * in data[1], each channel cooresponding to a bit. */
1150 s->state &= ~data[0];
1151 s->state |= data[0] & data[1];
1153 /* Write out the new digital output lines */
1154 writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
1156 /* on return, data[1] contains the value of the digital
1158 data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
1164 Configure one bit on a IO port as Input or Output (hence the name :-).
1166 static int rtd_dio_insn_config(struct comedi_device *dev,
1167 struct comedi_subdevice *s,
1168 struct comedi_insn *insn, unsigned int *data)
1170 struct rtdPrivate *devpriv = dev->private;
1171 int chan = CR_CHAN(insn->chanspec);
1173 /* The input or output configuration of each digital line is
1174 * configured by a special insn_config instruction. chanspec
1175 * contains the channel to be changed, and data[0] contains the
1176 * value COMEDI_INPUT or COMEDI_OUTPUT. */
1178 case INSN_CONFIG_DIO_OUTPUT:
1179 s->io_bits |= 1 << chan; /* 1 means Out */
1181 case INSN_CONFIG_DIO_INPUT:
1182 s->io_bits &= ~(1 << chan);
1184 case INSN_CONFIG_DIO_QUERY:
1186 (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
1193 /* TODO support digital match interrupts and strobes */
1194 devpriv->dioStatus = 0x01; /* set direction */
1195 writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
1196 writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
1197 devpriv->dioStatus = 0x00; /* clear interrupts */
1198 writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
1200 /* port1 can only be all input or all output */
1202 /* there are also 2 user input lines and 2 user output lines */
1207 static void rtd_reset(struct comedi_device *dev)
1209 struct rtdPrivate *devpriv = dev->private;
1211 writel(0, devpriv->las0 + LAS0_BOARD_RESET);
1212 udelay(100); /* needed? */
1213 writel(0, devpriv->lcfg + PLX_INTRCS_REG);
1214 devpriv->intMask = 0;
1215 writew(devpriv->intMask, devpriv->las0 + LAS0_IT);
1216 devpriv->intClearMask = ~0;
1217 writew(devpriv->intClearMask, devpriv->las0 + LAS0_CLEAR);
1218 readw(devpriv->las0 + LAS0_CLEAR);
1222 * initialize board, per RTD spec
1223 * also, initialize shadow registers
1225 static void rtd_init_board(struct comedi_device *dev)
1227 struct rtdPrivate *devpriv = dev->private;
1231 writel(0, devpriv->las0 + LAS0_OVERRUN);
1232 writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
1233 writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
1234 writel(0, devpriv->las0 + LAS0_DAC1_RESET);
1235 writel(0, devpriv->las0 + LAS0_DAC2_RESET);
1236 /* clear digital IO fifo */
1237 devpriv->dioStatus = 0;
1238 writew(devpriv->dioStatus, devpriv->las0 + LAS0_DIO_STATUS);
1239 devpriv->utcCtrl[0] = (0 << 6) | 0x30;
1240 devpriv->utcCtrl[1] = (1 << 6) | 0x30;
1241 devpriv->utcCtrl[2] = (2 << 6) | 0x30;
1242 devpriv->utcCtrl[3] = (3 << 6) | 0x00;
1243 writeb(devpriv->utcCtrl[0], devpriv->las0 + LAS0_UTC_CTRL);
1244 writeb(devpriv->utcCtrl[1], devpriv->las0 + LAS0_UTC_CTRL);
1245 writeb(devpriv->utcCtrl[2], devpriv->las0 + LAS0_UTC_CTRL);
1246 writeb(devpriv->utcCtrl[3], devpriv->las0 + LAS0_UTC_CTRL);
1247 /* TODO: set user out source ??? */
1250 /* The RTD driver does this */
1251 static void rtd_pci_latency_quirk(struct comedi_device *dev,
1252 struct pci_dev *pcidev)
1254 unsigned char pci_latency;
1256 pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency);
1257 if (pci_latency < 32) {
1258 dev_info(dev->class_dev,
1259 "PCI latency changed from %d to %d\n",
1261 pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32);
1265 static int rtd_auto_attach(struct comedi_device *dev,
1266 unsigned long context)
1268 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1269 const struct rtdBoard *thisboard = NULL;
1270 struct rtdPrivate *devpriv;
1271 struct comedi_subdevice *s;
1274 if (context < ARRAY_SIZE(rtd520Boards))
1275 thisboard = &rtd520Boards[context];
1278 dev->board_ptr = thisboard;
1279 dev->board_name = thisboard->name;
1281 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1284 dev->private = devpriv;
1286 ret = comedi_pci_enable(dev);
1290 devpriv->las0 = ioremap_nocache(pci_resource_start(pcidev, 2),
1291 pci_resource_len(pcidev, 2));
1292 devpriv->las1 = ioremap_nocache(pci_resource_start(pcidev, 3),
1293 pci_resource_len(pcidev, 3));
1294 devpriv->lcfg = ioremap_nocache(pci_resource_start(pcidev, 0),
1295 pci_resource_len(pcidev, 0));
1296 if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
1299 rtd_pci_latency_quirk(dev, pcidev);
1302 ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED,
1303 dev->board_name, dev);
1305 dev->irq = pcidev->irq;
1308 ret = comedi_alloc_subdevices(dev, 4);
1312 s = &dev->subdevices[0];
1313 /* analog input subdevice */
1314 s->type = COMEDI_SUBD_AI;
1315 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF;
1317 s->maxdata = 0x0fff;
1318 s->range_table = thisboard->ai_range;
1319 s->len_chanlist = RTD_MAX_CHANLIST;
1320 s->insn_read = rtd_ai_rinsn;
1322 dev->read_subdev = s;
1323 s->subdev_flags |= SDF_CMD_READ;
1324 s->do_cmd = rtd_ai_cmd;
1325 s->do_cmdtest = rtd_ai_cmdtest;
1326 s->cancel = rtd_ai_cancel;
1329 s = &dev->subdevices[1];
1330 /* analog output subdevice */
1331 s->type = COMEDI_SUBD_AO;
1332 s->subdev_flags = SDF_WRITABLE;
1334 s->maxdata = 0x0fff;
1335 s->range_table = &rtd_ao_range;
1336 s->insn_write = rtd_ao_winsn;
1337 s->insn_read = rtd_ao_rinsn;
1339 s = &dev->subdevices[2];
1340 /* digital i/o subdevice */
1341 s->type = COMEDI_SUBD_DIO;
1342 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1343 /* we only support port 0 right now. Ignoring port 1 and user IO */
1346 s->range_table = &range_digital;
1347 s->insn_bits = rtd_dio_insn_bits;
1348 s->insn_config = rtd_dio_insn_config;
1350 /* timer/counter subdevices (not currently supported) */
1351 s = &dev->subdevices[3];
1352 s->type = COMEDI_SUBD_COUNTER;
1353 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1355 s->maxdata = 0xffff;
1357 rtd_init_board(dev);
1359 ret = rtd520_probe_fifo_depth(dev);
1362 devpriv->fifoLen = ret;
1365 writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG);
1367 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
1372 static void rtd_detach(struct comedi_device *dev)
1374 struct rtdPrivate *devpriv = dev->private;
1377 /* Shut down any board ops by resetting it */
1378 if (devpriv->las0 && devpriv->lcfg)
1381 writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
1382 ~(ICS_PLIE | ICS_DMA0_E | ICS_DMA1_E),
1383 devpriv->lcfg + PLX_INTRCS_REG);
1384 free_irq(dev->irq, dev);
1387 iounmap(devpriv->las0);
1389 iounmap(devpriv->las1);
1391 iounmap(devpriv->lcfg);
1393 comedi_pci_disable(dev);
1396 static struct comedi_driver rtd520_driver = {
1397 .driver_name = "rtd520",
1398 .module = THIS_MODULE,
1399 .auto_attach = rtd_auto_attach,
1400 .detach = rtd_detach,
1403 static int rtd520_pci_probe(struct pci_dev *dev,
1404 const struct pci_device_id *id)
1406 return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data);
1409 static DEFINE_PCI_DEVICE_TABLE(rtd520_pci_table) = {
1410 { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 },
1411 { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 },
1414 MODULE_DEVICE_TABLE(pci, rtd520_pci_table);
1416 static struct pci_driver rtd520_pci_driver = {
1418 .id_table = rtd520_pci_table,
1419 .probe = rtd520_pci_probe,
1420 .remove = comedi_pci_auto_unconfig,
1422 module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver);
1424 MODULE_AUTHOR("Comedi http://www.comedi.org");
1425 MODULE_DESCRIPTION("Comedi low-level driver");
1426 MODULE_LICENSE("GPL");