3 Sensoray s626 Comedi driver
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 Description: Sensoray 626 driver
30 Devices: [Sensoray] 626 (s626)
31 Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32 Updated: Fri, 15 Feb 2008 10:28:42 +0000
35 Configuration options: not applicable, uses PCI auto config
37 INSN_CONFIG instructions:
45 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
46 supported configuration options:
52 Every channel must be configured before reading.
56 insn.insn=INSN_CONFIG; //configuration instruction
57 insn.n=1; //number of operation (must be 1)
58 insn.data=&initialvalue; //initial value loaded into encoder
59 //during configuration
60 insn.subdev=5; //encoder subdevice
61 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
64 comedi_do_insn(cf,&insn); //executing configuration
67 #include <linux/pci.h>
68 #include <linux/interrupt.h>
69 #include <linux/kernel.h>
70 #include <linux/types.h>
72 #include "../comedidev.h"
74 #include "comedi_fc.h"
77 #define PCI_VENDOR_ID_S626 0x1131
78 #define PCI_DEVICE_ID_S626 0x7146
79 #define PCI_SUBVENDOR_ID_S626 0x6000
80 #define PCI_SUBDEVICE_ID_S626 0x0272
83 void __iomem *base_addr;
84 uint8_t ai_cmd_running; /* ai_cmd is running */
85 uint8_t ai_continous; /* continous acquisition */
86 int ai_sample_count; /* number of samples to acquire */
87 unsigned int ai_sample_timer;
88 /* time between samples in units of the timer */
89 int ai_convert_count; /* conversion counter */
90 unsigned int ai_convert_timer;
91 /* time between conversion in units of the timer */
92 uint16_t CounterIntEnabs;
93 /* Counter interrupt enable mask for MISC2 register. */
94 uint8_t AdcItems; /* Number of items in ADC poll list. */
95 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
96 struct bufferDMA ANABuf;
97 /* DMA buffer used to receive ADC data and hold DAC data. */
99 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
100 uint16_t Dacpol; /* Image of DAC polarity register. */
101 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
102 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
104 /* I2C device address for onboard EEPROM (board rev dependent). */
106 unsigned int ao_readback[S626_DAC_CHANNELS];
121 static struct dio_private dio_private_A = {
123 .WRDOut = LP_WRDOUTA,
124 .RDEdgSel = LP_RDEDGSELA,
125 .WREdgSel = LP_WREDGSELA,
126 .RDCapSel = LP_RDCAPSELA,
127 .WRCapSel = LP_WRCAPSELA,
128 .RDCapFlg = LP_RDCAPFLGA,
129 .RDIntSel = LP_RDINTSELA,
130 .WRIntSel = LP_WRINTSELA,
133 static struct dio_private dio_private_B = {
135 .WRDOut = LP_WRDOUTB,
136 .RDEdgSel = LP_RDEDGSELB,
137 .WREdgSel = LP_WREDGSELB,
138 .RDCapSel = LP_RDCAPSELB,
139 .WRCapSel = LP_WRCAPSELB,
140 .RDCapFlg = LP_RDCAPFLGB,
141 .RDIntSel = LP_RDINTSELB,
142 .WRIntSel = LP_WRINTSELB,
145 static struct dio_private dio_private_C = {
147 .WRDOut = LP_WRDOUTC,
148 .RDEdgSel = LP_RDEDGSELC,
149 .WREdgSel = LP_WREDGSELC,
150 .RDCapSel = LP_RDCAPSELC,
151 .WRCapSel = LP_WRCAPSELC,
152 .RDCapFlg = LP_RDCAPFLGC,
153 .RDIntSel = LP_RDINTSELC,
154 .WRIntSel = LP_WRINTSELC,
157 /* to group dio devices (48 bits mask and data are not allowed ???)
158 static struct dio_private *dio_private_word[]={
165 #define diopriv ((struct dio_private *)s->private)
167 /* COUNTER OBJECT ------------------------------------------------ */
169 /* Pointers to functions that differ for A and B counters: */
170 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
171 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
172 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
173 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
174 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
175 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
176 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
177 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
178 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
179 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
181 uint16_t MyCRA; /* Address of CRA register. */
182 uint16_t MyCRB; /* Address of CRB register. */
183 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
185 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
188 #define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
190 /* Counter overflow/index event flag masks for RDMISC2. */
191 #define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
192 #define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
193 #define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
195 /* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
196 /* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
198 /* enab/disable a function or test status bit(s) that are accessed */
199 /* through Main Control Registers 1 or 2. */
200 #define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
202 #define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
204 #define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
206 /* #define WR7146(REGARDS,CTRLWORD)
207 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
208 #define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
210 /* #define RR7146(REGARDS)
211 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
212 #define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
214 #define BUGFIX_STREG(REGADRS) (REGADRS - 4)
216 /* Write a time slot control record to TSL2. */
217 #define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
218 #define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
220 /* Code macros used for constructing I2C command bytes. */
221 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
222 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
223 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
225 static const struct comedi_lrange s626_range_table = { 2, {
231 /* Execute a DEBI transfer. This must be called from within a */
232 /* critical section. */
233 static void DEBItransfer(struct comedi_device *dev)
235 struct s626_private *devpriv = dev->private;
237 /* Initiate upload of shadow RAM to DEBI control register. */
238 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
240 /* Wait for completion of upload from shadow RAM to DEBI control */
242 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
245 /* Wait until DEBI transfer is done. */
246 while (RR7146(P_PSR) & PSR_DEBI_S)
250 /* Initialize the DEBI interface for all transfers. */
252 static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
254 struct s626_private *devpriv = dev->private;
257 /* Set up DEBI control register value in shadow RAM. */
258 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
260 /* Execute the DEBI transfer. */
263 /* Fetch target register value. */
264 retval = (uint16_t) RR7146(P_DEBIAD);
266 /* Return register value. */
270 /* Write a value to a gate array register. */
271 static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
273 struct s626_private *devpriv = dev->private;
275 /* Set up DEBI control register value in shadow RAM. */
276 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
277 WR7146(P_DEBIAD, wdata);
279 /* Execute the DEBI transfer. */
283 /* Replace the specified bits in a gate array register. Imports: mask
284 * specifies bits that are to be preserved, wdata is new value to be
285 * or'd with the masked original.
287 static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
290 struct s626_private *devpriv = dev->private;
292 /* Copy target gate array register into P_DEBIAD register. */
293 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
294 /* Set up DEBI control reg value in shadow RAM. */
295 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
297 /* Write back the modified image. */
298 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
299 /* Set up DEBI control reg value in shadow RAM. */
301 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
302 /* Modify the register image. */
303 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
306 /* ************** EEPROM ACCESS FUNCTIONS ************** */
308 static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
310 struct s626_private *devpriv = dev->private;
312 /* Write I2C command to I2C Transfer Control shadow register. */
313 WR7146(P_I2CCTRL, val);
315 /* Upload I2C shadow registers into working registers and wait for */
316 /* upload confirmation. */
318 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
319 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
322 /* Wait until I2C bus transfer is finished or an error occurs. */
323 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
326 /* Return non-zero if I2C error occurred. */
327 return RR7146(P_I2CCTRL) & I2C_ERR;
331 /* Read uint8_t from EEPROM. */
332 static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
334 struct s626_private *devpriv = dev->private;
337 /* Send EEPROM target address. */
338 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
339 /* Byte2 = I2C command: write to I2C EEPROM device. */
340 | I2C_B1(I2C_ATTRSTOP, addr)
341 /* Byte1 = EEPROM internal target address. */
342 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
343 /* Abort function and declare error if handshake failed. */
346 /* Execute EEPROM read. */
347 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
351 /* from I2C EEPROM */
353 |I2C_B1(I2C_ATTRSTOP, 0)
358 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
360 /* Abort function and declare error if handshake failed. */
363 /* Return copy of EEPROM value. */
364 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
368 /* *********** DAC FUNCTIONS *********** */
370 /* Slot 0 base settings. */
371 #define VECT0 (XSD2 | RSD3 | SIB_A2)
372 /* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
374 /* TrimDac LogicalChan-to-PhysicalChan mapping table. */
375 static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
377 /* TrimDac LogicalChan-to-EepromAdrs mapping table. */
378 static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
380 /* Private helper function: Transmit serial data to DAC via Audio
381 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
382 * Dacpol contains valid target image.
384 static void SendDAC(struct comedi_device *dev, uint32_t val)
386 struct s626_private *devpriv = dev->private;
388 /* START THE SERIAL CLOCK RUNNING ------------- */
390 /* Assert DAC polarity control and enable gating of DAC serial clock
391 * and audio bit stream signals. At this point in time we must be
392 * assured of being in time slot 0. If we are not in slot 0, the
393 * serial clock and audio stream signals will be disabled; this is
394 * because the following DEBIwrite statement (which enables signals
395 * to be passed through the gate array) would execute before the
396 * trailing edge of WS1/WS3 (which turns off the signals), thus
397 * causing the signals to be inactive during the DAC write.
399 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
401 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
403 /* Copy DAC setpoint value to DAC's output DMA buffer. */
405 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
406 *devpriv->pDacWBuf = val;
408 /* enab the output DMA transfer. This will cause the DMAC to copy
409 * the DAC's data value to A2's output FIFO. The DMA transfer will
410 * then immediately terminate because the protection address is
411 * reached upon transfer of the first DWORD value.
413 MC_ENABLE(P_MC1, MC1_A2OUT);
415 /* While the DMA transfer is executing ... */
417 /* Reset Audio2 output FIFO's underflow flag (along with any other
418 * FIFO underflow/overflow flags). When set, this flag will
419 * indicate that we have emerged from slot 0.
421 WR7146(P_ISR, ISR_AFOU);
423 /* Wait for the DMA transfer to finish so that there will be data
424 * available in the FIFO when time slot 1 tries to transfer a DWORD
425 * from the FIFO to the output buffer register. We test for DMA
426 * Done by polling the DMAC enable flag; this flag is automatically
427 * cleared when the transfer has finished.
429 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
432 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
434 /* FIFO data is now available, so we enable execution of time slots
435 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
436 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
439 SETVECT(0, XSD2 | RSD3 | SIB_A2);
441 /* Wait for slot 1 to execute to ensure that the Packet will be
442 * transmitted. This is detected by polling the Audio2 output FIFO
443 * underflow flag, which will be set when slot 1 execution has
444 * finished transferring the DAC's data DWORD from the output FIFO
445 * to the output buffer register.
447 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
450 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
451 * back to slot 0 after executing the EOS in slot 5. Also,
452 * simultaneously shift out and in the 0x00 that is ALWAYS the value
453 * stored in the last byte to be shifted out of the FIFO's DWORD
456 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
458 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
460 /* Wait for the TSL to finish executing all time slots before
461 * exiting this function. We must do this so that the next DAC
462 * write doesn't start, thereby enabling clock/chip select signals:
464 * 1. Before the TSL sequence cycles back to slot 0, which disables
465 * the clock/cs signal gating and traps slot // list execution.
466 * we have not yet finished slot 5 then the clock/cs signals are
467 * still gated and we have not finished transmitting the stream.
469 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
470 * this case, the slot sequence is currently repeating, but with
471 * clock/cs signals disabled. We must wait for slot 0 to trap
472 * execution before setting up the next DAC setpoint DMA transfer
473 * and enabling the clock/cs signals. To detect the end of slot 5,
474 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
475 * the TSL has not yet finished executing slot 5 ...
477 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
478 /* The trap was set on time and we are still executing somewhere
479 * in slots 2-5, so we now wait for slot 0 to execute and trap
480 * TSL execution. This is detected when FB_BUFFER2 MSB changes
481 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
482 * out/in on SD2 the 0x00 that is always referenced by slot 5.
484 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
487 /* Either (1) we were too late setting the slot 0 trap; the TSL
488 * sequencer restarted slot 0 before we could set the EOS trap flag,
489 * or (2) we were not late and execution is now trapped at slot 0.
490 * In either case, we must now change slot 0 so that it will store
491 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
492 * In order to do this, we reprogram slot 0 so that it will shift in
493 * SD3, which is driven only by a pull-up resistor.
495 SETVECT(0, RSD3 | SIB_A2 | EOS);
497 /* Wait for slot 0 to execute, at which time the TSL is setup for
498 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
501 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
505 /* Private helper function: Write setpoint to an application DAC channel. */
506 static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
508 struct s626_private *devpriv = dev->private;
509 register uint16_t signmask;
510 register uint32_t WSImage;
512 /* Adjust DAC data polarity and set up Polarity Control Register */
514 signmask = 1 << chan;
517 devpriv->Dacpol |= signmask;
519 devpriv->Dacpol &= ~signmask;
521 /* Limit DAC setpoint value to valid range. */
522 if ((uint16_t) dacdata > 0x1FFF)
525 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
526 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
527 * data to a non-existent TrimDac channel just to keep the clock
528 * running after sending data to the target DAC. This is necessary
529 * to eliminate the clock glitch that would otherwise occur at the
530 * end of the target DAC's serial data stream. When the sequence
531 * restarts at V0 (after executing V5), the gate array automatically
532 * disables gating for the DAC clock and all DAC chip selects.
535 WSImage = (chan & 2) ? WS1 : WS2;
536 /* Choose DAC chip select to be asserted. */
537 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
538 /* Slot 2: Transmit high data byte to target DAC. */
539 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
540 /* Slot 3: Transmit low data byte to target DAC. */
541 SETVECT(4, XSD2 | XFIFO_3 | WS3);
542 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
543 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
544 /* Slot 5: running after writing target DAC's low data byte. */
546 /* Construct and transmit target DAC's serial packet:
547 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
548 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
549 * to a non-existent TrimDac channel) that serves to keep the clock
550 * running after the packet has been sent to the target DAC.
552 SendDAC(dev, 0x0F000000
553 /* Continue clock after target DAC data (write to non-existent trimdac). */
555 /* Address the two main dual-DAC devices (TSL's chip select enables
557 | ((uint32_t) (chan & 1) << 15)
558 /* Address the DAC channel within the device. */
559 | (uint32_t) dacdata); /* Include DAC setpoint data. */
563 static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
566 struct s626_private *devpriv = dev->private;
569 /* Save the new setpoint in case the application needs to read it back later. */
570 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
572 /* Map logical channel number to physical channel number. */
573 chan = (uint32_t) trimchan[LogicalChan];
575 /* Set up TSL2 records for TrimDac write operation. All slots shift
576 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
580 SETVECT(2, XSD2 | XFIFO_1 | WS3);
581 /* Slot 2: Send high uint8_t to target TrimDac. */
582 SETVECT(3, XSD2 | XFIFO_0 | WS3);
583 /* Slot 3: Send low uint8_t to target TrimDac. */
584 SETVECT(4, XSD2 | XFIFO_3 | WS1);
585 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
586 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
587 /* Slot 5: Send NOP low uint8_t to DAC0. */
589 /* Construct and transmit target DAC's serial packet:
590 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
591 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
592 * WORD value (that writes a channel 0 NOP command to a non-existent
593 * main DAC channel) that serves to keep the clock running after the
594 * packet has been sent to the target DAC.
597 /* Address the DAC channel within the trimdac device. */
598 SendDAC(dev, ((uint32_t) chan << 8)
599 | (uint32_t) DacData); /* Include DAC setpoint data. */
602 static void LoadTrimDACs(struct comedi_device *dev)
606 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
607 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
608 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
611 /* ****** COUNTER FUNCTIONS ******* */
612 /* All counter functions address a specific counter by means of the
613 * "Counter" argument, which is a logical counter number. The Counter
614 * argument may have any of the following legal values: 0=0A, 1=1A,
615 * 2=2A, 3=0B, 4=1B, 5=2B.
618 /* Read a counter's output latch. */
619 static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
621 register uint32_t value;
623 /* Latch counts and fetch LSW of latched counts value. */
624 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
626 /* Fetch MSW of latched counts and combine with LSW. */
627 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
629 /* Return latched counts. */
633 /* Return/set a counter pair's latch trigger source. 0: On read
634 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
637 static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
640 DEBIreplace(dev, k->MyCRB,
641 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
642 (uint16_t) (value << CRBBIT_LATCHSRC));
645 /* Write value into counter preload register. */
646 static void Preload(struct comedi_device *dev, struct enc_private *k,
649 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value);
650 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
651 (uint16_t) (value >> 16));
654 static unsigned int s626_ai_reg_to_uint(int data)
656 unsigned int tempdata;
658 tempdata = (data >> 18);
659 if (tempdata & 0x2000)
662 tempdata += (1 << 13);
667 /* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
671 static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
674 unsigned int bitmask;
677 /* select dio bank */
679 bitmask = 1 << (chan - (16 * group));
681 /* set channel to capture positive edge */
682 status = DEBIread(dev,
683 ((struct dio_private *)(dev->subdevices + 2 +
684 group)->private)->RDEdgSel);
686 ((struct dio_private *)(dev->subdevices + 2 +
687 group)->private)->WREdgSel,
690 /* enable interrupt on selected channel */
691 status = DEBIread(dev,
692 ((struct dio_private *)(dev->subdevices + 2 +
693 group)->private)->RDIntSel);
695 ((struct dio_private *)(dev->subdevices + 2 +
696 group)->private)->WRIntSel,
699 /* enable edge capture write command */
700 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
702 /* enable edge capture on selected channel */
703 status = DEBIread(dev,
704 ((struct dio_private *)(dev->subdevices + 2 +
705 group)->private)->RDCapSel);
707 ((struct dio_private *)(dev->subdevices + 2 +
708 group)->private)->WRCapSel,
714 static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
717 /* disable edge capture write command */
718 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
720 /* enable edge capture on selected channel */
722 ((struct dio_private *)(dev->subdevices + 2 +
723 group)->private)->WRCapSel, mask);
728 static int s626_dio_clear_irq(struct comedi_device *dev)
732 /* disable edge capture write command */
733 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
735 for (group = 0; group < S626_DIO_BANKS; group++) {
736 /* clear pending events and interrupt */
738 ((struct dio_private *)(dev->subdevices + 2 +
739 group)->private)->WRCapSel,
746 static irqreturn_t s626_irq_handler(int irq, void *d)
748 struct comedi_device *dev = d;
749 struct s626_private *devpriv = dev->private;
750 struct comedi_subdevice *s;
751 struct comedi_cmd *cmd;
752 struct enc_private *k;
755 uint32_t irqtype, irqstatus;
761 if (dev->attached == 0)
763 /* lock to avoid race with comedi_poll */
764 spin_lock_irqsave(&dev->spinlock, flags);
766 /* save interrupt enable register state */
767 irqstatus = readl(devpriv->base_addr + P_IER);
769 /* read interrupt type */
770 irqtype = readl(devpriv->base_addr + P_ISR);
772 /* disable master interrupt */
773 writel(0, devpriv->base_addr + P_IER);
775 /* clear interrupt */
776 writel(irqtype, devpriv->base_addr + P_ISR);
779 case IRQ_RPS1: /* end_of_scan occurs */
780 /* manage ai subdevice */
782 cmd = &(s->async->cmd);
784 /* Init ptr to DMA buffer that holds new ADC data. We skip the
785 * first uint16_t in the buffer because it contains junk data from
786 * the final ADC of the previous poll list scan.
788 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
790 /* get the data and hand it over to comedi */
791 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
792 /* Convert ADC data to 16-bit integer values and copy to application */
794 tempdata = s626_ai_reg_to_uint((int)*readaddr);
797 /* put data into read buffer */
798 /* comedi_buf_put(s->async, tempdata); */
799 if (cfc_write_to_buffer(s, tempdata) == 0)
801 ("s626_irq_handler: cfc_write_to_buffer error!\n");
804 /* end of scan occurs */
805 s->async->events |= COMEDI_CB_EOS;
807 if (!(devpriv->ai_continous))
808 devpriv->ai_sample_count--;
809 if (devpriv->ai_sample_count <= 0) {
810 devpriv->ai_cmd_running = 0;
812 /* Stop RPS program. */
813 MC_DISABLE(P_MC1, MC1_ERPS1);
815 /* send end of acquisition */
816 s->async->events |= COMEDI_CB_EOA;
818 /* disable master interrupt */
822 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
823 s626_dio_set_irq(dev, cmd->scan_begin_arg);
824 /* tell comedi that data is there */
825 comedi_event(dev, s);
827 case IRQ_GPIO3: /* check dio and conter interrupt */
828 /* manage ai subdevice */
830 cmd = &(s->async->cmd);
832 /* s626_dio_clear_irq(dev); */
834 for (group = 0; group < S626_DIO_BANKS; group++) {
836 /* read interrupt type */
837 irqbit = DEBIread(dev,
838 ((struct dio_private *)(dev->
844 /* check if interrupt is generated from dio channels */
846 s626_dio_reset_irq(dev, group, irqbit);
847 if (devpriv->ai_cmd_running) {
848 /* check if interrupt is an ai acquisition start trigger */
849 if ((irqbit >> (cmd->start_arg -
851 == 1 && cmd->start_src == TRIG_EXT) {
852 /* Start executing the RPS program. */
853 MC_ENABLE(P_MC1, MC1_ERPS1);
855 if (cmd->scan_begin_src ==
857 s626_dio_set_irq(dev,
858 cmd->scan_begin_arg);
861 if ((irqbit >> (cmd->scan_begin_arg -
864 && cmd->scan_begin_src ==
866 /* Trigger ADC scan loop start by setting RPS Signal 0. */
867 MC_ENABLE(P_MC2, MC2_ADC_RPS);
869 if (cmd->convert_src ==
871 devpriv->ai_convert_count
874 s626_dio_set_irq(dev,
878 if (cmd->convert_src ==
881 devpriv->ai_convert_count
887 if ((irqbit >> (cmd->convert_arg -
890 && cmd->convert_src == TRIG_EXT) {
891 /* Trigger ADC scan loop start by setting RPS Signal 0. */
892 MC_ENABLE(P_MC2, MC2_ADC_RPS);
894 devpriv->ai_convert_count--;
896 if (devpriv->ai_convert_count >
898 s626_dio_set_irq(dev,
907 /* read interrupt type */
908 irqbit = DEBIread(dev, LP_RDMISC2);
910 /* check interrupt on counters */
911 if (irqbit & IRQ_COINT1A) {
914 /* clear interrupt capture flag */
915 k->ResetCapFlags(dev, k);
917 if (irqbit & IRQ_COINT2A) {
920 /* clear interrupt capture flag */
921 k->ResetCapFlags(dev, k);
923 if (irqbit & IRQ_COINT3A) {
926 /* clear interrupt capture flag */
927 k->ResetCapFlags(dev, k);
929 if (irqbit & IRQ_COINT1B) {
932 /* clear interrupt capture flag */
933 k->ResetCapFlags(dev, k);
935 if (irqbit & IRQ_COINT2B) {
938 /* clear interrupt capture flag */
939 k->ResetCapFlags(dev, k);
941 if (devpriv->ai_convert_count > 0) {
942 devpriv->ai_convert_count--;
943 if (devpriv->ai_convert_count == 0)
944 k->SetEnable(dev, k, CLKENAB_INDEX);
946 if (cmd->convert_src == TRIG_TIMER) {
947 /* Trigger ADC scan loop start by setting RPS Signal 0. */
948 MC_ENABLE(P_MC2, MC2_ADC_RPS);
952 if (irqbit & IRQ_COINT3B) {
955 /* clear interrupt capture flag */
956 k->ResetCapFlags(dev, k);
958 if (cmd->scan_begin_src == TRIG_TIMER) {
959 /* Trigger ADC scan loop start by setting RPS Signal 0. */
960 MC_ENABLE(P_MC2, MC2_ADC_RPS);
963 if (cmd->convert_src == TRIG_TIMER) {
965 devpriv->ai_convert_count = cmd->chanlist_len;
966 k->SetEnable(dev, k, CLKENAB_ALWAYS);
971 /* enable interrupt */
972 writel(irqstatus, devpriv->base_addr + P_IER);
974 spin_unlock_irqrestore(&dev->spinlock, flags);
979 * this functions build the RPS program for hardware driven acquistion
981 static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
983 struct s626_private *devpriv = dev->private;
984 register uint32_t *pRPS;
989 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
991 /* Stop RPS program in case it is currently running. */
992 MC_DISABLE(P_MC1, MC1_ERPS1);
994 /* Set starting logical address to write RPS commands. */
995 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
997 /* Initialize RPS instruction pointer. */
998 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1000 /* Construct RPS program in RPSBuf DMA buffer */
1002 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1003 /* Wait for Start trigger. */
1004 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1005 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1008 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1009 * because the first RPS DEBI Write following a non-RPS DEBI write
1010 * seems to always fail. If we don't do this dummy write, the ADC
1011 * gain might not be set to the value required for the first slot in
1012 * the poll list; the ADC gain would instead remain unchanged from
1013 * the previously programmed value.
1015 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1016 /* Write DEBI Write command and address to shadow RAM. */
1018 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
1019 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1020 /* Write DEBI immediate data to shadow RAM: */
1022 *pRPS++ = GSEL_BIPOLAR5V;
1023 /* arbitrary immediate data value. */
1025 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1026 /* Reset "shadow RAM uploaded" flag. */
1027 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1028 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1030 /* Digitize all slots in the poll list. This is implemented as a
1031 * for loop to limit the slot count to 16 in case the application
1032 * forgot to set the EOPL flag in the final slot.
1034 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
1035 /* Convert application's poll list item to private board class
1036 * format. Each app poll list item is an uint8_t with form
1037 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1038 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1041 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1044 /* Switch ADC analog gain. */
1045 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1046 /* and address to */
1048 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
1049 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1050 /* immediate data to */
1053 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1055 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1056 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1059 /* Select ADC analog input channel. */
1060 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1061 /* Write DEBI command and address to shadow RAM. */
1062 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
1063 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1064 /* Write DEBI immediate data to shadow RAM. */
1066 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1067 /* Reset "shadow RAM uploaded" flag. */
1069 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1070 /* Invoke shadow RAM upload. */
1072 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1073 /* Wait for shadow upload to finish. */
1075 /* Delay at least 10 microseconds for analog input settling.
1076 * Instead of padding with NOPs, we use RPS_JUMP instructions
1077 * here; this allows us to produce a longer delay than is
1078 * possible with NOPs because each RPS_JUMP flushes the RPS'
1079 * instruction prefetch pipeline.
1082 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1083 (uint32_t) ((unsigned long)pRPS -
1084 (unsigned long)devpriv->RPSBuf.LogicalBase);
1085 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
1086 JmpAdrs += 8; /* Repeat to implement time delay: */
1087 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
1091 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1092 /* Wait for Start trigger. */
1093 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1094 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1096 /* Start ADC by pulsing GPIO1. */
1097 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1098 *pRPS++ = GPIO_BASE | GPIO1_LO;
1100 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1101 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1102 *pRPS++ = GPIO_BASE | GPIO1_HI;
1104 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1105 * busy) and for data from previous conversion to shift into FB
1106 * BUFFER 1 register.
1108 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1110 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1111 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1113 (uint32_t) devpriv->ANABuf.PhysicalBase +
1114 (devpriv->AdcItems << 2);
1116 /* If this slot's EndOfPollList flag is set, all channels have */
1117 /* now been processed. */
1118 if (*ppl++ & EOPL) {
1119 devpriv->AdcItems++; /* Adjust poll list item count. */
1120 break; /* Exit poll list processing loop. */
1124 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1125 * ADC to stabilize for 2 microseconds before starting the final
1126 * (dummy) conversion. This delay is necessary to allow sufficient
1127 * time between last conversion finished and the start of the dummy
1128 * conversion. Without this delay, the last conversion's data value
1129 * is sometimes set to the previous conversion's data value.
1131 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1134 /* Start a dummy conversion to cause the data from the last
1135 * conversion of interest to be shifted in.
1137 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
1138 *pRPS++ = GPIO_BASE | GPIO1_LO;
1140 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1141 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
1142 *pRPS++ = GPIO_BASE | GPIO1_HI;
1144 /* Wait for the data from the last conversion of interest to arrive
1145 * in FB BUFFER 1 register.
1147 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
1149 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1150 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
1152 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
1154 /* Indicate ADC scan loop is finished. */
1155 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
1157 /* invoke interrupt */
1158 if (devpriv->ai_cmd_running == 1) {
1161 /* Restart RPS program at its beginning. */
1162 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
1163 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1165 /* End of RPS program build */
1168 /* TO COMPLETE, IF NECESSARY */
1169 static int s626_ai_insn_config(struct comedi_device *dev,
1170 struct comedi_subdevice *s,
1171 struct comedi_insn *insn, unsigned int *data)
1177 /* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) */
1179 /* struct s626_private *devpriv = dev->private; */
1180 /* register uint8_t i; */
1181 /* register int32_t *readaddr; */
1183 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1184 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1186 /* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
1187 /* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1189 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1190 * first uint16_t in the buffer because it contains junk data from
1191 * the final ADC of the previous poll list scan.
1193 /* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1195 /* Convert ADC data to 16-bit integer values and copy to application buffer. */
1196 /* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1197 /* *data = s626_ai_reg_to_uint( *readaddr++ ); */
1204 static int s626_ai_insn_read(struct comedi_device *dev,
1205 struct comedi_subdevice *s,
1206 struct comedi_insn *insn, unsigned int *data)
1208 struct s626_private *devpriv = dev->private;
1209 uint16_t chan = CR_CHAN(insn->chanspec);
1210 uint16_t range = CR_RANGE(insn->chanspec);
1211 uint16_t AdcSpec = 0;
1215 /* interrupt call test */
1216 /* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1217 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1218 * corresponding interrupt to be generated if enabled
1221 /* Convert application's ADC specification into form
1222 * appropriate for register programming.
1225 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1227 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1229 /* Switch ADC analog gain. */
1230 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
1232 /* Select ADC analog input channel. */
1233 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
1235 for (n = 0; n < insn->n; n++) {
1237 /* Delay 10 microseconds for analog input settling. */
1240 /* Start ADC by pulsing GPIO1 low. */
1241 GpioImage = RR7146(P_GPIO);
1242 /* Assert ADC Start command */
1243 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1244 /* and stretch it out. */
1245 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1246 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1247 /* Negate ADC Start command. */
1248 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1250 /* Wait for ADC to complete (GPIO2 is asserted high when */
1251 /* ADC not busy) and for data from previous conversion to */
1252 /* shift into FB BUFFER 1 register. */
1254 /* Wait for ADC done. */
1255 while (!(RR7146(P_PSR) & PSR_GPIO2))
1258 /* Fetch ADC data. */
1260 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1262 /* Allow the ADC to stabilize for 4 microseconds before
1263 * starting the next (final) conversion. This delay is
1264 * necessary to allow sufficient time between last
1265 * conversion finished and the start of the next
1266 * conversion. Without this delay, the last conversion's
1267 * data value is sometimes set to the previous
1268 * conversion's data value.
1273 /* Start a dummy conversion to cause the data from the
1274 * previous conversion to be shifted in. */
1275 GpioImage = RR7146(P_GPIO);
1277 /* Assert ADC Start command */
1278 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1279 /* and stretch it out. */
1280 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1281 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1282 /* Negate ADC Start command. */
1283 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1285 /* Wait for the data to arrive in FB BUFFER 1 register. */
1287 /* Wait for ADC done. */
1288 while (!(RR7146(P_PSR) & PSR_GPIO2))
1291 /* Fetch ADC data from audio interface's input shift register. */
1293 /* Fetch ADC data. */
1295 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1300 static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1305 for (n = 0; n < cmd->chanlist_len; n++) {
1306 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1307 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1309 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1317 static int s626_ai_inttrig(struct comedi_device *dev,
1318 struct comedi_subdevice *s, unsigned int trignum)
1320 struct s626_private *devpriv = dev->private;
1325 /* Start executing the RPS program. */
1326 MC_ENABLE(P_MC1, MC1_ERPS1);
1328 s->async->inttrig = NULL;
1333 /* This function doesn't require a particular form, this is just what
1334 * happens to be used in some of the drivers. It should convert ns
1335 * nanoseconds to a counter value suitable for programming the device.
1336 * Also, it should adjust ns so that it cooresponds to the actual time
1337 * that the device will use. */
1338 static int s626_ns_to_timer(int *nanosec, int round_mode)
1342 base = 500; /* 2MHz internal clock */
1344 switch (round_mode) {
1345 case TRIG_ROUND_NEAREST:
1347 divider = (*nanosec + base / 2) / base;
1349 case TRIG_ROUND_DOWN:
1350 divider = (*nanosec) / base;
1353 divider = (*nanosec + base - 1) / base;
1357 *nanosec = base * divider;
1361 static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
1364 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1366 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1367 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
1368 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1369 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
1370 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1371 (CLKENAB_INDEX << BF_CLKENAB);
1372 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
1373 /* uint16_t enab=CLKENAB_ALWAYS; */
1375 k->SetMode(dev, k, Setup, FALSE);
1377 /* Set the preload register */
1378 Preload(dev, k, tick);
1380 /* Software index pulse forces the preload register to load */
1381 /* into the counter */
1382 k->SetLoadTrig(dev, k, 0);
1383 k->PulseIndex(dev, k);
1385 /* set reload on counter overflow */
1386 k->SetLoadTrig(dev, k, 1);
1388 /* set interrupt on overflow */
1389 k->SetIntSrc(dev, k, INTSRC_OVER);
1391 SetLatchSource(dev, k, valueSrclatch);
1392 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
1396 static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1398 struct s626_private *devpriv = dev->private;
1400 struct comedi_cmd *cmd = &s->async->cmd;
1401 struct enc_private *k;
1404 if (devpriv->ai_cmd_running) {
1405 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
1409 /* disable interrupt */
1410 writel(0, devpriv->base_addr + P_IER);
1412 /* clear interrupt request */
1413 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1415 /* clear any pending interrupt */
1416 s626_dio_clear_irq(dev);
1417 /* s626_enc_clear_irq(dev); */
1419 /* reset ai_cmd_running flag */
1420 devpriv->ai_cmd_running = 0;
1422 /* test if cmd is valid */
1426 if (dev->irq == 0) {
1428 "s626_ai_cmd: cannot run command without an irq");
1432 s626_ai_load_polllist(ppl, cmd);
1433 devpriv->ai_cmd_running = 1;
1434 devpriv->ai_convert_count = 0;
1436 switch (cmd->scan_begin_src) {
1440 /* set a conter to generate adc trigger at scan_begin_arg interval */
1442 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1443 cmd->flags & TRIG_ROUND_MASK);
1445 /* load timer value and enable interrupt */
1446 s626_timer_load(dev, k, tick);
1447 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1450 /* set the digital line and interrupt for scan trigger */
1451 if (cmd->start_src != TRIG_EXT)
1452 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1456 switch (cmd->convert_src) {
1460 /* set a conter to generate adc trigger at convert_arg interval */
1462 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1463 cmd->flags & TRIG_ROUND_MASK);
1465 /* load timer value and enable interrupt */
1466 s626_timer_load(dev, k, tick);
1467 k->SetEnable(dev, k, CLKENAB_INDEX);
1470 /* set the digital line and interrupt for convert trigger */
1471 if (cmd->scan_begin_src != TRIG_EXT
1472 && cmd->start_src == TRIG_EXT)
1473 s626_dio_set_irq(dev, cmd->convert_arg);
1477 switch (cmd->stop_src) {
1479 /* data arrives as one packet */
1480 devpriv->ai_sample_count = cmd->stop_arg;
1481 devpriv->ai_continous = 0;
1484 /* continous acquisition */
1485 devpriv->ai_continous = 1;
1486 devpriv->ai_sample_count = 0;
1492 switch (cmd->start_src) {
1494 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1495 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1497 /* Start executing the RPS program. */
1498 MC_ENABLE(P_MC1, MC1_ERPS1);
1500 s->async->inttrig = NULL;
1503 /* configure DIO channel for acquisition trigger */
1504 s626_dio_set_irq(dev, cmd->start_arg);
1506 s->async->inttrig = NULL;
1509 s->async->inttrig = s626_ai_inttrig;
1513 /* enable interrupt */
1514 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1519 static int s626_ai_cmdtest(struct comedi_device *dev,
1520 struct comedi_subdevice *s, struct comedi_cmd *cmd)
1525 /* Step 1 : check if triggers are trivially valid */
1527 err |= cfc_check_trigger_src(&cmd->start_src,
1528 TRIG_NOW | TRIG_INT | TRIG_EXT);
1529 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
1530 TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
1531 err |= cfc_check_trigger_src(&cmd->convert_src,
1532 TRIG_TIMER | TRIG_EXT | TRIG_NOW);
1533 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
1534 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
1539 /* Step 2a : make sure trigger sources are unique */
1541 err |= cfc_check_trigger_is_unique(cmd->start_src);
1542 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
1543 err |= cfc_check_trigger_is_unique(cmd->convert_src);
1544 err |= cfc_check_trigger_is_unique(cmd->stop_src);
1546 /* Step 2b : and mutually compatible */
1551 /* step 3: make sure arguments are trivially compatible */
1553 if (cmd->start_src != TRIG_EXT)
1554 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
1555 if (cmd->start_src == TRIG_EXT)
1556 err |= cfc_check_trigger_arg_max(&cmd->start_arg, 39);
1558 if (cmd->scan_begin_src == TRIG_EXT)
1559 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
1561 if (cmd->convert_src == TRIG_EXT)
1562 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 39);
1564 #define MAX_SPEED 200000 /* in nanoseconds */
1565 #define MIN_SPEED 2000000000 /* in nanoseconds */
1567 if (cmd->scan_begin_src == TRIG_TIMER) {
1568 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
1570 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
1573 /* external trigger */
1574 /* should be level/edge, hi/lo specification here */
1575 /* should specify multiple external triggers */
1576 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
1578 if (cmd->convert_src == TRIG_TIMER) {
1579 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, MAX_SPEED);
1580 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, MIN_SPEED);
1582 /* external trigger */
1584 /* err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9); */
1587 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
1589 if (cmd->stop_src == TRIG_COUNT)
1590 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
1591 else /* TRIG_NONE */
1592 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
1597 /* step 4: fix up any arguments */
1599 if (cmd->scan_begin_src == TRIG_TIMER) {
1600 tmp = cmd->scan_begin_arg;
1601 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1602 cmd->flags & TRIG_ROUND_MASK);
1603 if (tmp != cmd->scan_begin_arg)
1606 if (cmd->convert_src == TRIG_TIMER) {
1607 tmp = cmd->convert_arg;
1608 s626_ns_to_timer((int *)&cmd->convert_arg,
1609 cmd->flags & TRIG_ROUND_MASK);
1610 if (tmp != cmd->convert_arg)
1612 if (cmd->scan_begin_src == TRIG_TIMER &&
1613 cmd->scan_begin_arg <
1614 cmd->convert_arg * cmd->scan_end_arg) {
1615 cmd->scan_begin_arg =
1616 cmd->convert_arg * cmd->scan_end_arg;
1627 static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
1629 struct s626_private *devpriv = dev->private;
1631 /* Stop RPS program in case it is currently running. */
1632 MC_DISABLE(P_MC1, MC1_ERPS1);
1634 /* disable master interrupt */
1635 writel(0, devpriv->base_addr + P_IER);
1637 devpriv->ai_cmd_running = 0;
1642 static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1643 struct comedi_insn *insn, unsigned int *data)
1645 struct s626_private *devpriv = dev->private;
1647 uint16_t chan = CR_CHAN(insn->chanspec);
1650 for (i = 0; i < insn->n; i++) {
1651 dacdata = (int16_t) data[i];
1652 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
1653 dacdata -= (0x1fff);
1655 SetDAC(dev, chan, dacdata);
1661 static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1662 struct comedi_insn *insn, unsigned int *data)
1664 struct s626_private *devpriv = dev->private;
1667 for (i = 0; i < insn->n; i++)
1668 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
1673 /* *************** DIGITAL I/O FUNCTIONS ***************
1674 * All DIO functions address a group of DIO channels by means of
1675 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
1676 * ports A, B and C, respectively.
1679 static void s626_dio_init(struct comedi_device *dev)
1682 struct comedi_subdevice *s;
1684 /* Prepare to treat writes to WRCapSel as capture disables. */
1685 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
1687 /* For each group of sixteen channels ... */
1688 for (group = 0; group < S626_DIO_BANKS; group++) {
1689 s = dev->subdevices + 2 + group;
1690 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
1691 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
1693 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
1696 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
1697 /* to inactive state. */
1701 /* DIO devices are slightly special. Although it is possible to
1702 * implement the insn_read/insn_write interface, it is much more
1703 * useful to applications if you implement the insn_bits interface.
1704 * This allows packed reading/writing of the DIO channels. The comedi
1705 * core can convert between insn_bits and insn_read/write */
1707 static int s626_dio_insn_bits(struct comedi_device *dev,
1708 struct comedi_subdevice *s,
1709 struct comedi_insn *insn, unsigned int *data)
1712 * The insn data consists of a mask in data[0] and the new data in
1713 * data[1]. The mask defines which bits we are concerning about.
1714 * The new data must be anded with the mask. Each channel
1715 * corresponds to a bit.
1718 /* Check if requested ports are configured for output */
1719 if ((s->io_bits & data[0]) != data[0])
1722 s->state &= ~data[0];
1723 s->state |= data[0] & data[1];
1725 /* Write out the new digital output lines */
1727 DEBIwrite(dev, diopriv->WRDOut, s->state);
1729 data[1] = DEBIread(dev, diopriv->RDDIn);
1734 static int s626_dio_insn_config(struct comedi_device *dev,
1735 struct comedi_subdevice *s,
1736 struct comedi_insn *insn, unsigned int *data)
1740 case INSN_CONFIG_DIO_QUERY:
1743 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
1748 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
1751 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
1757 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
1762 /* Now this function initializes the value of the counter (data[0])
1763 and set the subdevice. To complete with trigger and interrupt
1765 /* FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
1766 * what is being configured, but this function appears to be using data[0]
1768 static int s626_enc_insn_config(struct comedi_device *dev,
1769 struct comedi_subdevice *s,
1770 struct comedi_insn *insn, unsigned int *data)
1772 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
1774 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
1775 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
1776 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
1777 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
1778 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
1779 (CLKENAB_INDEX << BF_CLKENAB);
1780 /* uint16_t DisableIntSrc=TRUE; */
1781 /* uint32_t Preloadvalue; //Counter initial value */
1782 uint16_t valueSrclatch = LATCHSRC_AB_READ;
1783 uint16_t enab = CLKENAB_ALWAYS;
1784 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1786 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
1788 k->SetMode(dev, k, Setup, TRUE);
1789 Preload(dev, k, data[0]);
1790 k->PulseIndex(dev, k);
1791 SetLatchSource(dev, k, valueSrclatch);
1792 k->SetEnable(dev, k, (uint16_t) (enab != 0));
1797 static int s626_enc_insn_read(struct comedi_device *dev,
1798 struct comedi_subdevice *s,
1799 struct comedi_insn *insn, unsigned int *data)
1803 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1805 for (n = 0; n < insn->n; n++)
1806 data[n] = ReadLatch(dev, k);
1811 static int s626_enc_insn_write(struct comedi_device *dev,
1812 struct comedi_subdevice *s,
1813 struct comedi_insn *insn, unsigned int *data)
1816 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
1818 /* Set the preload register */
1819 Preload(dev, k, data[0]);
1821 /* Software index pulse forces the preload register to load */
1822 /* into the counter */
1823 k->SetLoadTrig(dev, k, 0);
1824 k->PulseIndex(dev, k);
1825 k->SetLoadTrig(dev, k, 2);
1830 static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
1832 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
1833 /* MISC2 register. */
1834 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
1835 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
1838 static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
1841 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1847 /* find the matching allocation from the board struct */
1849 vbptr = pdma->LogicalBase;
1850 vpptr = pdma->PhysicalBase;
1852 pci_free_consistent(pcidev, bsize, vbptr, vpptr);
1853 pdma->LogicalBase = NULL;
1854 pdma->PhysicalBase = 0;
1858 /* ****** PRIVATE COUNTER FUNCTIONS ****** */
1860 /* Reset a counter's index and overflow event capture flags. */
1862 static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
1864 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
1865 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
1868 static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
1870 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
1871 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
1874 /* Return counter setup in a format (COUNTER_SETUP) that is consistent */
1875 /* for both A and B counters. */
1877 static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
1879 register uint16_t cra;
1880 register uint16_t crb;
1881 register uint16_t setup;
1883 /* Fetch CRA and CRB register images. */
1884 cra = DEBIread(dev, k->MyCRA);
1885 crb = DEBIread(dev, k->MyCRB);
1887 /* Populate the standardized counter setup bit fields. Note: */
1888 /* IndexSrc is restricted to ENC_X or IndxPol. */
1889 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
1890 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
1891 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
1892 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
1893 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
1894 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
1896 /* Adjust mode-dependent parameters. */
1897 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
1898 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1899 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
1900 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
1902 else /* If Counter mode (ClkSrcA<1> == 0): */
1903 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
1904 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
1905 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
1906 (MULT_X1 << STDBIT_CLKMULT) :
1907 ((cra >> (CRABIT_CLKMULT_A -
1908 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
1910 /* Return adjusted counter setup. */
1914 static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
1916 register uint16_t cra;
1917 register uint16_t crb;
1918 register uint16_t setup;
1920 /* Fetch CRA and CRB register images. */
1921 cra = DEBIread(dev, k->MyCRA);
1922 crb = DEBIread(dev, k->MyCRB);
1924 /* Populate the standardized counter setup bit fields. Note: */
1925 /* IndexSrc is restricted to ENC_X or IndxPol. */
1926 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
1927 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
1928 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
1929 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
1930 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
1931 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
1933 /* Adjust mode-dependent parameters. */
1934 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
1935 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
1936 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1937 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
1939 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
1940 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1941 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
1942 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
1944 else /* If Counter mode (ClkSrcB<1> == 0): */
1945 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
1946 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
1947 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
1949 /* Return adjusted counter setup. */
1954 * Set the operating mode for the specified counter. The setup
1955 * parameter is treated as a COUNTER_SETUP data type. The following
1956 * parameters are programmable (all other parms are ignored): ClkMult,
1957 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
1960 static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
1961 uint16_t Setup, uint16_t DisableIntSrc)
1963 struct s626_private *devpriv = dev->private;
1964 register uint16_t cra;
1965 register uint16_t crb;
1966 register uint16_t setup = Setup; /* Cache the Standard Setup. */
1968 /* Initialize CRA and CRB images. */
1969 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
1970 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
1972 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
1973 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
1975 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
1977 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
1980 /* Populate all mode-dependent attributes of CRA & CRB images. */
1981 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
1982 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
1983 /* (Extender valid only for B counters). */
1985 case CLKSRC_TIMER: /* Timer Mode: */
1986 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
1987 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
1988 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
1989 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
1992 default: /* Counter Mode: */
1993 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
1994 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
1995 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
1996 (MULT_X1 << CRABIT_CLKMULT_A) :
1997 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
2001 /* Force positive index polarity if IndxSrc is software-driven only, */
2002 /* otherwise pass it through. */
2003 if (~setup & STDMSK_INDXSRC)
2004 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
2007 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2008 /* enable mask to indicate the counter interrupt is disabled. */
2010 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2012 /* While retaining CounterB and LatchSrc configurations, program the */
2013 /* new counter operating mode. */
2014 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
2015 DEBIreplace(dev, k->MyCRB,
2016 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
2019 static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
2020 uint16_t Setup, uint16_t DisableIntSrc)
2022 struct s626_private *devpriv = dev->private;
2023 register uint16_t cra;
2024 register uint16_t crb;
2025 register uint16_t setup = Setup; /* Cache the Standard Setup. */
2027 /* Initialize CRA and CRB images. */
2028 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
2030 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
2031 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
2032 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
2034 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
2036 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2039 /* Populate all mode-dependent attributes of CRA & CRB images. */
2040 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
2041 case CLKSRC_TIMER: /* Timer Mode: */
2042 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
2043 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
2044 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
2045 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
2048 case CLKSRC_EXTENDER: /* Extender Mode: */
2049 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
2050 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
2051 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
2052 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
2055 default: /* Counter Mode: */
2056 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
2057 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
2058 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
2059 (MULT_X1 << CRBBIT_CLKMULT_B) :
2060 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
2064 /* Force positive index polarity if IndxSrc is software-driven only, */
2065 /* otherwise pass it through. */
2066 if (~setup & STDMSK_INDXSRC)
2067 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
2070 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2071 /* enable mask to indicate the counter interrupt is disabled. */
2073 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2075 /* While retaining CounterA and LatchSrc configurations, program the */
2076 /* new counter operating mode. */
2077 DEBIreplace(dev, k->MyCRA,
2078 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
2079 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
2082 /* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
2084 static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
2087 DEBIreplace(dev, k->MyCRB,
2088 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
2089 (uint16_t) (enab << CRBBIT_CLKENAB_A));
2092 static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
2095 DEBIreplace(dev, k->MyCRB,
2096 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
2097 (uint16_t) (enab << CRBBIT_CLKENAB_B));
2100 static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
2102 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
2105 static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
2107 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
2111 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
2113 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
2118 * Return/set the event that will trigger transfer of the preload
2119 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
2120 * 2=OverflowA (B counters only), 3=disabled.
2123 static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
2126 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
2127 (uint16_t) (Trig << CRABIT_LOADSRC_A));
2130 static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
2133 DEBIreplace(dev, k->MyCRB,
2134 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
2135 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
2138 static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
2140 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
2143 static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
2145 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
2148 /* Return/set counter interrupt source and clear any captured
2149 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
2150 * 2=IndexOnly, 3=IndexAndOverflow.
2153 static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
2156 struct s626_private *devpriv = dev->private;
2158 /* Reset any pending counter overflow or index captures. */
2159 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2160 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
2162 /* Program counter interrupt source. */
2163 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
2164 (uint16_t) (IntSource << CRABIT_INTSRC_A));
2166 /* Update MISC2 interrupt enable mask. */
2167 devpriv->CounterIntEnabs =
2168 (devpriv->CounterIntEnabs & ~k->
2169 MyEventBits[3]) | k->MyEventBits[IntSource];
2172 static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
2175 struct s626_private *devpriv = dev->private;
2178 /* Cache writeable CRB register image. */
2179 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
2181 /* Reset any pending counter overflow or index captures. */
2182 DEBIwrite(dev, k->MyCRB,
2183 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
2185 /* Program counter interrupt source. */
2186 DEBIwrite(dev, k->MyCRB,
2187 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
2190 /* Update MISC2 interrupt enable mask. */
2191 devpriv->CounterIntEnabs =
2192 (devpriv->CounterIntEnabs & ~k->
2193 MyEventBits[3]) | k->MyEventBits[IntSource];
2196 static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
2198 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
2201 static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
2203 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
2206 /* Return/set the clock multiplier. */
2208 /* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2210 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
2213 /* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
2215 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
2218 /* Return/set the clock polarity. */
2220 /* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2222 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
2225 /* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
2227 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
2230 /* Return/set the clock source. */
2232 /* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
2234 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
2237 /* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
2239 /* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
2242 /* Return/set the index polarity. */
2244 /* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2246 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
2249 /* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
2251 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
2254 /* Return/set the index source. */
2256 /* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
2258 /* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
2261 /* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
2263 /* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
2266 /* Generate an index pulse. */
2268 static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
2270 register uint16_t cra;
2272 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
2273 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
2274 DEBIwrite(dev, k->MyCRA, cra);
2277 static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
2279 register uint16_t crb;
2281 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
2282 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
2283 DEBIwrite(dev, k->MyCRB, crb);
2286 static struct enc_private enc_private_data[] = {
2288 .GetEnable = GetEnable_A,
2289 .GetIntSrc = GetIntSrc_A,
2290 .GetLoadTrig = GetLoadTrig_A,
2291 .GetMode = GetMode_A,
2292 .PulseIndex = PulseIndex_A,
2293 .SetEnable = SetEnable_A,
2294 .SetIntSrc = SetIntSrc_A,
2295 .SetLoadTrig = SetLoadTrig_A,
2296 .SetMode = SetMode_A,
2297 .ResetCapFlags = ResetCapFlags_A,
2300 .MyLatchLsw = LP_CNTR0ALSW,
2301 .MyEventBits = EVBITS(0),
2303 .GetEnable = GetEnable_A,
2304 .GetIntSrc = GetIntSrc_A,
2305 .GetLoadTrig = GetLoadTrig_A,
2306 .GetMode = GetMode_A,
2307 .PulseIndex = PulseIndex_A,
2308 .SetEnable = SetEnable_A,
2309 .SetIntSrc = SetIntSrc_A,
2310 .SetLoadTrig = SetLoadTrig_A,
2311 .SetMode = SetMode_A,
2312 .ResetCapFlags = ResetCapFlags_A,
2315 .MyLatchLsw = LP_CNTR1ALSW,
2316 .MyEventBits = EVBITS(1),
2318 .GetEnable = GetEnable_A,
2319 .GetIntSrc = GetIntSrc_A,
2320 .GetLoadTrig = GetLoadTrig_A,
2321 .GetMode = GetMode_A,
2322 .PulseIndex = PulseIndex_A,
2323 .SetEnable = SetEnable_A,
2324 .SetIntSrc = SetIntSrc_A,
2325 .SetLoadTrig = SetLoadTrig_A,
2326 .SetMode = SetMode_A,
2327 .ResetCapFlags = ResetCapFlags_A,
2330 .MyLatchLsw = LP_CNTR2ALSW,
2331 .MyEventBits = EVBITS(2),
2333 .GetEnable = GetEnable_B,
2334 .GetIntSrc = GetIntSrc_B,
2335 .GetLoadTrig = GetLoadTrig_B,
2336 .GetMode = GetMode_B,
2337 .PulseIndex = PulseIndex_B,
2338 .SetEnable = SetEnable_B,
2339 .SetIntSrc = SetIntSrc_B,
2340 .SetLoadTrig = SetLoadTrig_B,
2341 .SetMode = SetMode_B,
2342 .ResetCapFlags = ResetCapFlags_B,
2345 .MyLatchLsw = LP_CNTR0BLSW,
2346 .MyEventBits = EVBITS(3),
2348 .GetEnable = GetEnable_B,
2349 .GetIntSrc = GetIntSrc_B,
2350 .GetLoadTrig = GetLoadTrig_B,
2351 .GetMode = GetMode_B,
2352 .PulseIndex = PulseIndex_B,
2353 .SetEnable = SetEnable_B,
2354 .SetIntSrc = SetIntSrc_B,
2355 .SetLoadTrig = SetLoadTrig_B,
2356 .SetMode = SetMode_B,
2357 .ResetCapFlags = ResetCapFlags_B,
2360 .MyLatchLsw = LP_CNTR1BLSW,
2361 .MyEventBits = EVBITS(4),
2363 .GetEnable = GetEnable_B,
2364 .GetIntSrc = GetIntSrc_B,
2365 .GetLoadTrig = GetLoadTrig_B,
2366 .GetMode = GetMode_B,
2367 .PulseIndex = PulseIndex_B,
2368 .SetEnable = SetEnable_B,
2369 .SetIntSrc = SetIntSrc_B,
2370 .SetLoadTrig = SetLoadTrig_B,
2371 .SetMode = SetMode_B,
2372 .ResetCapFlags = ResetCapFlags_B,
2375 .MyLatchLsw = LP_CNTR2BLSW,
2376 .MyEventBits = EVBITS(5),
2380 static void CountersInit(struct comedi_device *dev)
2383 struct enc_private *k;
2384 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2386 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2387 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
2388 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2389 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
2390 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2391 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
2393 /* Disable all counter interrupts and clear any captured counter events. */
2394 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2396 k->SetMode(dev, k, Setup, TRUE);
2397 k->SetIntSrc(dev, k, 0);
2398 k->ResetCapFlags(dev, k);
2399 k->SetEnable(dev, k, CLKENAB_ALWAYS);
2403 static int s626_allocate_dma_buffers(struct comedi_device *dev)
2405 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2406 struct s626_private *devpriv = dev->private;
2410 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2413 devpriv->ANABuf.LogicalBase = addr;
2414 devpriv->ANABuf.PhysicalBase = appdma;
2416 addr = pci_alloc_consistent(pcidev, DMABUF_SIZE, &appdma);
2419 devpriv->RPSBuf.LogicalBase = addr;
2420 devpriv->RPSBuf.PhysicalBase = appdma;
2425 static void s626_initialize(struct comedi_device *dev)
2427 struct s626_private *devpriv = dev->private;
2428 dma_addr_t pPhysBuf;
2432 /* Enable DEBI and audio pins, enable I2C interface */
2433 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
2436 * Configure DEBI operating mode
2438 * Local bus is 16 bits wide
2439 * Declare DEBI transfer timeout interval
2440 * Set up byte lane steering
2441 * Intel-compatible local bus (DEBI never times out)
2443 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 |
2444 (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
2445 DEBI_SWAP | DEBI_CFG_INTEL);
2447 /* Disable MMU paging */
2448 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);
2450 /* Init GPIO so that ADC Start* is negated */
2451 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
2453 /* I2C device address for onboard eeprom (revb) */
2454 devpriv->I2CAdrs = 0xA0;
2457 * Issue an I2C ABORT command to halt any I2C
2458 * operation in progress and reset BUSY flag.
2460 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
2461 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
2462 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
2466 * Per SAA7146 data sheet, write to STATUS
2467 * reg twice to reset all I2C error flags.
2469 for (i = 0; i < 2; i++) {
2470 WR7146(P_I2CSTAT, I2C_CLKSEL);
2471 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
2472 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2477 * Init audio interface functional attributes: set DAC/ADC
2478 * serial clock rates, invert DAC serial clock so that
2479 * DAC data setup times are satisfied, enable DAC serial
2482 WR7146(P_ACON2, ACON2_INIT);
2485 * Set up TSL1 slot list, which is used to control the
2486 * accumulation of ADC data: RSD1 = shift data in on SD1.
2487 * SIB_A1 = store data uint8_t at next available location
2488 * in FB BUFFER1 register.
2490 WR7146(P_TSL1, RSD1 | SIB_A1);
2491 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
2493 /* Enable TSL1 slot list so that it executes all the time */
2494 WR7146(P_ACON1, ACON1_ADCSTART);
2497 * Initialize RPS registers used for ADC
2500 /* Physical start of RPS program */
2501 WR7146(P_RPSADDR1, (uint32_t)devpriv->RPSBuf.PhysicalBase);
2502 /* RPS program performs no explicit mem writes */
2503 WR7146(P_RPSPAGE1, 0);
2504 /* Disable RPS timeouts */
2505 WR7146(P_RPS1_TOUT, 0);
2509 * SAA7146 BUG WORKAROUND
2511 * Initialize SAA7146 ADC interface to a known state by
2512 * invoking ADCs until FB BUFFER 1 register shows that it
2513 * is correctly receiving ADC data. This is necessary
2514 * because the SAA7146 ADC interface does not start up in
2515 * a defined state after a PCI reset.
2523 unsigned int data[16];
2525 /* Create a simple polling list for analog input channel 0 */
2527 ResetADC(dev, &PollList);
2529 /* Get initial ADC value */
2530 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2534 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION.
2536 * Invoke ADCs until the new ADC value differs from the initial
2537 * value or a timeout occurs. The timeout protects against the
2538 * possibility that the driver is restarting and the ADC data is a
2539 * fixed value resulting from the applied ADC analog input being
2540 * unusually quiet or at the rail.
2542 for (index = 0; index < 500; index++) {
2543 s626_ai_rinsn(dev, dev->subdevices, NULL, data);
2545 if (AdcData != StartVal)
2550 #endif /* SAA7146 BUG WORKAROUND */
2553 * Initialize the DAC interface
2557 * Init Audio2's output DMAC attributes:
2558 * burst length = 1 DWORD
2559 * threshold = 1 DWORD.
2561 WR7146(P_PCI_BT_A, 0);
2564 * Init Audio2's output DMA physical addresses. The protection
2565 * address is set to 1 DWORD past the base address so that a
2566 * single DWORD will be transferred each time a DMA transfer is
2569 pPhysBuf = devpriv->ANABuf.PhysicalBase +
2570 (DAC_WDMABUF_OS * sizeof(uint32_t));
2571 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);
2572 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t)));
2575 * Cache Audio2's output DMA buffer logical address. This is
2576 * where DAC data is buffered for A2 output DMA transfers.
2578 devpriv->pDacWBuf = (uint32_t *)devpriv->ANABuf.LogicalBase +
2582 * Audio2's output channels does not use paging. The
2583 * protection violation handling bit is set so that the
2584 * DMAC will automatically halt and its PCI address pointer
2585 * will be reset when the protection address is reached.
2587 WR7146(P_PAGEA2_OUT, 8);
2590 * Initialize time slot list 2 (TSL2), which is used to control
2591 * the clock generation for and serialization of data to be sent
2592 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
2593 * execution; this permits other slots to be safely modified
2594 * without first turning off the TSL sequencer (which is
2595 * apparently impossible to do). Also, SD3 (which is driven by a
2596 * pull-up resistor) is shifted in and stored to the MSB of
2597 * FB_BUFFER2 to be used as evidence that the slot sequence has
2598 * not yet finished executing.
2601 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2602 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
2605 * Initialize slot 1, which is constant. Slot 1 causes a
2606 * DWORD to be transferred from audio channel 2's output FIFO
2607 * to the FIFO's output buffer so that it can be serialized
2608 * and sent to the DAC during subsequent slots. All remaining
2609 * slots are dynamically populated as required by the target
2613 /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2616 /* Start DAC's audio interface (TSL2) running */
2617 WR7146(P_ACON1, ACON1_DACSTART);
2620 * Init Trim DACs to calibrated values. Do it twice because the
2621 * SAA7146 audio channel does not always reset properly and
2622 * sometimes causes the first few TrimDAC writes to malfunction.
2628 * Manually init all gate array hardware in case this is a soft
2629 * reset (we have no way of determining whether this is a warm
2630 * or cold start). This is necessary because the gate array will
2631 * reset only in response to a PCI hard reset; there is no soft
2636 * Init all DAC outputs to 0V and init all DAC setpoint and
2639 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
2640 SetDAC(dev, chan, 0);
2646 * Without modifying the state of the Battery Backup enab, disable
2647 * the watchdog timer, set DIO channels 0-5 to operate in the
2648 * standard DIO (vs. counter overflow) mode, disable the battery
2649 * charger, and reset the watchdog interval selector to zero.
2651 WriteMISC2(dev, (uint16_t)(DEBIread(dev, LP_RDMISC2) &
2652 MISC2_BATT_ENABLE));
2654 /* Initialize the digital I/O subsystem */
2657 /* enable interrupt test */
2658 /* writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER); */
2661 static int s626_auto_attach(struct comedi_device *dev,
2662 unsigned long context_unused)
2664 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2665 struct s626_private *devpriv;
2666 struct comedi_subdevice *s;
2669 dev->board_name = dev->driver->driver_name;
2671 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
2674 dev->private = devpriv;
2676 ret = comedi_pci_enable(pcidev, dev->board_name);
2679 dev->iobase = 1; /* detach needs this */
2681 devpriv->base_addr = ioremap(pci_resource_start(pcidev, 0),
2682 pci_resource_len(pcidev, 0));
2683 if (!devpriv->base_addr)
2686 /* disable master interrupt */
2687 writel(0, devpriv->base_addr + P_IER);
2690 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
2692 /* DMA FIXME DMA// */
2694 ret = s626_allocate_dma_buffers(dev);
2699 ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2700 dev->board_name, dev);
2703 dev->irq = pcidev->irq;
2706 ret = comedi_alloc_subdevices(dev, 6);
2710 s = dev->subdevices + 0;
2711 /* analog input subdevice */
2712 dev->read_subdev = s;
2713 /* we support single-ended (ground) and differential */
2714 s->type = COMEDI_SUBD_AI;
2715 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
2716 s->n_chan = S626_ADC_CHANNELS;
2717 s->maxdata = (0xffff >> 2);
2718 s->range_table = &s626_range_table;
2719 s->len_chanlist = S626_ADC_CHANNELS;
2720 s->insn_config = s626_ai_insn_config;
2721 s->insn_read = s626_ai_insn_read;
2722 s->do_cmd = s626_ai_cmd;
2723 s->do_cmdtest = s626_ai_cmdtest;
2724 s->cancel = s626_ai_cancel;
2726 s = dev->subdevices + 1;
2727 /* analog output subdevice */
2728 s->type = COMEDI_SUBD_AO;
2729 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2730 s->n_chan = S626_DAC_CHANNELS;
2731 s->maxdata = (0x3fff);
2732 s->range_table = &range_bipolar10;
2733 s->insn_write = s626_ao_winsn;
2734 s->insn_read = s626_ao_rinsn;
2736 s = dev->subdevices + 2;
2737 /* digital I/O subdevice */
2738 s->type = COMEDI_SUBD_DIO;
2739 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2742 s->io_bits = 0xffff;
2743 s->private = &dio_private_A;
2744 s->range_table = &range_digital;
2745 s->insn_config = s626_dio_insn_config;
2746 s->insn_bits = s626_dio_insn_bits;
2748 s = dev->subdevices + 3;
2749 /* digital I/O subdevice */
2750 s->type = COMEDI_SUBD_DIO;
2751 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2754 s->io_bits = 0xffff;
2755 s->private = &dio_private_B;
2756 s->range_table = &range_digital;
2757 s->insn_config = s626_dio_insn_config;
2758 s->insn_bits = s626_dio_insn_bits;
2760 s = dev->subdevices + 4;
2761 /* digital I/O subdevice */
2762 s->type = COMEDI_SUBD_DIO;
2763 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2766 s->io_bits = 0xffff;
2767 s->private = &dio_private_C;
2768 s->range_table = &range_digital;
2769 s->insn_config = s626_dio_insn_config;
2770 s->insn_bits = s626_dio_insn_bits;
2772 s = dev->subdevices + 5;
2773 /* encoder (counter) subdevice */
2774 s->type = COMEDI_SUBD_COUNTER;
2775 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2776 s->n_chan = S626_ENCODER_CHANNELS;
2777 s->private = enc_private_data;
2778 s->insn_config = s626_enc_insn_config;
2779 s->insn_read = s626_enc_insn_read;
2780 s->insn_write = s626_enc_insn_write;
2781 s->maxdata = 0xffffff;
2782 s->range_table = &range_unknown;
2784 s626_initialize(dev);
2786 dev_info(dev->class_dev, "%s attached\n", dev->board_name);
2791 static void s626_detach(struct comedi_device *dev)
2793 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2794 struct s626_private *devpriv = dev->private;
2797 /* stop ai_command */
2798 devpriv->ai_cmd_running = 0;
2800 if (devpriv->base_addr) {
2801 /* interrupt mask */
2802 WR7146(P_IER, 0); /* Disable master interrupt. */
2803 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
2805 /* Disable the watchdog timer and battery charger. */
2808 /* Close all interfaces on 7146 device. */
2809 WR7146(P_MC1, MC1_SHUTDOWN);
2810 WR7146(P_ACON1, ACON1_BASE);
2812 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
2813 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
2817 free_irq(dev->irq, dev);
2818 if (devpriv->base_addr)
2819 iounmap(devpriv->base_addr);
2823 comedi_pci_disable(pcidev);
2827 static struct comedi_driver s626_driver = {
2828 .driver_name = "s626",
2829 .module = THIS_MODULE,
2830 .auto_attach = s626_auto_attach,
2831 .detach = s626_detach,
2834 static int s626_pci_probe(struct pci_dev *dev,
2835 const struct pci_device_id *ent)
2837 return comedi_pci_auto_config(dev, &s626_driver);
2841 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2842 * also subvendor:subdevice ids, because otherwise it will conflict with
2843 * Philips SAA7146 media/dvb based cards.
2845 static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
2846 { PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
2847 PCI_SUBVENDOR_ID_S626, PCI_SUBDEVICE_ID_S626, 0, 0, 0 },
2850 MODULE_DEVICE_TABLE(pci, s626_pci_table);
2852 static struct pci_driver s626_pci_driver = {
2854 .id_table = s626_pci_table,
2855 .probe = s626_pci_probe,
2856 .remove = comedi_pci_auto_unconfig,
2858 module_comedi_pci_driver(s626_driver, s626_pci_driver);
2860 MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2861 MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2862 MODULE_LICENSE("GPL");