2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream-ch2.h"
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <linux/slab.h>
35 #include <asm/uaccess.h>
37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
39 MODULE_LICENSE("GPL");
41 static int _intr_msk =
42 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
44 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
45 __le32 * rp, unsigned int offset,
46 unsigned int bpl, u32 sync_line,
48 int fifo_enable, int field_type)
51 int dist_betwn_starts = bpl * 2;
53 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
55 if (USE_RISC_NOOP_VIDEO) {
56 for (i = 0; i < NUM_NO_OPS; i++) {
57 *(rp++) = cpu_to_le32(RISC_NOOP);
62 for (line = 0; line < lines; line++) {
63 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
64 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
65 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
67 if ((lines <= NTSC_FIELD_HEIGHT)
68 || (line < (NTSC_FIELD_HEIGHT - 1))
69 || !(dev->_isNTSC_ch2)) {
70 offset += dist_betwn_starts;
77 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
79 dma_addr_t databuf_phys_addr,
81 u32 sync_line, unsigned int bpl,
83 int fifo_enable, int field_type)
86 struct sram_channel *sram_ch =
87 &dev->sram_channels[dev->_channel2_upstream_select];
88 int dist_betwn_starts = bpl * 2;
90 /* sync instruction */
91 if (sync_line != NO_SYNC_LINE) {
92 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
95 if (USE_RISC_NOOP_VIDEO) {
96 for (i = 0; i < NUM_NO_OPS; i++) {
97 *(rp++) = cpu_to_le32(RISC_NOOP);
102 for (line = 0; line < lines; line++) {
103 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
104 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
105 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
107 if ((lines <= NTSC_FIELD_HEIGHT)
108 || (line < (NTSC_FIELD_HEIGHT - 1))
109 || !(dev->_isNTSC_ch2)) {
110 offset += dist_betwn_starts;
113 // check if we need to enable the FIFO after the first 4 lines
114 // For the upstream video channel, the risc engine will enable the FIFO.
115 if (fifo_enable && line == 3) {
116 *(rp++) = RISC_WRITECR;
117 *(rp++) = sram_ch->dma_ctl;
118 *(rp++) = FLD_VID_FIFO_EN;
119 *(rp++) = 0x00000001;
126 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
128 unsigned int top_offset, unsigned int bpl,
133 int singlefield_lines = lines >> 1; //get line count for single field
134 int odd_num_lines = singlefield_lines;
137 int databuf_offset = 0;
138 int risc_program_size = 0;
139 int risc_flag = RISC_CNT_RESET;
140 unsigned int bottom_offset = bpl;
141 dma_addr_t risc_phys_jump_addr;
143 if (dev->_isNTSC_ch2) {
144 odd_num_lines = singlefield_lines + 1;
145 risc_program_size = FRAME1_VID_PROG_SIZE;
148 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
149 FRAME_SIZE_NTSC_Y422;
151 risc_program_size = PAL_VID_PROG_SIZE;
154 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
157 /* Virtual address of Risc buffer program */
158 rp = dev->_dma_virt_addr_ch2;
160 for (frame = 0; frame < NUM_FRAMES; frame++) {
161 databuf_offset = frame_size * frame;
163 if (UNSET != top_offset) {
164 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
165 rp = cx25821_risc_field_upstream_ch2(dev, rp,
167 _data_buf_phys_addr_ch2
175 fifo_enable = FIFO_DISABLE;
178 rp = cx25821_risc_field_upstream_ch2(dev, rp,
180 _data_buf_phys_addr_ch2 +
182 bottom_offset, 0x200, bpl,
184 fifo_enable, EVEN_FIELD);
187 risc_flag = RISC_CNT_RESET;
188 risc_phys_jump_addr =
189 dev->_dma_phys_start_addr_ch2 + risc_program_size;
191 risc_flag = RISC_CNT_INC;
192 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
195 // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
196 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
197 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
198 *(rp++) = cpu_to_le32(0);
204 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
206 struct sram_channel *sram_ch =
207 &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_J];
210 if (!dev->_is_running_ch2) {
212 ("cx25821: No video file is currently running so return!\n");
215 //Disable RISC interrupts
216 tmp = cx_read(sram_ch->int_msk);
217 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
219 //Turn OFF risc and fifo
220 tmp = cx_read(sram_ch->dma_ctl);
221 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
223 //Clear data buffer memory
224 if (dev->_data_buf_virt_addr_ch2)
225 memset(dev->_data_buf_virt_addr_ch2, 0,
226 dev->_data_buf_size_ch2);
228 dev->_is_running_ch2 = 0;
229 dev->_is_first_frame_ch2 = 0;
230 dev->_frame_count_ch2 = 0;
231 dev->_file_status_ch2 = END_OF_FILE;
233 if (dev->_irq_queues_ch2) {
234 kfree(dev->_irq_queues_ch2);
235 dev->_irq_queues_ch2 = NULL;
238 if (dev->_filename_ch2 != NULL)
239 kfree(dev->_filename_ch2);
241 tmp = cx_read(VID_CH_MODE_SEL);
242 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
245 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
247 if (dev->_is_running_ch2) {
248 cx25821_stop_upstream_video_ch2(dev);
251 if (dev->_dma_virt_addr_ch2) {
252 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
253 dev->_dma_virt_addr_ch2,
254 dev->_dma_phys_addr_ch2);
255 dev->_dma_virt_addr_ch2 = NULL;
258 if (dev->_data_buf_virt_addr_ch2) {
259 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
260 dev->_data_buf_virt_addr_ch2,
261 dev->_data_buf_phys_addr_ch2);
262 dev->_data_buf_virt_addr_ch2 = NULL;
266 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
269 int frame_index_temp = dev->_frame_index_ch2;
272 (dev->_pixel_format_ch2 ==
273 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
275 int frame_offset = 0;
276 ssize_t vfs_read_retval = 0;
277 char mybuf[line_size];
282 if (dev->_file_status_ch2 == END_OF_FILE)
285 if (dev->_isNTSC_ch2) {
288 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
289 FRAME_SIZE_NTSC_Y422;
293 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
296 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
297 file_offset = dev->_frame_count_ch2 * frame_size;
299 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
301 if (IS_ERR(myfile)) {
302 const int open_errno = -PTR_ERR(myfile);
303 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
304 __func__, dev->_filename_ch2, open_errno);
305 return PTR_ERR(myfile);
307 if (!(myfile->f_op)) {
308 printk("%s: File has no file operations registered!",
310 filp_close(myfile, NULL);
314 if (!myfile->f_op->read) {
315 printk("%s: File has no READ operations registered!",
317 filp_close(myfile, NULL);
325 for (i = 0; i < dev->_lines_count_ch2; i++) {
329 vfs_read(myfile, mybuf, line_size, &pos);
331 if (vfs_read_retval > 0 && vfs_read_retval == line_size
332 && dev->_data_buf_virt_addr_ch2 != NULL) {
333 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
334 frame_offset / 4), mybuf,
338 file_offset += vfs_read_retval;
339 frame_offset += vfs_read_retval;
341 if (vfs_read_retval < line_size) {
343 "Done: exit %s() since no more bytes to read from Video file.\n",
350 dev->_frame_count_ch2++;
352 dev->_file_status_ch2 =
353 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
356 filp_close(myfile, NULL);
362 static void cx25821_vidups_handler_ch2(struct work_struct *work)
364 struct cx25821_dev *dev =
365 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
368 printk("ERROR %s(): since container_of(work_struct) FAILED! \n",
373 cx25821_get_frame_ch2(dev,
374 &dev->sram_channels[dev->
375 _channel2_upstream_select]);
378 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
383 (dev->_pixel_format_ch2 ==
384 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
385 ssize_t vfs_read_retval = 0;
386 char mybuf[line_size];
388 loff_t offset = (unsigned long)0;
391 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
393 if (IS_ERR(myfile)) {
394 const int open_errno = -PTR_ERR(myfile);
395 printk("%s(): ERROR opening file(%s) with errno = %d! \n",
396 __func__, dev->_filename_ch2, open_errno);
397 return PTR_ERR(myfile);
399 if (!(myfile->f_op)) {
400 printk("%s: File has no file operations registered!",
402 filp_close(myfile, NULL);
406 if (!myfile->f_op->read) {
408 ("%s: File has no READ operations registered! Returning.",
410 filp_close(myfile, NULL);
418 for (j = 0; j < NUM_FRAMES; j++) {
419 for (i = 0; i < dev->_lines_count_ch2; i++) {
423 vfs_read(myfile, mybuf, line_size, &pos);
425 if (vfs_read_retval > 0
426 && vfs_read_retval == line_size
427 && dev->_data_buf_virt_addr_ch2 != NULL) {
428 memcpy((void *)(dev->
429 _data_buf_virt_addr_ch2
430 + offset / 4), mybuf,
434 offset += vfs_read_retval;
436 if (vfs_read_retval < line_size) {
438 "Done: exit %s() since no more bytes to read from Video file.\n",
445 dev->_frame_count_ch2++;
447 if (vfs_read_retval < line_size) {
452 dev->_file_status_ch2 =
453 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
457 filp_close(myfile, NULL);
463 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
464 struct sram_channel *sram_ch,
469 dma_addr_t data_dma_addr;
471 if (dev->_dma_virt_addr_ch2 != NULL) {
472 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
473 dev->_dma_virt_addr_ch2,
474 dev->_dma_phys_addr_ch2);
477 dev->_dma_virt_addr_ch2 =
478 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
480 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
481 dev->_dma_phys_start_addr_ch2 = dma_addr;
482 dev->_dma_phys_addr_ch2 = dma_addr;
483 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
485 if (!dev->_dma_virt_addr_ch2) {
487 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
491 //Iniitize at this address until n bytes to 0
492 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
494 if (dev->_data_buf_virt_addr_ch2 != NULL) {
495 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
496 dev->_data_buf_virt_addr_ch2,
497 dev->_data_buf_phys_addr_ch2);
499 //For Video Data buffer allocation
500 dev->_data_buf_virt_addr_ch2 =
501 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
503 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
504 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
506 if (!dev->_data_buf_virt_addr_ch2) {
508 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
512 //Initialize at this address until n bytes to 0
513 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
515 ret = cx25821_openfile_ch2(dev, sram_ch);
519 //Creating RISC programs
521 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
522 dev->_lines_count_ch2);
525 "cx25821: Failed creating Video Upstream Risc programs! \n");
535 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
539 struct sram_channel *channel = &dev->sram_channels[chan_num];
540 int singlefield_lines = NTSC_FIELD_HEIGHT;
541 int line_size_in_bytes = Y422_LINE_SZ;
542 int odd_risc_prog_size = 0;
543 dma_addr_t risc_phys_jump_addr;
546 if (status & FLD_VID_SRC_RISC1) {
547 // We should only process one program per call
548 u32 prog_cnt = cx_read(channel->gpcnt);
550 //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
551 int_msk_tmp = cx_read(channel->int_msk);
552 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
553 cx_write(channel->int_stat, _intr_msk);
555 spin_lock(&dev->slock);
557 dev->_frame_index_ch2 = prog_cnt;
559 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
561 if (dev->_is_first_frame_ch2) {
562 dev->_is_first_frame_ch2 = 0;
564 if (dev->_isNTSC_ch2) {
565 singlefield_lines += 1;
566 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
568 singlefield_lines = PAL_FIELD_HEIGHT;
569 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
572 if (dev->_dma_virt_start_addr_ch2 != NULL) {
574 (dev->_pixel_format_ch2 ==
575 PIXEL_FRMT_411) ? Y411_LINE_SZ :
577 risc_phys_jump_addr =
578 dev->_dma_phys_start_addr_ch2 +
581 rp = cx25821_update_riscprogram_ch2(dev,
583 _dma_virt_start_addr_ch2,
591 // Jump to Even Risc program of 1st Frame
592 *(rp++) = cpu_to_le32(RISC_JUMP);
593 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
594 *(rp++) = cpu_to_le32(0);
598 spin_unlock(&dev->slock);
601 if (dev->_file_status_ch2 == END_OF_FILE) {
602 printk("cx25821: EOF Channel 2 Framecount = %d\n",
603 dev->_frame_count_ch2);
606 //ElSE, set the interrupt mask register, re-enable irq.
607 int_msk_tmp = cx_read(channel->int_msk);
608 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
613 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
615 struct cx25821_dev *dev = dev_id;
616 u32 msk_stat, vid_status;
619 struct sram_channel *sram_ch;
624 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
626 sram_ch = &dev->sram_channels[channel_num];
628 msk_stat = cx_read(sram_ch->int_mstat);
629 vid_status = cx_read(sram_ch->int_stat);
631 // Only deal with our interrupt
634 cx25821_video_upstream_irq_ch2(dev, channel_num,
639 cx25821_stop_upstream_video_ch2(dev);
644 return IRQ_RETVAL(handled);
647 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
648 struct sram_channel *ch, int pix_format)
650 int width = WIDTH_D1;
651 int height = dev->_lines_count_ch2;
652 int num_lines, odd_num_lines;
654 int vip_mode = PIXEL_ENGINE_VIP1;
656 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
658 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
659 cx_write(ch->vid_fmt_ctl, value);
661 // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
662 cx_write(ch->vid_active_ctl1, width);
664 num_lines = (height / 2) & 0x3FF;
665 odd_num_lines = num_lines;
667 if (dev->_isNTSC_ch2) {
671 value = (num_lines << 16) | odd_num_lines;
673 // set number of active lines in field 0 (top) and field 1 (bottom)
674 cx_write(ch->vid_active_ctl2, value);
676 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
679 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
680 struct sram_channel *sram_ch)
685 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
686 tmp = cx_read(VID_CH_MODE_SEL);
687 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
689 // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
690 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
691 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
694 cx_write(sram_ch->gpcnt_ctl, 3);
696 // Clear our bits from the interrupt status register.
697 cx_write(sram_ch->int_stat, _intr_msk);
699 //Set the interrupt mask register, enable irq.
700 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
701 tmp = cx_read(sram_ch->int_msk);
702 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
705 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
706 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
708 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
712 // Start the DMA engine
713 tmp = cx_read(sram_ch->dma_ctl);
714 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
716 dev->_is_running_ch2 = 1;
717 dev->_is_first_frame_ch2 = 1;
722 cx25821_dev_unregister(dev);
726 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
729 struct sram_channel *sram_ch;
733 int data_frame_size = 0;
734 int risc_buffer_size = 0;
737 if (dev->_is_running_ch2) {
738 printk("Video Channel is still running so return!\n");
742 dev->_channel2_upstream_select = channel_select;
743 sram_ch = &dev->sram_channels[channel_select];
745 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
746 dev->_irq_queues_ch2 =
747 create_singlethread_workqueue("cx25821_workqueue2");
749 if (!dev->_irq_queues_ch2) {
751 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
754 // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
755 tmp = cx_read(VID_CH_MODE_SEL);
756 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
758 dev->_is_running_ch2 = 0;
759 dev->_frame_count_ch2 = 0;
760 dev->_file_status_ch2 = RESET_STATUS;
761 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
762 dev->_pixel_format_ch2 = pixel_format;
763 dev->_line_size_ch2 =
764 (dev->_pixel_format_ch2 ==
765 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
766 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
768 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
770 if (dev->input_filename_ch2) {
771 str_length = strlen(dev->input_filename_ch2);
773 (char *)kmalloc(str_length + 1, GFP_KERNEL);
775 if (!dev->_filename_ch2)
778 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
781 str_length = strlen(dev->_defaultname_ch2);
783 (char *)kmalloc(str_length + 1, GFP_KERNEL);
785 if (!dev->_filename_ch2)
788 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
792 //Default if filename is empty string
793 if (strcmp(dev->input_filename_ch2, "") == 0) {
794 if (dev->_isNTSC_ch2) {
796 (dev->_pixel_format_ch2 ==
797 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
801 (dev->_pixel_format_ch2 ==
802 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
808 cx25821_sram_channel_setup_upstream(dev, sram_ch,
809 dev->_line_size_ch2, 0);
811 /* setup fifo + format */
812 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
814 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
815 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
817 //Allocating buffers and prepare RISC program
819 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
820 dev->_line_size_ch2);
823 "%s: Failed to set up Video upstream buffers!\n",
828 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
833 cx25821_dev_unregister(dev);