2 * Driver for the Conexant CX25821 PCIe bridge
4 * Copyright (C) 2009 Conexant Systems Inc.
5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include "cx25821-video.h"
24 #include "cx25821-video-upstream-ch2.h"
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/init.h>
30 #include <linux/module.h>
31 #include <linux/syscalls.h>
32 #include <linux/file.h>
33 #include <linux/fcntl.h>
34 #include <linux/slab.h>
35 #include <linux/uaccess.h>
37 MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
38 MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
39 MODULE_LICENSE("GPL");
41 static int _intr_msk =
42 FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
44 static __le32 *cx25821_update_riscprogram_ch2(struct cx25821_dev *dev,
45 __le32 *rp, unsigned int offset,
46 unsigned int bpl, u32 sync_line,
48 int fifo_enable, int field_type)
51 int dist_betwn_starts = bpl * 2;
53 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
55 if (USE_RISC_NOOP_VIDEO) {
56 for (i = 0; i < NUM_NO_OPS; i++)
57 *(rp++) = cpu_to_le32(RISC_NOOP);
61 for (line = 0; line < lines; line++) {
62 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
63 *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr_ch2 + offset);
64 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
66 if ((lines <= NTSC_FIELD_HEIGHT)
67 || (line < (NTSC_FIELD_HEIGHT - 1))
68 || !(dev->_isNTSC_ch2)) {
69 offset += dist_betwn_starts;
76 static __le32 *cx25821_risc_field_upstream_ch2(struct cx25821_dev *dev,
78 dma_addr_t databuf_phys_addr,
80 u32 sync_line, unsigned int bpl,
82 int fifo_enable, int field_type)
85 struct sram_channel *sram_ch =
86 dev->channels[dev->_channel2_upstream_select].sram_channels;
87 int dist_betwn_starts = bpl * 2;
89 /* sync instruction */
90 if (sync_line != NO_SYNC_LINE)
91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
93 if (USE_RISC_NOOP_VIDEO) {
94 for (i = 0; i < NUM_NO_OPS; i++)
95 *(rp++) = cpu_to_le32(RISC_NOOP);
99 for (line = 0; line < lines; line++) {
100 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl);
101 *(rp++) = cpu_to_le32(databuf_phys_addr + offset);
102 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
104 if ((lines <= NTSC_FIELD_HEIGHT)
105 || (line < (NTSC_FIELD_HEIGHT - 1))
106 || !(dev->_isNTSC_ch2)) {
107 offset += dist_betwn_starts;
111 check if we need to enable the FIFO after the first 4 lines
112 For the upstream video channel, the risc engine will enable
115 if (fifo_enable && line == 3) {
116 *(rp++) = RISC_WRITECR;
117 *(rp++) = sram_ch->dma_ctl;
118 *(rp++) = FLD_VID_FIFO_EN;
119 *(rp++) = 0x00000001;
126 int cx25821_risc_buffer_upstream_ch2(struct cx25821_dev *dev,
128 unsigned int top_offset, unsigned int bpl,
133 int singlefield_lines = lines >> 1; /*get line count for single field */
134 int odd_num_lines = singlefield_lines;
137 int databuf_offset = 0;
138 int risc_program_size = 0;
139 int risc_flag = RISC_CNT_RESET;
140 unsigned int bottom_offset = bpl;
141 dma_addr_t risc_phys_jump_addr;
143 if (dev->_isNTSC_ch2) {
144 odd_num_lines = singlefield_lines + 1;
145 risc_program_size = FRAME1_VID_PROG_SIZE;
148 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
149 FRAME_SIZE_NTSC_Y422;
151 risc_program_size = PAL_VID_PROG_SIZE;
154 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
157 /* Virtual address of Risc buffer program */
158 rp = dev->_dma_virt_addr_ch2;
160 for (frame = 0; frame < NUM_FRAMES; frame++) {
161 databuf_offset = frame_size * frame;
163 if (UNSET != top_offset) {
164 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
165 rp = cx25821_risc_field_upstream_ch2(dev, rp,
167 _data_buf_phys_addr_ch2
175 fifo_enable = FIFO_DISABLE;
178 rp = cx25821_risc_field_upstream_ch2(dev, rp,
180 _data_buf_phys_addr_ch2 +
182 bottom_offset, 0x200, bpl,
184 fifo_enable, EVEN_FIELD);
187 risc_flag = RISC_CNT_RESET;
188 risc_phys_jump_addr =
189 dev->_dma_phys_start_addr_ch2 + risc_program_size;
191 risc_flag = RISC_CNT_INC;
192 risc_phys_jump_addr = dev->_dma_phys_start_addr_ch2;
196 Loop to 2ndFrameRISC or to Start of
197 Risc program & generate IRQ
199 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag);
200 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
201 *(rp++) = cpu_to_le32(0);
207 void cx25821_stop_upstream_video_ch2(struct cx25821_dev *dev)
209 struct sram_channel *sram_ch =
210 dev->channels[VID_UPSTREAM_SRAM_CHANNEL_J].sram_channels;
213 if (!dev->_is_running_ch2) {
215 ("cx25821: No video file is currently running so return!\n");
218 /* Disable RISC interrupts */
219 tmp = cx_read(sram_ch->int_msk);
220 cx_write(sram_ch->int_msk, tmp & ~_intr_msk);
222 /* Turn OFF risc and fifo */
223 tmp = cx_read(sram_ch->dma_ctl);
224 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN));
226 /* Clear data buffer memory */
227 if (dev->_data_buf_virt_addr_ch2)
228 memset(dev->_data_buf_virt_addr_ch2, 0,
229 dev->_data_buf_size_ch2);
231 dev->_is_running_ch2 = 0;
232 dev->_is_first_frame_ch2 = 0;
233 dev->_frame_count_ch2 = 0;
234 dev->_file_status_ch2 = END_OF_FILE;
236 if (dev->_irq_queues_ch2) {
237 kfree(dev->_irq_queues_ch2);
238 dev->_irq_queues_ch2 = NULL;
241 if (dev->_filename_ch2 != NULL)
242 kfree(dev->_filename_ch2);
244 tmp = cx_read(VID_CH_MODE_SEL);
245 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
248 void cx25821_free_mem_upstream_ch2(struct cx25821_dev *dev)
250 if (dev->_is_running_ch2)
251 cx25821_stop_upstream_video_ch2(dev);
253 if (dev->_dma_virt_addr_ch2) {
254 pci_free_consistent(dev->pci, dev->_risc_size_ch2,
255 dev->_dma_virt_addr_ch2,
256 dev->_dma_phys_addr_ch2);
257 dev->_dma_virt_addr_ch2 = NULL;
260 if (dev->_data_buf_virt_addr_ch2) {
261 pci_free_consistent(dev->pci, dev->_data_buf_size_ch2,
262 dev->_data_buf_virt_addr_ch2,
263 dev->_data_buf_phys_addr_ch2);
264 dev->_data_buf_virt_addr_ch2 = NULL;
268 int cx25821_get_frame_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
271 int frame_index_temp = dev->_frame_index_ch2;
274 (dev->_pixel_format_ch2 ==
275 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
277 int frame_offset = 0;
278 ssize_t vfs_read_retval = 0;
279 char mybuf[line_size];
284 if (dev->_file_status_ch2 == END_OF_FILE)
287 if (dev->_isNTSC_ch2) {
290 Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 :
291 FRAME_SIZE_NTSC_Y422;
295 Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
298 frame_offset = (frame_index_temp > 0) ? frame_size : 0;
299 file_offset = dev->_frame_count_ch2 * frame_size;
301 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
302 if (IS_ERR(myfile)) {
303 const int open_errno = -PTR_ERR(myfile);
304 printk("%s(): ERROR opening file(%s) with errno = %d!\n",
305 __func__, dev->_filename_ch2, open_errno);
306 return PTR_ERR(myfile);
308 if (!(myfile->f_op)) {
309 printk("%s: File has no file operations registered!",
311 filp_close(myfile, NULL);
315 if (!myfile->f_op->read) {
316 printk("%s: File has no READ operations registered!",
318 filp_close(myfile, NULL);
326 for (i = 0; i < dev->_lines_count_ch2; i++) {
330 vfs_read(myfile, mybuf, line_size, &pos);
332 if (vfs_read_retval > 0 && vfs_read_retval == line_size
333 && dev->_data_buf_virt_addr_ch2 != NULL) {
334 memcpy((void *)(dev->_data_buf_virt_addr_ch2 +
335 frame_offset / 4), mybuf,
339 file_offset += vfs_read_retval;
340 frame_offset += vfs_read_retval;
342 if (vfs_read_retval < line_size) {
344 "Done: exit %s() since no more bytes to read from Video file.\n",
351 dev->_frame_count_ch2++;
353 dev->_file_status_ch2 =
354 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
357 filp_close(myfile, NULL);
363 static void cx25821_vidups_handler_ch2(struct work_struct *work)
365 struct cx25821_dev *dev =
366 container_of(work, struct cx25821_dev, _irq_work_entry_ch2);
369 printk("ERROR %s(): since container_of(work_struct) FAILED!\n",
374 cx25821_get_frame_ch2(dev,
376 _channel2_upstream_select].sram_channels);
379 int cx25821_openfile_ch2(struct cx25821_dev *dev, struct sram_channel *sram_ch)
384 (dev->_pixel_format_ch2 ==
385 PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
386 ssize_t vfs_read_retval = 0;
387 char mybuf[line_size];
389 loff_t offset = (unsigned long)0;
392 myfile = filp_open(dev->_filename_ch2, O_RDONLY | O_LARGEFILE, 0);
394 if (IS_ERR(myfile)) {
395 const int open_errno = -PTR_ERR(myfile);
396 printk("%s(): ERROR opening file(%s) with errno = %d!\n",
397 __func__, dev->_filename_ch2, open_errno);
398 return PTR_ERR(myfile);
400 if (!(myfile->f_op)) {
401 printk("%s: File has no file operations registered!",
403 filp_close(myfile, NULL);
407 if (!myfile->f_op->read) {
409 ("%s: File has no READ operations registered! Returning.",
411 filp_close(myfile, NULL);
419 for (j = 0; j < NUM_FRAMES; j++) {
420 for (i = 0; i < dev->_lines_count_ch2; i++) {
424 vfs_read(myfile, mybuf, line_size, &pos);
426 if (vfs_read_retval > 0
427 && vfs_read_retval == line_size
428 && dev->_data_buf_virt_addr_ch2 != NULL) {
429 memcpy((void *)(dev->
430 _data_buf_virt_addr_ch2
431 + offset / 4), mybuf,
435 offset += vfs_read_retval;
437 if (vfs_read_retval < line_size) {
439 "Done: exit %s() since no more bytes to read from Video file.\n",
446 dev->_frame_count_ch2++;
448 if (vfs_read_retval < line_size)
452 dev->_file_status_ch2 =
453 (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
457 filp_close(myfile, NULL);
463 static int cx25821_upstream_buffer_prepare_ch2(struct cx25821_dev *dev,
464 struct sram_channel *sram_ch,
469 dma_addr_t data_dma_addr;
471 if (dev->_dma_virt_addr_ch2 != NULL) {
472 pci_free_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
473 dev->_dma_virt_addr_ch2,
474 dev->_dma_phys_addr_ch2);
477 dev->_dma_virt_addr_ch2 =
478 pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size_ch2,
480 dev->_dma_virt_start_addr_ch2 = dev->_dma_virt_addr_ch2;
481 dev->_dma_phys_start_addr_ch2 = dma_addr;
482 dev->_dma_phys_addr_ch2 = dma_addr;
483 dev->_risc_size_ch2 = dev->upstream_riscbuf_size_ch2;
485 if (!dev->_dma_virt_addr_ch2) {
487 ("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
491 /* Iniitize at this address until n bytes to 0 */
492 memset(dev->_dma_virt_addr_ch2, 0, dev->_risc_size_ch2);
494 if (dev->_data_buf_virt_addr_ch2 != NULL) {
495 pci_free_consistent(dev->pci, dev->upstream_databuf_size_ch2,
496 dev->_data_buf_virt_addr_ch2,
497 dev->_data_buf_phys_addr_ch2);
499 /* For Video Data buffer allocation */
500 dev->_data_buf_virt_addr_ch2 =
501 pci_alloc_consistent(dev->pci, dev->upstream_databuf_size_ch2,
503 dev->_data_buf_phys_addr_ch2 = data_dma_addr;
504 dev->_data_buf_size_ch2 = dev->upstream_databuf_size_ch2;
506 if (!dev->_data_buf_virt_addr_ch2) {
508 ("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
512 /* Initialize at this address until n bytes to 0 */
513 memset(dev->_data_buf_virt_addr_ch2, 0, dev->_data_buf_size_ch2);
515 ret = cx25821_openfile_ch2(dev, sram_ch);
519 /* Creating RISC programs */
521 cx25821_risc_buffer_upstream_ch2(dev, dev->pci, 0, bpl,
522 dev->_lines_count_ch2);
525 "cx25821: Failed creating Video Upstream Risc programs!\n");
535 int cx25821_video_upstream_irq_ch2(struct cx25821_dev *dev, int chan_num,
539 struct sram_channel *channel = dev->channels[chan_num].sram_channels;
540 int singlefield_lines = NTSC_FIELD_HEIGHT;
541 int line_size_in_bytes = Y422_LINE_SZ;
542 int odd_risc_prog_size = 0;
543 dma_addr_t risc_phys_jump_addr;
546 if (status & FLD_VID_SRC_RISC1) {
547 /* We should only process one program per call */
548 u32 prog_cnt = cx_read(channel->gpcnt);
551 * Since we've identified our IRQ, clear our bits from the
552 * interrupt mask and interrupt status registers
554 int_msk_tmp = cx_read(channel->int_msk);
555 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
556 cx_write(channel->int_stat, _intr_msk);
558 spin_lock(&dev->slock);
560 dev->_frame_index_ch2 = prog_cnt;
562 queue_work(dev->_irq_queues_ch2, &dev->_irq_work_entry_ch2);
564 if (dev->_is_first_frame_ch2) {
565 dev->_is_first_frame_ch2 = 0;
567 if (dev->_isNTSC_ch2) {
568 singlefield_lines += 1;
569 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
571 singlefield_lines = PAL_FIELD_HEIGHT;
572 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
575 if (dev->_dma_virt_start_addr_ch2 != NULL) {
577 (dev->_pixel_format_ch2 ==
578 PIXEL_FRMT_411) ? Y411_LINE_SZ :
580 risc_phys_jump_addr =
581 dev->_dma_phys_start_addr_ch2 +
584 rp = cx25821_update_riscprogram_ch2(dev,
586 _dma_virt_start_addr_ch2,
594 /* Jump to Even Risc program of 1st Frame */
595 *(rp++) = cpu_to_le32(RISC_JUMP);
596 *(rp++) = cpu_to_le32(risc_phys_jump_addr);
597 *(rp++) = cpu_to_le32(0);
601 spin_unlock(&dev->slock);
604 if (dev->_file_status_ch2 == END_OF_FILE) {
605 printk("cx25821: EOF Channel 2 Framecount = %d\n",
606 dev->_frame_count_ch2);
609 /* ElSE, set the interrupt mask register, re-enable irq. */
610 int_msk_tmp = cx_read(channel->int_msk);
611 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk);
616 static irqreturn_t cx25821_upstream_irq_ch2(int irq, void *dev_id)
618 struct cx25821_dev *dev = dev_id;
619 u32 msk_stat, vid_status;
622 struct sram_channel *sram_ch;
627 channel_num = VID_UPSTREAM_SRAM_CHANNEL_J;
628 sram_ch = dev->channels[channel_num].sram_channels;
630 msk_stat = cx_read(sram_ch->int_mstat);
631 vid_status = cx_read(sram_ch->int_stat);
633 /* Only deal with our interrupt */
636 cx25821_video_upstream_irq_ch2(dev, channel_num,
641 cx25821_stop_upstream_video_ch2(dev);
645 return IRQ_RETVAL(handled);
648 static void cx25821_set_pixelengine_ch2(struct cx25821_dev *dev,
649 struct sram_channel *ch, int pix_format)
651 int width = WIDTH_D1;
652 int height = dev->_lines_count_ch2;
653 int num_lines, odd_num_lines;
655 int vip_mode = PIXEL_ENGINE_VIP1;
657 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7);
659 value |= dev->_isNTSC_ch2 ? 0 : 0x10;
660 cx_write(ch->vid_fmt_ctl, value);
663 * set number of active pixels in each line. Default is 720
664 * pixels in both NTSC and PAL format
666 cx_write(ch->vid_active_ctl1, width);
668 num_lines = (height / 2) & 0x3FF;
669 odd_num_lines = num_lines;
671 if (dev->_isNTSC_ch2)
674 value = (num_lines << 16) | odd_num_lines;
676 /* set number of active lines in field 0 (top) and field 1 (bottom) */
677 cx_write(ch->vid_active_ctl2, value);
679 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3);
682 int cx25821_start_video_dma_upstream_ch2(struct cx25821_dev *dev,
683 struct sram_channel *sram_ch)
689 * 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface
692 tmp = cx_read(VID_CH_MODE_SEL);
693 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
696 * Set the physical start address of the RISC program in the initial
697 * program counter(IPC) member of the cmds.
699 cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr_ch2);
700 cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
703 cx_write(sram_ch->gpcnt_ctl, 3);
705 /* Clear our bits from the interrupt status register. */
706 cx_write(sram_ch->int_stat, _intr_msk);
708 /* Set the interrupt mask register, enable irq. */
709 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
710 tmp = cx_read(sram_ch->int_msk);
711 cx_write(sram_ch->int_msk, tmp |= _intr_msk);
714 request_irq(dev->pci->irq, cx25821_upstream_irq_ch2,
715 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
717 printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name,
721 /* Start the DMA engine */
722 tmp = cx_read(sram_ch->dma_ctl);
723 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN);
725 dev->_is_running_ch2 = 1;
726 dev->_is_first_frame_ch2 = 1;
731 cx25821_dev_unregister(dev);
735 int cx25821_vidupstream_init_ch2(struct cx25821_dev *dev, int channel_select,
738 struct sram_channel *sram_ch;
742 int data_frame_size = 0;
743 int risc_buffer_size = 0;
746 if (dev->_is_running_ch2) {
747 printk("Video Channel is still running so return!\n");
751 dev->_channel2_upstream_select = channel_select;
752 sram_ch = dev->channels[channel_select].sram_channels;
754 INIT_WORK(&dev->_irq_work_entry_ch2, cx25821_vidups_handler_ch2);
755 dev->_irq_queues_ch2 =
756 create_singlethread_workqueue("cx25821_workqueue2");
758 if (!dev->_irq_queues_ch2) {
760 ("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
764 * 656/VIP SRC Upstream Channel I & J and 7 -
765 * Host Bus Interface for channel A-C
767 tmp = cx_read(VID_CH_MODE_SEL);
768 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF);
770 dev->_is_running_ch2 = 0;
771 dev->_frame_count_ch2 = 0;
772 dev->_file_status_ch2 = RESET_STATUS;
773 dev->_lines_count_ch2 = dev->_isNTSC_ch2 ? 480 : 576;
774 dev->_pixel_format_ch2 = pixel_format;
775 dev->_line_size_ch2 =
776 (dev->_pixel_format_ch2 ==
777 PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
778 data_frame_size = dev->_isNTSC_ch2 ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
780 dev->_isNTSC_ch2 ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
782 if (dev->input_filename_ch2) {
783 str_length = strlen(dev->input_filename_ch2);
784 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
786 if (!dev->_filename_ch2)
789 memcpy(dev->_filename_ch2, dev->input_filename_ch2,
792 str_length = strlen(dev->_defaultname_ch2);
793 dev->_filename_ch2 = kmalloc(str_length + 1, GFP_KERNEL);
795 if (!dev->_filename_ch2)
798 memcpy(dev->_filename_ch2, dev->_defaultname_ch2,
802 /* Default if filename is empty string */
803 if (strcmp(dev->input_filename_ch2, "") == 0) {
804 if (dev->_isNTSC_ch2) {
806 (dev->_pixel_format_ch2 ==
807 PIXEL_FRMT_411) ? "/root/vid411.yuv" :
811 (dev->_pixel_format_ch2 ==
812 PIXEL_FRMT_411) ? "/root/pal411.yuv" :
818 cx25821_sram_channel_setup_upstream(dev, sram_ch,
819 dev->_line_size_ch2, 0);
821 /* setup fifo + format */
822 cx25821_set_pixelengine_ch2(dev, sram_ch, dev->_pixel_format_ch2);
824 dev->upstream_riscbuf_size_ch2 = risc_buffer_size * 2;
825 dev->upstream_databuf_size_ch2 = data_frame_size * 2;
827 /* Allocating buffers and prepare RISC program */
829 cx25821_upstream_buffer_prepare_ch2(dev, sram_ch,
830 dev->_line_size_ch2);
833 "%s: Failed to set up Video upstream buffers!\n",
838 cx25821_start_video_dma_upstream_ch2(dev, sram_ch);
843 cx25821_dev_unregister(dev);