drivers/staging/cxt1e1/comet.c

   1 /* Copyright (C) 2003-2005  SBE, Inc.
   2  *
   3  *   This program is free software; you can redistribute it and/or modify
   4  *   it under the terms of the GNU General Public License as published by
   5  *   the Free Software Foundation; either version 2 of the License, or
   6  *   (at your option) any later version.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #include <asm/io.h>
  15 #include <linux/hdlc.h>
  16 #include "pmcc4_sysdep.h"
  17 #include "sbecom_inline_linux.h"
  18 #include "libsbew.h"
  19 #include "pmcc4.h"
  20 #include "comet.h"
  21 #include "comet_tables.h"
  22
  23 #ifdef SBE_INCLUDE_SYMBOLS
  24 #define STATIC
  25 #else
  26 #define STATIC  static
  27 #endif
  28
  29
  30 extern int  log_level;
  31
  32 #define COMET_NUM_SAMPLES   24  /* Number of entries in the waveform table */
  33 #define COMET_NUM_UNITS     5   /* Number of points per entry in table */
  34
  35 /* forward references */
  36 STATIC void SetPwrLevel (comet_t * comet);
  37 STATIC void WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table);
  38 STATIC void WrtXmtWaveformTbl (ci_t * ci, comet_t * comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
  39
  40
  41 void       *TWV_table[12] = {
  42     TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
  43     TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4,
  44     TWVShortHaul5,
  45     TWV_E1_75Ohm,    /** PORT POINT - 75 Ohm not supported **/
  46     TWV_E1_120Ohm
  47 };
  48
  49
  50 static int
  51 lbo_tbl_lkup (int t1, int lbo)
  52 {
  53     if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120))    /* error switches to
  54                                                          * default */
  55     {
  56         if (t1)
  57             lbo = CFG_LBO_LH0;  /* default T1 waveform table */
  58         else
  59             lbo = CFG_LBO_E120;     /* default E1 waveform table */
  60     }
  61     return (lbo - 1);               /* make index ZERO relative */
  62 }
  63
  64
  65 void
  66 init_comet (void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
  67             u_int8_t moreParams)
  68 {
  69     u_int8_t isT1mode;
  70     u_int8_t    tix = CFG_LBO_LH0;      /* T1 default */
  71
  72     isT1mode = IS_FRAME_ANY_T1 (port_mode);
  73     /* T1 or E1 */
  74     if (isT1mode)
  75     {
  76         pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0);     /* Select T1 Mode & PIO
  77                                                                  * output enabled */
  78         tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0);     /* default T1 waveform
  79                                                          * table */
  80     } else
  81     {
  82         pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0x81);     /* Select E1 Mode & PIO
  83                                                                  * output enabled */
  84         tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120);    /* default E1 waveform
  85                                                          * table */
  86     }
  87
  88     if (moreParams & CFG_LBO_MASK)
  89         tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK);       /* dial-in requested
  90                                                                          * waveform table */
  91
  92     /* Tx line Intfc cfg     ** Set for analog & no special patterns */
  93     pci_write_32 ((u_int32_t *) &comet->tx_line_cfg, 0x00);     /* Transmit Line
  94                                                                  * Interface Config. */
  95
  96     /* master test    ** Ignore Test settings for now */
  97     pci_write_32 ((u_int32_t *) &comet->mtest, 0x00);   /* making sure it's
  98                                                          * Default value */
  99
 100     /* Turn on Center (CENT) and everything else off */
 101     pci_write_32 ((u_int32_t *) &comet->rjat_cfg, 0x10);        /* RJAT cfg */
 102     /* Set Jitter Attenuation to recommend T1 values */
 103     if (isT1mode)
 104     {
 105         pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0x2F);  /* RJAT Divider N1
 106                                                                  * Control */
 107         pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0x2F);  /* RJAT Divider N2
 108                                                                  * Control */
 109     } else
 110     {
 111         pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0xFF);  /* RJAT Divider N1
 112                                                                  * Control */
 113         pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0xFF);  /* RJAT Divider N2
 114                                                                  * Control */
 115     }
 116
 117     /* Turn on Center (CENT) and everything else off */
 118     pci_write_32 ((u_int32_t *) &comet->tjat_cfg, 0x10);        /* TJAT Config. */
 119
 120     /* Do not bypass jitter attenuation and bypass elastic store */
 121     pci_write_32 ((u_int32_t *) &comet->rx_opt, 0x00);  /* rx opts */
 122
 123     /* TJAT ctrl & TJAT divider ctrl */
 124     /* Set Jitter Attenuation to recommended T1 values */
 125     if (isT1mode)
 126     {
 127         pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0x2F);  /* TJAT Divider N1
 128                                                                  * Control */
 129         pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0x2F);  /* TJAT Divider N2
 130                                                                  * Control */
 131     } else
 132     {
 133         pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0xFF);  /* TJAT Divider N1
 134                                                                  * Control */
 135         pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0xFF);  /* TJAT Divider N2
 136                                                                  * Control */
 137     }
 138
 139     /* 1c: rx ELST cfg   20: tx ELST cfg  28&38: rx&tx data link ctrl */
 140     if (isT1mode)
 141     {                               /* Select 193-bit frame format */
 142         pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x00);
 143         pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x00);
 144     } else
 145     {                               /* Select 256-bit frame format */
 146         pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x03);
 147         pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x03);
 148         pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x00);   /* disable T1 data link
 149                                                                  * receive */
 150         pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x00);   /* disable T1 data link
 151                                                                  * transmit */
 152     }
 153
 154     /* the following is a default value */
 155     /* Enable 8 out of 10 validation */
 156     pci_write_32 ((u_int32_t *) &comet->t1_rboc_ena, 0x00);     /* t1RBOC
 157                                                                  * enable(BOC:BitOriented
 158                                                                  * Code) */
 159     if (isT1mode)
 160     {
 161
 162         /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
 163         pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x04);    /* 6 bit down, 5 bit up
 164                                                                  * (assert)  */
 165         pci_write_32 ((u_int32_t *) &comet->ibcd_act, 0x08);    /* line loopback
 166                                                                  * activate pattern */
 167         pci_write_32 ((u_int32_t *) &comet->ibcd_deact, 0x24);  /* deactivate code
 168                                                                  * pattern (i.e.001) */
 169     }
 170     /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg  */
 171     /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg  */
 172     /* 60: t1 ALMI cfg */
 173     /* Configure Line Coding */
 174
 175     switch (port_mode)
 176     {
 177     case CFG_FRAME_SF:              /* 1 - T1 B8ZS */
 178         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 179         pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0);
 180         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 181         pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */
 182         pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0);
 183         break;
 184     case CFG_FRAME_ESF:     /* 2 - T1 B8ZS */
 185         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 186         pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20);   /* Bit 5: T1 DataLink
 187                                                                  * Enable */
 188         pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20);   /* 5: T1 DataLink Enable */
 189         pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF  5:ESFFA */
 190         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04);    /* 2:ESF */
 191         pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF  5:B8ZS */
 192         pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
 193         break;
 194     case CFG_FRAME_E1PLAIN:         /* 3 - HDB3 */
 195         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 196         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 197         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0);
 198         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 199         break;
 200     case CFG_FRAME_E1CAS:           /* 4 - HDB3 */
 201         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 202         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 203         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x60);
 204         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0);
 205         break;
 206     case CFG_FRAME_E1CRC:           /* 5 - HDB3 */
 207         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 208         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 209         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x10);
 210         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 211         break;
 212     case CFG_FRAME_E1CRC_CAS:       /* 6 - HDB3 */
 213         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
 214         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 215         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x70);
 216         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 217         break;
 218     case CFG_FRAME_SF_AMI:          /* 7 - T1 AMI */
 219         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 220                                                                  * Decoding */
 221         pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0);
 222         pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0);
 223         pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0);
 224         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 225         break;
 226     case CFG_FRAME_ESF_AMI:         /* 8 - T1 AMI */
 227         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 228                                                                  * Decoding */
 229         pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20);   /* 5: T1 DataLink Enable */
 230         pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20);   /* 5: T1 DataLink Enable */
 231         pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF  5:ESFFA */
 232         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04);    /* 2:ESF */
 233         pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */
 234         pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
 235         break;
 236     case CFG_FRAME_E1PLAIN_AMI:       /* 9 - AMI */
 237         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 238                                                                  * Decoding */
 239         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 240         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x80);
 241         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 242         break;
 243     case CFG_FRAME_E1CAS_AMI:       /* 10 - AMI */
 244         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 245                                                                  * Decoding */
 246         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 247         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
 248         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0);
 249         break;
 250     case CFG_FRAME_E1CRC_AMI:       /* 11 - AMI */
 251         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 252                                                                  * Decoding */
 253         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 254         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x90);
 255         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 256         break;
 257     case CFG_FRAME_E1CRC_CAS_AMI:   /* 12 - AMI */
 258         pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80);    /* Enable AMI Line
 259                                                                  * Decoding */
 260         pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
 261         pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
 262         pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 263         break;
 264     }                               /* end switch */
 265
 266     /***
 267      * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
 268      * CMODE=1: Clock slave mode with BRCLK as an input,
 269      * DE=0: Use falling edge of BRCLK for data,
 270      * FE=0: Use falling edge of BRCLK for frame,
 271      * CMS=0: Use backplane freq,
 272      * RATE[1:0]=0,0: T1
 273      ***/
 274
 275
 276     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
 277     /* note "rate bits can only be set once after reset" */
 278     if (clockmaster)
 279     {                               /* CMODE == clockMode, 0=clock master (so
 280                                      * all 3 others should be slave) */
 281         if (isT1mode)               /* rate = 1.544 Mb/s */
 282             pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x00);        /* Comet 0 Master
 283                                                                          * Mode(CMODE=0) */
 284         else                        /* rate = 2.048 Mb/s */
 285             pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x01);        /* Comet 0 Master
 286                                                                          * Mode(CMODE=0) */
 287
 288         /* 31: BRIF frame pulse cfg  06: tx timing options */
 289         pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x00);  /* Master Mode
 290                                                                  * i.e.FPMODE=0 (@0x20) */
 291         if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
 292         {
 293             if (log_level >= LOG_SBEBUG12)
 294                 printk (">> init_comet: clockmaster internal clock\n");
 295             pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */
 296         } else                      /* external clock source */
 297         {
 298             if (log_level >= LOG_SBEBUG12)
 299                 printk (">> init_comet: clockmaster external clock\n");
 300             pci_write_32 ((u_int32_t *) &comet->tx_time, 0x09); /* loop timing
 301                                                                  * (external) */
 302         }
 303
 304     } else                          /* slave */
 305     {
 306         if (isT1mode)
 307             pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x20);        /* Slave Mode(CMODE=1,
 308                                                                          * see above) */
 309         else
 310             pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x21);        /* Slave Mode (CMODE=1) */
 311         pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x20);  /* Slave Mode i.e.
 312                                                                  * FPMODE=1 (@0x20) */
 313         if (log_level >= LOG_SBEBUG12)
 314             printk (">> init_comet: clockslave internal clock\n");
 315         pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d);     /* oscillator timing */
 316     }
 317
 318     /* 32: BRIF parity F-bit cfg */
 319     /* Totem-pole operation */
 320     pci_write_32 ((u_int32_t *) &comet->brif_pfcfg, 0x01);      /* Receive Backplane
 321                                                                  * Parity/F-bit */
 322
 323     /* dc: RLPS equalizer V ref */
 324     /* Configuration */
 325     if (isT1mode)
 326         pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x2c);   /* RLPS Equalizer
 327                                                                  * Voltage  */
 328     else
 329         pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x34);   /* RLPS Equalizer
 330                                                                  * Voltage  */
 331
 332     /* Reserved bit set and SQUELCH enabled */
 333     /* f8: RLPS cfg & status  f9: RLPS ALOS detect/clear threshold */
 334     pci_write_32 ((u_int32_t *) &comet->rlps_cfgsts, 0x11);     /* RLPS Configuration
 335                                                                  * Status */
 336     if (isT1mode)
 337         pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x55);    /* ? */
 338     else
 339         pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x22);    /* ? */
 340
 341
 342     /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
 343     /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
 344     /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
 345     /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
 346 /***    Transmit side is always an Input, Slave Clock*/
 347     /* 40: BTIF cfg  41: BTIF frame pulse cfg */
 348     if (isT1mode)
 349         pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x38);    /* BTIF Configuration
 350                                                                  * Reg. */
 351     else
 352         pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x39);    /* BTIF Configuration
 353                                                                  * Reg. */
 354
 355     pci_write_32 ((u_int32_t *) &comet->btif_fpcfg, 0x01);      /* BTIF Frame Pulse
 356                                                                  * Config. */
 357
 358     /* 0a: master diag  06: tx timing options */
 359     /* if set Comet to loop back */
 360
 361     /* Comets set to normal */
 362     pci_write_32 ((u_int32_t *) &comet->mdiag, 0x00);
 363
 364     /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted  */
 365     /* Store is enabled. */
 366
 367     WrtXmtWaveformTbl (ci, comet, TWV_table[tix]);
 368     if (isT1mode)
 369         WrtRcvEqualizerTbl ((ci_t *) ci, comet, &T1_Equalizer[0]);
 370     else
 371         WrtRcvEqualizerTbl ((ci_t *) ci, comet, &E1_Equalizer[0]);
 372     SetPwrLevel (comet);
 373 }
 374
 375 /*
 376 ** Name:        WrtXmtWaveform
 377 ** Description: Formulate the Data for the Pulse Waveform Storage
 378 **                Write register, (F2), from the sample and unit inputs.
 379 **                Write the data to the Pulse Waveform Storage Data register.
 380 ** Returns:     Nothing
 381 */
 382 STATIC void
 383 WrtXmtWaveform (ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
 384 {
 385     u_int8_t    WaveformAddr;
 386
 387     WaveformAddr = (sample << 3) + (unit & 7);
 388     pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
 389     pci_flush_write (ci);           /* for write order preservation when
 390                                      * Optimizing driver */
 391     pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
 392 }
 393
 394 /*
 395 ** Name:        WrtXmtWaveformTbl
 396 ** Description: Fill in the Transmit Waveform Values
 397 **                for driving the transmitter DAC.
 398 ** Returns:     Nothing
 399 */
 400 STATIC void
 401 WrtXmtWaveformTbl (ci_t * ci, comet_t * comet,
 402                    u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
 403 {
 404     u_int32_t sample, unit;
 405
 406     for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
 407     {
 408         for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 409             WrtXmtWaveform (ci, comet, sample, unit, table[sample][unit]);
 410     }
 411
 412     /* Enable transmitter and set output amplitude */
 413     pci_write_32 ((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
 414 }
 415
 416
 417 /*
 418 ** Name:        WrtXmtWaveform
 419 ** Description: Fill in the Receive Equalizer RAM from the desired
 420 **                table.
 421 ** Returns:     Nothing
 422 **
 423 ** Remarks:  Per PM4351 Device Errata, Receive Equalizer RAM Initialization
 424 **           is coded with early setup of indirect address.
 425 */
 426
 427 STATIC void
 428 WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table)
 429 {
 430     u_int32_t   ramaddr;
 431     volatile u_int32_t value;
 432
 433     for (ramaddr = 0; ramaddr < 256; ramaddr++)
 434     {
 435         /*** the following lines are per Errata 7, 2.5 ***/
 436         {
 437             pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);   /* Set up for a read
 438                                                                          * operation */
 439             pci_flush_write (ci);   /* for write order preservation when
 440                                      * Optimizing driver */
 441             pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr,
 442                                                                                   * initiate a read */
 443             pci_flush_write (ci);   /* for write order preservation when
 444                                      * Optimizing driver */
 445             /*
 446              * wait 3 line rate clock cycles to ensure address bits are
 447              * captured by T1/E1 clock
 448              */
 449             OS_uwait (4, "wret");   /* 683ns * 3 = 1366 ns, approx 2us (but
 450                                      * use 4us) */
 451         }
 452
 453         value = *table++;
 454         pci_write_32 ((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
 455         pci_write_32 ((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
 456         pci_write_32 ((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
 457         pci_write_32 ((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 458         pci_flush_write (ci);       /* for write order preservation when
 459                                      * Optimizing driver */
 460
 461         /* Storing RAM address, causes RAM to be updated */
 462
 463         pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0);  /* Set up for a write
 464                                                                  * operation */
 465         pci_flush_write (ci);       /* for write order preservation when
 466                                      * Optimizing driver */
 467         pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr,
 468                                                                                  * initiate a read */
 469         pci_flush_write (ci);       /* for write order preservation when
 470                                      * Optimizing driver */
 471         /*
 472          * wait 3 line rate clock cycles to ensure address bits are captured
 473          * by T1/E1 clock
 474          */
 475         OS_uwait (4, "wret");       /* 683ns * 3 = 1366 ns, approx 2us (but
 476                                      * use 4us) */
 477     }
 478
 479     pci_write_32 ((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);     /* Enable Equalizer &
 480                                                                  * set it to use 256
 481                                                                  * periods */
 482 }
 483
 484
 485 /*
 486 ** Name:        SetPwrLevel
 487 ** Description: Implement power level setting algorithm described below
 488 ** Returns:     Nothing
 489 */
 490
 491 STATIC void
 492 SetPwrLevel (comet_t * comet)
 493 {
 494     volatile u_int32_t temp;
 495
 496 /*
 497 **    Algorithm to Balance the Power Distribution of Ttip Tring
 498 **
 499 **    Zero register F6
 500 **    Write 0x01 to register F4
 501 **    Write another 0x01 to register F4
 502 **    Read register F4
 503 **    Remove the 0x01 bit by Anding register F4 with 0xFE
 504 **    Write the resultant value to register F4
 505 **    Repeat these steps for register F5
 506 **    Write 0x01 to register F6
 507 */
 508     pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);  /* XLPG Fuse Data Select */
 509
 510     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test
 511                                                                  * Positive control */
 512     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 513
 514     temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
 515     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, temp);
 516
 517     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test
 518                                                                  * Negative control */
 519     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 520
 521     temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
 522     pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, temp);
 523     pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);  /* XLPG */
 524 }
 525
 526
 527 /*
 528 ** Name:        SetCometOps
 529 ** Description: Set up the selected Comet's clock edge drive for both
 530 **                the transmit out the analog side and receive to the
 531 **                backplane side.
 532 ** Returns:     Nothing
 533 */
 534 #if 0
 535 STATIC void
 536 SetCometOps (comet_t * comet)
 537 {
 538     volatile u_int8_t rd_value;
 539
 540     if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
 541     {
 542         rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg);     /* read the BRIF
 543                                                                                  * Configuration */
 544         rd_value &= ~0x20;
 545         pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 546
 547         rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg);   /* read the BRIF Frame
 548                                                                                  * Pulse Configuration */
 549         rd_value &= ~0x20;
 550         pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
 551     } else
 552     {
 553         rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg);     /* read the BRIF
 554                                                                                  * Configuration */
 555         rd_value |= 0x20;
 556         pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 557
 558         rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg);   /* read the BRIF Frame
 559                                                                                  * Pulse Configuration */
 560         rd_value |= 0x20;
 561         pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
 562     }
 563 }
 564 #endif
 565
 566 /***  End-of-File  ***/