drivers/staging/cxt1e1/comet.c

   1 /* Copyright (C) 2003-2005  SBE, Inc.
   2  *
   3  *   This program is free software; you can redistribute it and/or modify
   4  *   it under the terms of the GNU General Public License as published by
   5  *   the Free Software Foundation; either version 2 of the License, or
   6  *   (at your option) any later version.
   7  *
   8  *   This program is distributed in the hope that it will be useful,
   9  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *   GNU General Public License for more details.
  12  */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/io.h>
  17 #include <linux/hdlc.h>
  18 #include "pmcc4_sysdep.h"
  19 #include "sbecom_inline_linux.h"
  20 #include "libsbew.h"
  21 #include "pmcc4.h"
  22 #include "comet.h"
  23 #include "comet_tables.h"
  24
  25 extern int  cxt1e1_log_level;
  26
  27 #define COMET_NUM_SAMPLES   24  /* Number of entries in the waveform table */
  28 #define COMET_NUM_UNITS     5   /* Number of points per entry in table */
  29
  30 /* forward references */
  31 static void SetPwrLevel(struct s_comet_reg *comet);
  32 static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table);
  33 static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
  34
  35
  36 void       *TWV_table[12] = {
  37         TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
  38         TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
  39         TWVShortHaul4, TWVShortHaul5,
  40         /** PORT POINT - 75 Ohm not supported **/
  41         TWV_E1_75Ohm,
  42         TWV_E1_120Ohm
  43 };
  44
  45
  46 static int
  47 lbo_tbl_lkup(int t1, int lbo) {
  48         /* error switches to default */
  49         if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
  50                 if (t1)
  51                         /* default T1 waveform table */
  52                         lbo = CFG_LBO_LH0;
  53                 else
  54                         /* default E1 waveform table */
  55                         lbo = CFG_LBO_E120;
  56         }
  57         /* make index ZERO relative */
  58         return lbo - 1;
  59 }
  60
  61 void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode, int clockmaster,
  62                 u_int8_t moreParams)
  63 {
  64         u_int8_t isT1mode;
  65         /* T1 default */
  66         u_int8_t    tix = CFG_LBO_LH0;
  67         isT1mode = IS_FRAME_ANY_T1(port_mode);
  68         /* T1 or E1 */
  69         if (isT1mode) {
  70                 /* Select T1 Mode & PIO output enabled */
  71                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
  72                 /* default T1 waveform table */
  73                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
  74         } else {
  75                 /* Select E1 Mode & PIO output enabled */
  76                 pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
  77                 /* default E1 waveform table */
  78                 tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
  79         }
  80
  81         if (moreParams & CFG_LBO_MASK)
  82                 /* dial-in requested waveform table */
  83                 tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
  84         /* Tx line Intfc cfg Set for analog & no special patterns */
  85         /* Transmit Line Interface Config. */
  86         pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
  87         /* master test Ignore Test settings for now */
  88         /* making sure it's Default value */
  89         pci_write_32((u_int32_t *) &comet->mtest, 0x00);
  90         /* Turn on Center (CENT) and everything else off */
  91         /* RJAT cfg */
  92         pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
  93         /* Set Jitter Attenuation to recommend T1 values */
  94         if (isT1mode) {
  95                 /* RJAT Divider N1 Control */
  96                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
  97                 /* RJAT Divider N2 Control */
  98                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
  99         } else {
 100                 /* RJAT Divider N1 Control */
 101                 pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
 102                 /* RJAT Divider N2 Control */
 103                 pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
 104         }
 105
 106         /* Turn on Center (CENT) and everything else off */
 107         /* TJAT Config. */
 108         pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
 109
 110         /* Do not bypass jitter attenuation and bypass elastic store */
 111         /* rx opts */
 112         pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
 113
 114         /* TJAT ctrl & TJAT divider ctrl */
 115         /* Set Jitter Attenuation to recommended T1 values */
 116         if (isT1mode) {
 117                 /* TJAT Divider N1 Control */
 118                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
 119                 /* TJAT Divider N2  Control */
 120                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
 121         } else {
 122                 /* TJAT Divider N1 Control */
 123                 pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
 124                 /* TJAT Divider N2 Control */
 125                 pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
 126         }
 127
 128         /* 1c: rx ELST cfg   20: tx ELST cfg  28&38: rx&tx data link ctrl */
 129
 130         /* Select 193-bit frame format */
 131         if (isT1mode) {
 132                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
 133                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
 134         } else {
 135                 /* Select 256-bit frame format */
 136                 pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
 137                 pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
 138                 /* disable T1 data link receive */
 139                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
 140                 /* disable T1 data link transmit */
 141                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
 142         }
 143
 144     /* the following is a default value */
 145     /* Enable 8 out of 10 validation */
 146          /* t1RBOC enable(BOC:BitOriented Code) */
 147         pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
 148         if (isT1mode) {
 149                 /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
 150                 /* 6 bit down, 5 bit up (assert) */
 151                 pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
 152                 /* line loopback activate pattern */
 153                 pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
 154                 /* deactivate code pattern (i.e.001) */
 155                 pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
 156         }
 157     /* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg  */
 158     /* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg  */
 159     /* 60: t1 ALMI cfg */
 160     /* Configure Line Coding */
 161
 162         switch (port_mode) {
 163         /* 1 - T1 B8ZS */
 164         case CFG_FRAME_SF:
 165                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 166                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 167                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 168                 /* 5:B8ZS */
 169                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
 170                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 171                 break;
 172         /* 2 - T1 B8ZS */
 173         case CFG_FRAME_ESF:
 174                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 175                 /* Bit 5: T1 DataLink Enable */
 176                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 177                 /* 5: T1 DataLink Enable */
 178                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 179                 /* 4:ESF  5:ESFFA */
 180                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 181                 /* 2:ESF */
 182                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 183                 /* 4:ESF  5:B8ZS */
 184                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
 185                 /* 4:ESF */
 186                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 187                 break;
 188         /* 3 - HDB3 */
 189         case CFG_FRAME_E1PLAIN:
 190                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 191                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 192                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
 193                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 194                 break;
 195         /* 4 - HDB3 */
 196         case CFG_FRAME_E1CAS:
 197                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 198                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 199                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
 200                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 201                 break;
 202         /* 5 - HDB3 */
 203         case CFG_FRAME_E1CRC:
 204                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 205                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 206                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
 207                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 208                 break;
 209         /* 6 - HDB3 */
 210         case CFG_FRAME_E1CRC_CAS:
 211                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
 212                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 213                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
 214                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 215                 break;
 216         /* 7 - T1 AMI */
 217         case CFG_FRAME_SF_AMI:
 218                 /* Enable AMI Line Decoding */
 219                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 220                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
 221                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
 222                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
 223                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 224                 break;
 225         /* 8 - T1 AMI */
 226         case CFG_FRAME_ESF_AMI:
 227                 /* Enable AMI Line Decoding */
 228                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 229                 /* 5: T1 DataLink Enable */
 230                 pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
 231                 /* 5: T1 DataLink Enable */
 232                 pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
 233                 /* Bit 4:ESF  5:ESFFA */
 234                 pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
 235                 /* 2:ESF */
 236                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
 237                 /* 4:ESF */
 238                 pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
 239                 /* 4:ESF */
 240                 pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
 241                 break;
 242         /* 9 - AMI */
 243         case CFG_FRAME_E1PLAIN_AMI:
 244                 /* Enable AMI Line Decoding */
 245                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 246                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 247                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
 248                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
 249                 break;
 250         /* 10 - AMI */
 251         case CFG_FRAME_E1CAS_AMI:
 252                 /* Enable AMI Line Decoding */
 253                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 254                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 255                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
 256                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
 257                 break;
 258         /* 11 - AMI */
 259         case CFG_FRAME_E1CRC_AMI:
 260                 /* Enable AMI Line Decoding */
 261                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 262                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 263                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
 264                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
 265                 break;
 266         /* 12 - AMI */
 267         case CFG_FRAME_E1CRC_CAS_AMI:
 268                 /* Enable AMI Line Decoding */
 269                 pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
 270                 pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
 271                 pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
 272                 pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
 273                 break;
 274         }       /* end switch */
 275
 276     /***
 277      * Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
 278      * CMODE=1: Clock slave mode with BRCLK as an input,
 279      * DE=0: Use falling edge of BRCLK for data,
 280      * FE=0: Use falling edge of BRCLK for frame,
 281      * CMS=0: Use backplane freq,
 282      * RATE[1:0]=0,0: T1
 283      ***/
 284
 285
 286     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
 287     /* note "rate bits can only be set once after reset" */
 288         if (clockmaster) {
 289                 /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
 290                 /* rate = 1.544 Mb/s */
 291                 if (isT1mode)
 292                         /* Comet 0 Master Mode(CMODE=0) */
 293                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
 294                 /* rate = 2.048 Mb/s */
 295                 else
 296                         /* Comet 0 Master Mode(CMODE=0) */
 297                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
 298
 299                 /* 31: BRIF frame pulse cfg  06: tx timing options */
 300
 301                 /* Master Mode i.e.FPMODE=0 (@0x20) */
 302                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
 303                 if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
 304                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 305                                 pr_info(">> %s: clockmaster internal clock\n",
 306                                         __func__);
 307                         /* internal oscillator */
 308                         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 309                 } else {
 310                         /* external clock source */
 311                         if (cxt1e1_log_level >= LOG_SBEBUG12)
 312                                 pr_info(">> %s: clockmaster external clock\n",
 313                                         __func__);
 314                         /* loop timing(external) */
 315                         pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
 316                 }
 317
 318         } else  {
 319                 /* slave */
 320                 if (isT1mode)
 321                         /* Slave Mode(CMODE=1, see above) */
 322                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
 323                 else
 324                         /* Slave Mode(CMODE=1)*/
 325                         pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
 326                 /* Slave Mode i.e. FPMODE=1 (@0x20) */
 327                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
 328         if (cxt1e1_log_level >= LOG_SBEBUG12)
 329                 pr_info(">> %s: clockslave internal clock\n", __func__);
 330         /* oscillator timing */
 331         pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 332         }
 333
 334         /* 32: BRIF parity F-bit cfg */
 335         /* Totem-pole operation */
 336         /* Receive Backplane Parity/F-bit */
 337         pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
 338
 339     /* dc: RLPS equalizer V ref */
 340     /* Configuration */
 341         if (isT1mode)
 342                 /* RLPS Equalizer Voltage  */
 343                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
 344         else
 345                 /* RLPS Equalizer Voltage  */
 346                 pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
 347
 348     /* Reserved bit set and SQUELCH enabled */
 349     /* f8: RLPS cfg & status  f9: RLPS ALOS detect/clear threshold */
 350         /* RLPS Configuration Status */
 351         pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
 352         if (isT1mode)
 353                 /* ? */
 354                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
 355         else
 356                 /* ? */
 357                 pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
 358
 359
 360     /* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
 361     /* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
 362     /* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
 363     /* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
 364     /***    Transmit side is always an Input, Slave Clock*/
 365     /* 40: BTIF cfg  41: loop timing(external) */
 366         /*BTIF frame pulse cfg */
 367         if (isT1mode)
 368                 /* BTIF Configuration  Reg. */
 369                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
 370         else
 371                 /* BTIF Configuration  Reg. */
 372                 pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
 373         /* BTIF Frame Pulse Config. */
 374         pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
 375
 376     /* 0a: master diag  06: tx timing options */
 377     /* if set Comet to loop back */
 378
 379     /* Comets set to normal */
 380         pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
 381
 382     /* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted  */
 383     /* Store is enabled. */
 384
 385         WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
 386         if (isT1mode)
 387                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
 388         else
 389                 WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
 390         SetPwrLevel(comet);
 391 }
 392
 393 /*
 394 ** Name:        WrtXmtWaveform
 395 ** Description: Formulate the Data for the Pulse Waveform Storage
 396 **                Write register, (F2), from the sample and unit inputs.
 397 **                Write the data to the Pulse Waveform Storage Data register.
 398 ** Returns:     Nothing
 399 */
 400 static void
 401 WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
 402 {
 403         u_int8_t    WaveformAddr;
 404
 405         WaveformAddr = (sample << 3) + (unit & 7);
 406         pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
 407         /* for write order preservation when Optimizing driver */
 408         pci_flush_write(ci);
 409         pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
 410 }
 411
 412 /*
 413 ** Name:        WrtXmtWaveformTbl
 414 ** Description: Fill in the Transmit Waveform Values
 415 **                for driving the transmitter DAC.
 416 ** Returns:     Nothing
 417 */
 418 static void
 419 WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
 420                   u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
 421 {
 422         u_int32_t sample, unit;
 423
 424         for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
 425                 for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 426                         WrtXmtWaveform(ci, comet, sample, unit,
 427                                         table[sample][unit]);
 428                 }
 429
 430     /* Enable transmitter and set output amplitude */
 431         pci_write_32((u_int32_t *) &comet->xlpg_cfg,
 432                         table[COMET_NUM_SAMPLES][0]);
 433 }
 434
 435
 436 /*
 437 ** Name:        WrtXmtWaveform
 438 ** Description: Fill in the Receive Equalizer RAM from the desired
 439 **                table.
 440 ** Returns:     Nothing
 441 **
 442 ** Remarks:  Per PM4351 Device Errata, Receive Equalizer RAM Initialization
 443 **           is coded with early setup of indirect address.
 444 */
 445
 446 static void
 447 WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
 448 {
 449         u_int32_t   ramaddr;
 450         volatile u_int32_t value;
 451
 452         for (ramaddr = 0; ramaddr < 256; ramaddr++) {
 453                 /*** the following lines are per Errata 7, 2.5 ***/
 454                 {
 455                 /* Set up for a read operation */
 456                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
 457                 /* for write order preservation when Optimizing driver */
 458                 pci_flush_write(ci);
 459                 /* write the addr, initiate a read */
 460                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 461                                 (u_int8_t) ramaddr);
 462                 /* for write order preservation when Optimizing driver */
 463                 pci_flush_write(ci);
 464                 /*
 465                 * wait 3 line rate clock cycles to ensure address bits are
 466                 * captured by T1/E1 clock
 467                 */
 468
 469                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 470                 OS_uwait(4, "wret");
 471         }
 472
 473         value = *table++;
 474         pci_write_32((u_int32_t *) &comet->rlps_idata3,
 475                         (u_int8_t) (value >> 24));
 476         pci_write_32((u_int32_t *) &comet->rlps_idata2,
 477                         (u_int8_t) (value >> 16));
 478         pci_write_32((u_int32_t *) &comet->rlps_idata1,
 479                         (u_int8_t) (value >> 8));
 480         pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 481          /* for write order preservation when Optimizing driver */
 482         pci_flush_write(ci);
 483
 484         /* Storing RAM address, causes RAM to be updated */
 485
 486                 /* Set up for a write operation */
 487                 pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
 488                 /* for write order preservation when optimizing driver */
 489                 pci_flush_write(ci);
 490                 /* write the addr, initiate a read */
 491                 pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
 492                                 (u_int8_t) ramaddr);
 493                  /* for write order preservation when optimizing driver */
 494                 pci_flush_write(ci);
 495
 496         /*
 497         * wait 3 line rate clock cycles to ensure address bits are captured
 498         * by T1/E1 clock
 499         */
 500                 /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
 501                 OS_uwait(4, "wret");
 502         }
 503
 504         /* Enable Equalizer & set it to use 256 periods */
 505         pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
 506 }
 507
 508
 509 /*
 510 ** Name:        SetPwrLevel
 511 ** Description: Implement power level setting algorithm described below
 512 ** Returns:     Nothing
 513 */
 514
 515 static void
 516 SetPwrLevel(struct s_comet_reg *comet)
 517 {
 518         volatile u_int32_t temp;
 519
 520 /*
 521 **    Algorithm to Balance the Power Distribution of Ttip Tring
 522 **
 523 **    Zero register F6
 524 **    Write 0x01 to register F4
 525 **    Write another 0x01 to register F4
 526 **    Read register F4
 527 **    Remove the 0x01 bit by Anding register F4 with 0xFE
 528 **    Write the resultant value to register F4
 529 **    Repeat these steps for register F5
 530 **    Write 0x01 to register F6
 531 */
 532         /* XLPG Fuse Data Select */
 533         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
 534         /* XLPG Analog Test Positive control */
 535         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 536         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
 537         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
 538         pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
 539         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 540         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
 541         /* XLPG Analog Test Negative control */
 542         temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
 543         pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
 544         /* XLPG */
 545         pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
 546 }
 547
 548
 549 /*
 550 ** Name:        SetCometOps
 551 ** Description: Set up the selected Comet's clock edge drive for both
 552 **                the transmit out the analog side and receive to the
 553 **                backplane side.
 554 ** Returns:     Nothing
 555 */
 556 #if 0
 557 static void
 558 SetCometOps(struct s_comet_reg *comet)
 559 {
 560         volatile u_int8_t rd_value;
 561
 562         if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
 563                 /* read the BRIF Configuration */
 564                 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 565                 rd_value &= ~0x20;
 566                 pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 567                 /* read the BRIF Frame Pulse Configuration */
 568                 rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 569                 rd_value &= ~0x20;
 570                 pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
 571         } else {
 572         /* read the BRIF Configuration */
 573         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 574         rd_value |= 0x20;
 575         pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
 576         /* read the BRIF Frame Pulse Configuration */
 577         rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
 578         rd_value |= 0x20;
 579         pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
 580         }
 581 }
 582 #endif
 583
 584 /***  End-of-File  ***/