1 /* Copyright (C) 2003-2005 SBE, Inc.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 #include <linux/slab.h>
18 #include <asm/byteorder.h>
19 #include <linux/netdevice.h>
20 #include <linux/delay.h>
21 #include <linux/hdlc.h>
22 #include "pmcc4_sysdep.h"
23 #include "sbecom_inline_linux.h"
28 #ifndef USE_MAX_INT_DELAY
33 extern int drvr_state;
38 pci_read_32(u_int32_t *p)
45 if (cxt1e1_log_level >= LOG_DEBUG)
46 pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
49 FLUSH_PCI_READ(); /* */
50 return le32_to_cpu(*p);
55 pci_write_32(u_int32_t *p, u_int32_t v)
58 if (cxt1e1_log_level >= LOG_DEBUG)
59 pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
62 FLUSH_PCI_WRITE(); /* This routine is called from routines
63 * which do multiple register writes
64 * which themselves need flushing between
65 * writes in order to guarantee write
66 * ordering. It is less code-cumbersome
67 * to flush here-in then to investigate
68 * and code the many other register
69 * writing routines. */
75 pci_flush_write(ci_t *ci)
79 /* issue a PCI read to flush PCI write thru bridge */
80 v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
83 * return nothing, this just reads PCI bridge interface to flush
84 * previously written data
90 watchdog_func(unsigned long arg)
92 struct watchdog *wd = (void *) arg;
94 if (drvr_state != SBE_DRVR_AVAILABLE) {
95 if (cxt1e1_log_level >= LOG_MONITOR)
96 pr_warning("%s: drvr not available (%x)\n",
97 __func__, drvr_state);
100 schedule_work(&wd->work);
101 mod_timer(&wd->h, jiffies + wd->ticks);
104 int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *),
109 wdp->ticks = (HZ) * (usec / 1000) / 1000;
110 INIT_WORK(&wdp->work, (void *)f);
113 ci_t *ci = (ci_t *) c;
115 wdp->h.data = (unsigned long) &ci->wd;
117 wdp->h.function = watchdog_func;
122 OS_uwait(int usec, char *description)
128 /* now delay residual */
129 tmp = (usec / 1000) * 1000; /* round */
130 tmp = usec - tmp; /* residual */
131 if (tmp) { /* wait on residual */
139 /* dummy short delay routine called as a subroutine so that compiler
140 * does not optimize/remove its intent (a short delay)
146 #ifndef USE_MAX_INT_DELAY
155 OS_sem_init(void *sem, int state)
159 sema_init((struct semaphore *) sem, 0);
162 sema_init((struct semaphore *) sem, 1);
164 default: /* otherwise, set sem.count to state's
166 sema_init(sem, state);
173 sd_line_is_ok(void *user)
175 struct net_device *ndev = (struct net_device *) user;
177 return netif_carrier_ok(ndev);
181 sd_line_is_up(void *user)
183 struct net_device *ndev = (struct net_device *) user;
185 netif_carrier_on(ndev);
190 sd_line_is_down(void *user)
192 struct net_device *ndev = (struct net_device *) user;
194 netif_carrier_off(ndev);
199 sd_disable_xmit(void *user)
201 struct net_device *dev = (struct net_device *) user;
203 netif_stop_queue(dev);
208 sd_enable_xmit(void *user)
210 struct net_device *dev = (struct net_device *) user;
212 netif_wake_queue(dev);
217 sd_queue_stopped(void *user)
219 struct net_device *ndev = (struct net_device *) user;
221 return netif_queue_stopped(ndev);
224 void sd_recv_consume(void *token, size_t len, void *user)
226 struct net_device *ndev = user;
227 struct sk_buff *skb = token;
231 skb->protocol = hdlc_type_trans(skb, ndev);
237 ** Read some reserved location w/in the COMET chip as a usable
238 ** VMETRO trigger point or other trace marking event.
243 extern ci_t *CI; /* dummy pointer to board ZERO's data */
245 VMETRO_TRIGGER(ci_t *ci, int x)
247 struct s_comet_reg *comet;
248 volatile u_int32_t data;
250 comet = ci->port[0].cometbase; /* default to COMET # 0 */
255 data = pci_read_32((u_int32_t *) &comet->__res24); /* 0x90 */
258 data = pci_read_32((u_int32_t *) &comet->__res25); /* 0x94 */
261 data = pci_read_32((u_int32_t *) &comet->__res26); /* 0x98 */
264 data = pci_read_32((u_int32_t *) &comet->__res27); /* 0x9C */
267 data = pci_read_32((u_int32_t *) &comet->__res88); /* 0x220 */
270 data = pci_read_32((u_int32_t *) &comet->__res89); /* 0x224 */
273 data = pci_read_32((u_int32_t *) &comet->__res8A); /* 0x228 */
276 data = pci_read_32((u_int32_t *) &comet->__res8B); /* 0x22C */
279 data = pci_read_32((u_int32_t *) &comet->__resA0); /* 0x280 */
282 data = pci_read_32((u_int32_t *) &comet->__resA1); /* 0x284 */
285 data = pci_read_32((u_int32_t *) &comet->__resA2); /* 0x288 */
288 data = pci_read_32((u_int32_t *) &comet->__resA3); /* 0x28C */
291 data = pci_read_32((u_int32_t *) &comet->__resA4); /* 0x290 */
294 data = pci_read_32((u_int32_t *) &comet->__resA5); /* 0x294 */
297 data = pci_read_32((u_int32_t *) &comet->__resA6); /* 0x298 */
300 data = pci_read_32((u_int32_t *) &comet->__resA7); /* 0x29C */
303 data = pci_read_32((u_int32_t *) &comet->__res74); /* 0x1D0 */
306 data = pci_read_32((u_int32_t *) &comet->__res75); /* 0x1D4 */
309 data = pci_read_32((u_int32_t *) &comet->__res76); /* 0x1D8 */
312 data = pci_read_32((u_int32_t *) &comet->__res77); /* 0x1DC */
318 /*** End-of-File ***/