1 /*-----------------------------------------------------------------------------
4 * Copyright (C) 2007 One Stop Systems, Inc.
5 * Copyright (C) 2002-2006 SBE, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * For further information, contact via email: support@onestopsystems.com
18 * One Stop Systems, Inc. Escondido, California U.S.A.
19 *-----------------------------------------------------------------------------
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/types.h>
25 #include "pmcc4_sysdep.h"
26 #include <linux/errno.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h> /* include for timer */
29 #include <linux/timer.h> /* include for timer */
30 #include <linux/hdlc.h>
33 #include "sbecom_inline_linux.h"
35 #include "pmcc4_private.h"
37 #include "pmcc4_ioctls.h"
42 #define KERN_WARN KERN_WARNING
44 /* forward references */
45 status_t c4_wk_chan_init (mpi_t *, mch_t *);
46 void c4_wq_port_cleanup (mpi_t *);
47 status_t c4_wq_port_init (mpi_t *);
49 int c4_loop_port (ci_t *, int, u_int8_t);
50 status_t c4_set_port (ci_t *, int);
51 status_t musycc_chan_down (ci_t *, int);
53 u_int32_t musycc_chan_proto (int);
54 status_t musycc_dump_ring (ci_t *, unsigned int);
55 status_t __init musycc_init (ci_t *);
56 void musycc_init_mdt (mpi_t *);
57 void musycc_serv_req (mpi_t *, u_int32_t);
58 void musycc_update_timeslots (mpi_t *);
60 extern void musycc_update_tx_thp (mch_t *);
61 extern int cxt1e1_log_level;
62 extern int cxt1e1_max_mru;
63 extern int cxt1e1_max_mtu;
64 extern int max_rxdesc_used, max_rxdesc_default;
65 extern int max_txdesc_used, max_txdesc_default;
67 #if defined (__powerpc__)
68 extern void *memset (void *s, int c, size_t n);
72 int drvr_state = SBE_DRVR_INIT;
74 ci_t *CI; /* dummy pointer to board ZEROE's data -
79 sbecom_set_loglevel (int d)
82 * The code within the following -if- clause is a backdoor debug facility
83 * which can be used to display the state of a board's channel.
87 unsigned int channum = d - (LOG_DEBUG + 1); /* convert to ZERO
90 (void) musycc_dump_ring ((ci_t *) CI, channum); /* CI implies support
94 if (cxt1e1_log_level != d)
96 pr_info("log level changed from %d to %d\n", cxt1e1_log_level, d);
97 cxt1e1_log_level = d; /* set new */
99 pr_info("log level is %d\n", cxt1e1_log_level);
105 c4_find_chan (int channum)
111 for (ci = c4_list; ci; ci = ci->next)
112 for (portnum = 0; portnum < ci->max_port; portnum++)
113 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
115 ch = ci->port[portnum].chan[gchan];
117 if ((ch->state != UNASSIGNED) &&
118 (ch->channum == channum))
126 * Check port state and set LED states using watchdog or ioctl...
127 * also check for in-band SF loopback commands (& cause results if they are there)
129 * Alarm function depends on comet bits indicating change in
130 * link status (linkMask) to keep the link status indication straight.
132 * Indications are only LED and system log -- except when ioctl is invoked.
134 * "alarmed" record (a.k.a. copyVal, in some cases below) decodes as:
136 * RMAI (E1 only) 0x100
139 * link returned 0x20 (link was down, now it's back and 'port get' hasn't run)
140 * change in LED 0x10 (update LED register because value has changed)
146 * note "link has returned" indication is reset on read
147 * (e.g. by use of the c4_control port get command)
150 #define sbeLinkMask 0x41 /* change in signal status (lost/recovered) +
152 #define sbeLinkChange 0x40
153 #define sbeLinkDown 0x01
154 #define sbeAlarmsMask 0x07 /* red / yellow / blue alarm conditions */
155 #define sbeE1AlarmsMask 0x107 /* alarm conditions */
157 #define COMET_LBCMD_READ 0x80 /* read only (do not set, return read value) */
160 checkPorts (ci_t *ci)
162 #ifndef CONFIG_SBE_PMCC4_NCOMM
164 * PORT POINT - NCOMM needs to avoid this code since the polling of
165 * alarms conflicts with NCOMM's interrupt servicing implementation.
168 struct s_comet_reg *comet;
169 volatile u_int32_t value;
170 u_int32_t copyVal, LEDval;
175 for (portnum = 0; portnum < ci->max_port; portnum++)
177 copyVal = 0x12f & (ci->alarmed[portnum]); /* port's alarm record */
178 comet = ci->port[portnum].cometbase;
179 value = pci_read_32 ((u_int32_t *) &comet->cdrc_ists) & sbeLinkMask; /* link loss reg */
181 if (value & sbeLinkChange) /* is there a change in the link stuff */
183 /* if there's been a change (above) and yet it's the same (below) */
184 if (!(((copyVal >> 3) & sbeLinkDown) ^ (value & sbeLinkDown)))
186 if (value & sbeLinkDown)
187 pr_warning("%s: Port %d momentarily recovered.\n",
188 ci->devname, portnum);
190 pr_warning("%s: Warning: Port %d link was briefly down.\n",
191 ci->devname, portnum);
192 } else if (value & sbeLinkDown)
193 pr_warning("%s: Warning: Port %d link is down.\n",
194 ci->devname, portnum);
197 pr_warning("%s: Port %d link has recovered.\n",
198 ci->devname, portnum);
199 copyVal |= 0x20; /* record link transition to up */
201 copyVal |= 0x10; /* change (link) --> update LEDs */
203 copyVal &= 0x137; /* clear LED & link old history bits &
205 if (value & sbeLinkDown)
206 copyVal |= 0x08; /* record link status (now) */
208 { /* if link is up, do this */
209 copyVal |= 0x40; /* LED indicate link is up */
210 /* Alarm things & the like ... first if E1, then if T1 */
211 if (IS_FRAME_ANY_E1 (ci->port[portnum].p.port_mode))
214 * first check Codeword (SaX) changes & CRC and
215 * sub-multi-frame errors
218 * note these errors are printed every time they are detected
221 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_nat_ists); /* codeword */
223 { /* if errors (crc or smf only) */
225 pr_warning("%s: E1 Port %d Codeword Sa4 change detected.\n",
226 ci->devname, portnum);
228 pr_warning("%s: E1 Port %d Codeword Sa5 change detected.\n",
229 ci->devname, portnum);
231 pr_warning("%s: E1 Port %d Codeword Sa6 change detected.\n",
232 ci->devname, portnum);
234 pr_warning("%s: E1 Port %d Codeword Sa7 change detected.\n",
235 ci->devname, portnum);
237 pr_warning("%s: E1 Port %d Codeword Sa8 change detected.\n",
238 ci->devname, portnum);
240 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_mists); /* crc & smf */
242 { /* if errors (crc or smf only) */
243 if (value & sbeE1CRC)
244 pr_warning("%s: E1 Port %d CRC-4 error(s) detected.\n",
245 ci->devname, portnum);
246 if (value & sbeE1errSMF) /* error in sub-multiframe */
247 pr_warning("%s: E1 Port %d received errored SMF.\n",
248 ci->devname, portnum);
250 value = pci_read_32 ((u_int32_t *) &comet->e1_frmr_masts) & 0xcc; /* alarms */
252 * pack alarms together (bitmiser), and construct similar to
255 /* RAI,RMAI,.,.,LOF,AIS,.,. ==> RMAI,.,.,.,.,.,RAI,LOF,AIS */
257 value = (value >> 2);
261 value |= 0x40; /* RAI */
263 value |= 0x100; /* RMAI */
265 } /* finished packing alarm in handy order */
266 if (value != (copyVal & sbeE1AlarmsMask))
267 { /* if alarms changed */
268 copyVal |= 0x10;/* change LED status */
269 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
271 copyVal &= ~sbeRedAlm;
272 pr_warning("%s: E1 Port %d LOF alarm ended.\n",
273 ci->devname, portnum);
274 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
276 copyVal |= sbeRedAlm;
277 pr_warning("%s: E1 Warning: Port %d LOF alarm.\n",
278 ci->devname, portnum);
279 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
281 copyVal &= ~sbeYelAlm;
282 pr_warning("%s: E1 Port %d RAI alarm ended.\n",
283 ci->devname, portnum);
284 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
286 copyVal |= sbeYelAlm;
287 pr_warning("%s: E1 Warning: Port %d RAI alarm.\n",
288 ci->devname, portnum);
289 } else if ((copyVal & sbeE1RMAI) && !(value & sbeE1RMAI))
291 copyVal &= ~sbeE1RMAI;
292 pr_warning("%s: E1 Port %d RMAI alarm ended.\n",
293 ci->devname, portnum);
294 } else if (!(copyVal & sbeE1RMAI) && (value & sbeE1RMAI))
296 copyVal |= sbeE1RMAI;
297 pr_warning("%s: E1 Warning: Port %d RMAI alarm.\n",
298 ci->devname, portnum);
299 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
301 copyVal &= ~sbeAISAlm;
302 pr_warning("%s: E1 Port %d AIS alarm ended.\n",
303 ci->devname, portnum);
304 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
306 copyVal |= sbeAISAlm;
307 pr_warning("%s: E1 Warning: Port %d AIS alarm.\n",
308 ci->devname, portnum);
311 /* end of E1 alarm code */
314 value = pci_read_32 ((u_int32_t *) &comet->t1_almi_ists); /* alarms */
315 value &= sbeAlarmsMask;
316 if (value != (copyVal & sbeAlarmsMask))
317 { /* if alarms changed */
318 copyVal |= 0x10;/* change LED status */
319 if ((copyVal & sbeRedAlm) && !(value & sbeRedAlm))
321 copyVal &= ~sbeRedAlm;
322 pr_warning("%s: Port %d red alarm ended.\n",
323 ci->devname, portnum);
324 } else if (!(copyVal & sbeRedAlm) && (value & sbeRedAlm))
326 copyVal |= sbeRedAlm;
327 pr_warning("%s: Warning: Port %d red alarm.\n",
328 ci->devname, portnum);
329 } else if ((copyVal & sbeYelAlm) && !(value & sbeYelAlm))
331 copyVal &= ~sbeYelAlm;
332 pr_warning("%s: Port %d yellow (RAI) alarm ended.\n",
333 ci->devname, portnum);
334 } else if (!(copyVal & sbeYelAlm) && (value & sbeYelAlm))
336 copyVal |= sbeYelAlm;
337 pr_warning("%s: Warning: Port %d yellow (RAI) alarm.\n",
338 ci->devname, portnum);
339 } else if ((copyVal & sbeAISAlm) && !(value & sbeAISAlm))
341 copyVal &= ~sbeAISAlm;
342 pr_warning("%s: Port %d blue (AIS) alarm ended.\n",
343 ci->devname, portnum);
344 } else if (!(copyVal & sbeAISAlm) && (value & sbeAISAlm))
346 copyVal |= sbeAISAlm;
347 pr_warning("%s: Warning: Port %d blue (AIS) alarm.\n",
348 ci->devname, portnum);
351 } /* end T1 mode alarm checks */
353 if (copyVal & sbeAlarmsMask)
354 copyVal |= 0x80; /* if alarm turn yel LED on */
356 LEDval |= 0x100; /* tag if LED values have changed */
357 LEDval |= ((copyVal & 0xc0) >> (6 - (portnum * 2)));
359 ci->alarmed[portnum] &= 0xfffff000; /* out with the old (it's fff
361 ci->alarmed[portnum] |= (copyVal); /* in with the new */
364 * enough with the alarms and LED's, now let's check for loopback
368 if (IS_FRAME_ANY_T1 (ci->port[portnum].p.port_mode))
371 * begin in-band (SF) loopback code detection -- start by reading
374 value = pci_read_32 ((u_int32_t *) &comet->ibcd_ies); /* detect reg. */
375 value &= 0x3; /* trim to handy bits */
377 { /* activate loopback (sets for deactivate
379 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
381 if (copyVal != COMET_MDIAG_LINELB) /* don't do it again if
382 * already in that mode */
383 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
387 { /* deactivate loopback (sets for activate
389 copyVal = c4_loop_port (ci, portnum, COMET_LBCMD_READ); /* read line loopback
391 if (copyVal != COMET_MDIAG_LBOFF) /* don't do it again if
392 * already in that mode */
393 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
397 if (IS_FRAME_ANY_T1ESF (ci->port[portnum].p.port_mode))
398 { /* if a T1 ESF mode */
399 /* begin ESF loopback code */
400 value = pci_read_32 ((u_int32_t *) &comet->t1_rboc_sts) & 0x3f; /* read command */
402 c4_loop_port (ci, portnum, COMET_MDIAG_LINELB); /* put port in line
405 c4_loop_port (ci, portnum, COMET_MDIAG_PAYLB); /* put port in payload
407 if ((value == 0x1c) || (value == 0x19) || (value == 0x12))
408 c4_loop_port (ci, portnum, COMET_MDIAG_LBOFF); /* take port out of any
410 if (cxt1e1_log_level >= LOG_DEBUG)
412 pr_warning("%s: BOC value = %x on Port %d\n",
413 ci->devname, value, portnum);
414 /* end ESF loopback code */
418 /* if something is new, update LED's */
420 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, LEDval & 0xff);
421 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
426 c4_watchdog (ci_t *ci)
428 if (drvr_state != SBE_DRVR_AVAILABLE)
430 if (cxt1e1_log_level >= LOG_MONITOR)
431 pr_info("drvr not available (%x)\n", drvr_state);
450 next = ci->next; /* protect <next> from upcoming <free> */
451 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
452 for (portnum = 0; portnum < ci->max_port; portnum++)
454 pi = &ci->port[portnum];
455 c4_wq_port_cleanup (pi);
456 for (j = 0; j < MUSYCC_NCHANS; j++)
459 kfree(pi->chan[j]); /* free mch_t struct */
461 kfree(pi->regram_saved);
463 kfree(ci->iqd_p_saved);
465 ci = next; /* cleanup next board, if any */
471 * This function issues a write to all comet chips and expects the same data
472 * to be returned from the subsequent read. This determines the board build
473 * to be a 1-port, 2-port, or 4-port build. The value returned represents a
474 * bit-mask of the found ports. Only certain configurations are considered
475 * VALID or LEGAL builds.
479 c4_get_portcfg (ci_t *ci)
481 struct s_comet_reg *comet;
483 u_int32_t wdata, rdata;
485 wdata = COMET_MDIAG_LBOFF; /* take port out of any loopback mode */
488 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
490 comet = ci->port[portnum].cometbase;
491 pci_write_32 ((u_int32_t *) &comet->mdiag, wdata);
492 rdata = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
494 mask |= 1 << portnum;
500 /* nothing herein should generate interrupts */
503 c4_init (ci_t *ci, u_char *func0, u_char *func1)
507 static u_int32_t count = 0;
512 ci->intlog.this_status_new = 0;
513 atomic_set (&ci->bh_pending, 0);
515 ci->reg = (struct musycc_globalr *) func0;
516 ci->eeprombase = (u_int32_t *) (func1 + EEPROM_OFFSET);
517 ci->cpldbase = (c4cpld_t *) ((u_int32_t *) (func1 + ISPLD_OFFSET));
519 /*** PORT POINT - the following is the first access of any type to the hardware ***/
520 #ifdef CONFIG_SBE_PMCC4_NCOMM
521 /* NCOMM driver uses INTB interrupt to monitor CPLD register */
522 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC);
524 /* standard driver POLLS for INTB via CPLD register */
525 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
531 /* need comet addresses available for determination of hardware build */
532 for (portnum = 0; portnum < MUSYCC_NPORTS; portnum++)
534 pi = &ci->port[portnum];
535 pi->cometbase = (struct s_comet_reg *) ((u_int32_t *) (func1 + COMET_OFFSET (portnum)));
536 pi->reg = (struct musycc_globalr *) ((u_char *) ci->reg + (portnum * 0x800));
537 pi->portnum = portnum;
538 pi->p.portnum = portnum;
541 pr_info("Comet-%d: addr = %p\n", portnum, pi->cometbase);
544 pmsk = c4_get_portcfg (ci);
554 case 0x7: /* not built, but could be... */
563 pr_warning("%s: illegal port configuration (%x)\n",
565 return SBE_DRVR_FAIL;
568 pr_info(">> %s: c4_get_build - pmsk %x max_port %x\n",
569 ci->devname, pmsk, ci->max_port);
573 for (portnum = 0; portnum < ci->max_port; portnum++)
575 pi = &ci->port[portnum];
577 pi->sr_last = 0xffffffff;
578 pi->p.port_mode = CFG_FRAME_SF; /* T1 B8ZS, the default */
579 pi->p.portP = (CFG_CLK_PORT_EXTERNAL | CFG_LBO_LH0); /* T1 defaults */
581 OS_sem_init (&pi->sr_sem_busy, SEM_AVAILABLE);
582 OS_sem_init (&pi->sr_sem_wait, SEM_TAKEN);
584 for (j = 0; j < 32; j++)
587 pi->tsm[j] = 0; /* no assignments, all available */
590 /* allocate channel structures for this port */
591 for (j = 0; j < MUSYCC_NCHANS; j++)
593 ch = kzalloc(sizeof(mch_t), GFP_KERNEL | GFP_DMA);
597 ch->state = UNASSIGNED;
599 ch->gchan = (-1); /* channel assignment not yet known */
600 ch->channum = (-1); /* channel assignment not yet known */
601 ch->p.card = ci->brdno;
602 ch->p.port = portnum;
603 ch->p.channum = (-1); /* channel assignment not yet known */
604 ch->p.mode_56k = 0; /* default is 64kbps mode */
607 pr_warning("failed mch_t malloc, port %d channel %d size %u.\n",
608 portnum, j, (unsigned int) sizeof (mch_t));
617 * Set LEDs through their paces to supply visual proof that LEDs are
618 * functional and not burnt out nor broken.
620 * YELLOW + GREEN -> OFF.
623 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds,
624 PMCC4_CPLD_LED_GREEN | PMCC4_CPLD_LED_YELLOW);
625 OS_uwait (750000, "leds");
626 pci_write_32 ((u_int32_t *) &ci->cpldbase->leds, PMCC4_CPLD_LED_OFF);
629 OS_init_watchdog (&ci->wd, (void (*) (void *)) c4_watchdog, ci, WATCHDOG_TIMEOUT);
630 return SBE_DRVR_SUCCESS;
634 /* better be fully setup to handle interrupts when you call this */
641 /* PORT POINT: this routine generates first interrupt */
642 ret = musycc_init(ci);
643 if (ret != SBE_DRVR_SUCCESS)
647 ci->p.framing_type = FRAMING_CBP;
648 ci->p.h110enable = 1;
654 ci->p.clock = 0; /* Use internal clocking until set to
656 c4_card_set_params (ci, &ci->p);
658 OS_start_watchdog (&ci->wd);
659 return SBE_DRVR_SUCCESS;
663 /* This function sets the loopback mode (or clears it, as the case may be). */
666 c4_loop_port (ci_t *ci, int portnum, u_int8_t cmd)
668 struct s_comet_reg *comet;
669 volatile u_int32_t loopValue;
671 comet = ci->port[portnum].cometbase;
672 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
674 if (cmd & COMET_LBCMD_READ)
675 return loopValue; /* return the read value */
677 if (loopValue != cmd)
681 case COMET_MDIAG_LINELB:
682 /* set(SF)loopback down (turn off) code length to 6 bits */
683 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x05);
685 case COMET_MDIAG_LBOFF:
686 /* set (SF) loopback up (turn on) code length to 5 bits */
687 pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x00);
691 pci_write_32 ((u_int32_t *) &comet->mdiag, cmd);
692 if (cxt1e1_log_level >= LOG_WARN)
693 pr_info("%s: loopback mode changed to %2x from %2x on Port %d\n",
694 ci->devname, cmd, loopValue, portnum);
695 loopValue = pci_read_32 ((u_int32_t *) &comet->mdiag) & COMET_MDIAG_LBMASK;
696 if (loopValue != cmd)
698 if (cxt1e1_log_level >= LOG_ERROR)
699 pr_info("%s: write to loop register failed, unknown state for Port %d\n",
700 ci->devname, portnum);
704 if (cxt1e1_log_level >= LOG_WARN)
705 pr_info("%s: loopback already in that mode (%2x)\n",
706 ci->devname, loopValue);
712 /* c4_frame_rw: read or write the comet register specified
713 * (modifies use of port_param to non-standard use of struct)
715 * pp.portnum (one guess)
716 * pp.port_mode offset of register
717 * pp.portP write (or not, i.e. read)
718 * pp.portStatus write value
720 * pp.portStatus also used to return read value
721 * pp.portP also used during write, to return old reg value
725 c4_frame_rw (ci_t *ci, struct sbecom_port_param *pp)
727 struct s_comet_reg *comet;
728 volatile u_int32_t data;
730 if (pp->portnum >= ci->max_port)/* sanity check */
733 comet = ci->port[pp->portnum].cometbase;
734 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
737 { /* control says this is a register
739 if (pp->portStatus == data)
740 pr_info("%s: Port %d already that value! Writing again anyhow.\n",
741 ci->devname, pp->portnum);
742 pp->portP = (u_int8_t) data;
743 pci_write_32 ((u_int32_t *) comet + pp->port_mode,
745 data = pci_read_32 ((u_int32_t *) comet + pp->port_mode) & 0xff;
747 pp->portStatus = (u_int8_t) data;
752 /* c4_pld_rw: read or write the pld register specified
753 * (modifies use of port_param to non-standard use of struct)
755 * pp.port_mode offset of register
756 * pp.portP write (or not, i.e. read)
757 * pp.portStatus write value
759 * pp.portStatus also used to return read value
760 * pp.portP also used during write, to return old reg value
764 c4_pld_rw (ci_t *ci, struct sbecom_port_param *pp)
766 volatile u_int32_t *regaddr;
767 volatile u_int32_t data;
768 int regnum = pp->port_mode;
770 regaddr = (u_int32_t *) ci->cpldbase + regnum;
771 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
774 { /* control says this is a register
776 pp->portP = (u_int8_t) data;
777 pci_write_32 ((u_int32_t *) regaddr, pp->portStatus);
778 data = pci_read_32 ((u_int32_t *) regaddr) & 0xff;
780 pp->portStatus = (u_int8_t) data;
784 /* c4_musycc_rw: read or write the musycc register specified
785 * (modifies use of port_param to non-standard use of struct)
787 * mcp.RWportnum port number and write indication bit (0x80)
788 * mcp.offset offset of register
789 * mcp.value write value going in and read value returning
792 /* PORT POINT: TX Subchannel Map registers are write-only
793 * areas within the MUSYCC and always return FF */
794 /* PORT POINT: regram and reg structures are minorly different and <offset> ioctl
795 * settings are aligned with the <reg> struct musycc_globalr{} usage.
796 * Also, regram is separately allocated shared memory, allocated for each port.
797 * PORT POINT: access offsets of 0x6000 for Msg Cfg Desc Tbl are for 4-port MUSYCC
798 * only. (An 8-port MUSYCC has 0x16000 offsets for accessing its upper 4 tables.)
802 c4_musycc_rw (ci_t *ci, struct c4_musycc_param *mcp)
805 volatile u_int32_t *dph; /* hardware implemented register */
806 u_int32_t *dpr = NULL; /* RAM image of registers for group command
808 int offset = mcp->offset % 0x800; /* group relative address
809 * offset, mcp->portnum is
811 int portnum, ramread = 0;
812 volatile u_int32_t data;
815 * Sanity check hardware accessibility. The 0x6000 portion handles port
816 * numbers associated with Msg Descr Tbl decoding.
818 portnum = (mcp->offset % 0x6000) / 0x800;
819 if (portnum >= ci->max_port)
821 pi = &ci->port[portnum];
822 if (mcp->offset >= 0x6000)
823 offset += 0x6000; /* put back in MsgCfgDesc address offset */
824 dph = (u_int32_t *) ((u_long) pi->reg + offset);
826 /* read of TX are from RAM image, since hardware returns FF */
827 dpr = (u_int32_t *) ((u_long) pi->regram + offset);
828 if (mcp->offset < 0x6000) /* non MsgDesc Tbl accesses might require
831 if (offset >= 0x200 && offset < 0x380)
833 if (offset >= 0x10 && offset < 0x200)
836 /* read register from RAM or hardware, depending... */
840 //pr_info("c4_musycc_rw: RAM addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dpr, data, portnum, offset, ramread); /* RLD DEBUG */
843 data = pci_read_32 ((u_int32_t *) dph);
844 //pr_info("c4_musycc_rw: REG addr %p read data %x (portno %x offset %x RAM ramread %x)\n", dph, data, portnum, offset, ramread); /* RLD DEBUG */
848 if (mcp->RWportnum & 0x80)
849 { /* control says this is a register
851 if (mcp->value == data)
852 pr_info("%s: musycc grp%d already that value! writing again anyhow.\n",
853 ci->devname, (mcp->RWportnum & 0x7));
854 /* write register RAM */
857 /* write hardware register */
858 pci_write_32 ((u_int32_t *) dph, mcp->value);
860 mcp->value = data; /* return the read value (or the 'old
861 * value', if is write) */
866 c4_get_port (ci_t *ci, int portnum)
868 if (portnum >= ci->max_port) /* sanity check */
871 SD_SEM_TAKE (&ci->sem_wdbusy, "_wd_"); /* only 1 thru here, per
874 ci->port[portnum].p.portStatus = (u_int8_t) ci->alarmed[portnum];
875 ci->alarmed[portnum] &= 0xdf;
876 SD_SEM_GIVE (&ci->sem_wdbusy); /* release per-board hold */
881 c4_set_port (ci_t *ci, int portnum)
884 struct sbecom_port_param *pp;
889 if (portnum >= ci->max_port) /* sanity check */
892 pi = &ci->port[portnum];
893 pp = &ci->port[portnum].p;
894 e1mode = IS_FRAME_ANY_E1 (pp->port_mode);
895 if (cxt1e1_log_level >= LOG_MONITOR2)
897 pr_info("%s: c4_set_port[%d]: entered, e1mode = %x, openchans %d.\n",
899 portnum, e1mode, pi->openchans);
902 return -EBUSY; /* group needs initialization only for
903 * first channel of a group */
908 ret = c4_wq_port_init(pi);
909 if (ret) /* create/init workqueue_struct */
913 init_comet (ci, pi->cometbase, pp->port_mode, 1 /* clockmaster == true */ , pp->portP);
914 clck = pci_read_32 ((u_int32_t *) &ci->cpldbase->mclk) & PMCC4_CPLD_MCLK_MASK;
916 clck |= 1 << portnum;
918 clck &= 0xf ^ (1 << portnum);
920 pci_write_32 ((u_int32_t *) &ci->cpldbase->mclk, clck);
921 pci_write_32 ((u_int32_t *) &ci->cpldbase->mcsr, PMCC4_CPLD_MCSR_IND);
922 pci_write_32 ((u_int32_t *) &pi->reg->gbp, OS_vtophys (pi->regram));
924 /*********************************************************************/
925 /* ERRATA: If transparent mode is used, do not set OOFMP_DISABLE bit */
926 /*********************************************************************/
929 __constant_cpu_to_le32 (MUSYCC_GRCD_RX_ENABLE |
930 MUSYCC_GRCD_TX_ENABLE |
931 MUSYCC_GRCD_OOFMP_DISABLE |
932 MUSYCC_GRCD_SF_ALIGN | /* per MUSYCC ERRATA,
934 MUSYCC_GRCD_COFAIRQ_DISABLE |
935 MUSYCC_GRCD_MC_ENABLE |
936 (MUSYCC_GRCD_POLLTH_32 << MUSYCC_GRCD_POLLTH_SHIFT));
939 __constant_cpu_to_le32 ((e1mode ? 1 : 0) |
940 MUSYCC_PCD_TXSYNC_RISING |
941 MUSYCC_PCD_RXSYNC_RISING |
942 MUSYCC_PCD_RXDATA_RISING);
944 /* Message length descriptor */
945 pi->regram->mld = __constant_cpu_to_le32 (cxt1e1_max_mru | (cxt1e1_max_mru << 16));
948 for (i = 0; i < 32; i++)
951 /*** ASSIGNMENT NOTES: ***/
952 /*** Group's channel ZERO unavailable if E1. ***/
953 /*** Group's channel 16 unavailable if E1 CAS. ***/
954 /*** Group's channels 24-31 unavailable if T1. ***/
956 if (((i == 0) && e1mode) ||
957 ((i == 16) && ((pp->port_mode == CFG_FRAME_E1CRC_CAS) || (pp->port_mode == CFG_FRAME_E1CRC_CAS_AMI)))
958 || ((i > 23) && (!e1mode)))
960 pi->tsm[i] = 0xff; /* make tslot unavailable for this mode */
963 pi->tsm[i] = 0x00; /* make tslot available for assignment */
966 for (i = 0; i < MUSYCC_NCHANS; i++)
968 pi->regram->ttsm[i] = 0;
969 pi->regram->rtsm[i] = 0;
972 musycc_serv_req (pi, SR_GROUP_INIT | SR_RX_DIRECTION);
973 musycc_serv_req (pi, SR_GROUP_INIT | SR_TX_DIRECTION);
975 musycc_init_mdt (pi);
977 pi->group_is_set = 1;
983 unsigned int max_int = 0;
986 c4_new_chan (ci_t *ci, int portnum, int channum, void *user)
992 if (c4_find_chan (channum)) /* a new channel shouldn't already exist */
995 if (portnum >= ci->max_port) /* sanity check */
998 pi = &(ci->port[portnum]);
999 /* find any available channel within this port */
1000 for (gchan = 0; gchan < MUSYCC_NCHANS; gchan++)
1002 ch = pi->chan[gchan];
1003 if (ch && ch->state == UNASSIGNED) /* no assignment is good! */
1006 if (gchan == MUSYCC_NCHANS) /* exhausted table, all were assigned */
1011 /* NOTE: mch_t already cleared during OS_kmalloc() */
1015 ch->channum = channum; /* mark our channel assignment */
1016 ch->p.channum = channum;
1018 ch->p.card = ci->brdno;
1019 ch->p.port = portnum;
1021 ch->p.chan_mode = CFG_CH_PROTO_HDLC_FCS16;
1022 ch->p.idlecode = CFG_CH_FLAG_7E;
1023 ch->p.pad_fill_count = 2;
1024 spin_lock_init (&ch->ch_rxlock);
1025 spin_lock_init (&ch->ch_txlock);
1030 ret = c4_wk_chan_init(pi, ch);
1035 /* save off interface assignments which bound a board */
1036 if (!ci->first_if) /* first channel registered is assumed to
1037 * be the lowest channel */
1039 ci->first_if = ci->last_if = user;
1040 ci->first_channum = ci->last_channum = channum;
1044 if (ci->last_channum < channum) /* higher number channel found */
1045 ci->last_channum = channum;
1051 c4_del_chan (int channum)
1055 ch = c4_find_chan(channum);
1059 if (ch->state == UP)
1060 musycc_chan_down ((ci_t *) 0, channum);
1061 ch->state = UNASSIGNED;
1064 ch->p.channum = (-1);
1069 c4_del_chan_stats (int channum)
1073 ch = c4_find_chan(channum);
1077 memset (&ch->s, 0, sizeof (struct sbecom_chan_stats));
1083 c4_set_chan (int channum, struct sbecom_chan_param *p)
1088 ch = c4_find_chan(channum);
1093 if (ch->p.card != p->card ||
1094 ch->p.port != p->port ||
1095 ch->p.channum != p->channum)
1099 if (!(ch->up->group_is_set))
1101 return -EIO; /* out of order, SET_PORT command
1102 * required prior to first group's
1103 * SET_CHAN command */
1106 * Check for change of parameter settings in order to invoke closing of
1107 * channel prior to hardware poking.
1110 if (ch->p.status != p->status || ch->p.chan_mode != p->chan_mode ||
1111 ch->p.data_inv != p->data_inv || ch->p.intr_mask != p->intr_mask ||
1112 ch->txd_free < ch->txd_num) /* to clear out queued messages */
1113 x = 1; /* we have a change requested */
1114 for (i = 0; i < 32; i++) /* check for timeslot mapping changes */
1115 if (ch->p.bitmask[i] != p->bitmask[i])
1116 x = 1; /* we have a change requested */
1118 if (x && (ch->state == UP)) /* if change request and channel is
1123 ret = musycc_chan_down((ci_t *)0, channum);
1126 ret = c4_chan_up(ch->up->up, channum);
1129 sd_enable_xmit (ch->user); /* re-enable to catch flow controlled
1137 c4_get_chan (int channum, struct sbecom_chan_param *p)
1141 ch = c4_find_chan(channum);
1150 c4_get_chan_stats (int channum, struct sbecom_chan_stats *p)
1154 ch = c4_find_chan(channum);
1159 p->tx_pending = atomic_read (&ch->tx_pending);
1164 c4_fifo_alloc (mpi_t *pi, int chan, int *len)
1166 int i, l = 0, start = 0, max = 0, maxstart = 0;
1168 for (i = 0; i < 32; i++)
1170 if (pi->fifomap[i] != -1)
1187 if (cxt1e1_log_level >= LOG_WARN)
1188 pr_info("%s: wanted to allocate %d fifo space, but got only %d\n",
1189 pi->up->devname, *len, max);
1192 if (cxt1e1_log_level >= LOG_DEBUG)
1193 pr_info("%s: allocated %d fifo at %d for channel %d/%d\n",
1194 pi->up->devname, max, start, chan, pi->p.portnum);
1195 for (i = maxstart; i < (maxstart + max); i++)
1196 pi->fifomap[i] = chan;
1201 c4_fifo_free (mpi_t *pi, int chan)
1205 if (cxt1e1_log_level >= LOG_DEBUG)
1206 pr_info("%s: deallocated fifo for channel %d/%d\n",
1207 pi->up->devname, chan, pi->p.portnum);
1208 for (i = 0; i < 32; i++)
1209 if (pi->fifomap[i] == chan)
1210 pi->fifomap[i] = -1;
1215 c4_chan_up (ci_t *ci, int channum)
1221 int nts, nbuf, txnum, rxnum;
1222 int addr, i, j, gchan;
1223 u_int32_t tmp; /* for optimizing conversion across BE
1226 ch = c4_find_chan(channum);
1230 if (ch->state == UP)
1232 if (cxt1e1_log_level >= LOG_MONITOR)
1233 pr_info("%s: channel already UP, graceful early exit\n",
1239 /* find nts ('number of timeslots') */
1241 for (i = 0; i < 32; i++)
1243 if (ch->p.bitmask[i] & pi->tsm[i])
1245 if (1 || cxt1e1_log_level >= LOG_WARN)
1247 pr_info("%s: c4_chan_up[%d] EINVAL (attempt to cfg in-use or unavailable TimeSlot[%d])\n",
1248 ci->devname, channum, i);
1249 pr_info("+ ask4 %x, currently %x\n",
1250 ch->p.bitmask[i], pi->tsm[i]);
1254 for (j = 0; j < 8; j++)
1255 if (ch->p.bitmask[i] & (1 << j))
1259 nbuf = nts / 8 ? nts / 8 : 1;
1262 /* if( cxt1e1_log_level >= LOG_WARN) */
1263 pr_info("%s: c4_chan_up[%d] ENOBUFS (no TimeSlots assigned)\n",
1264 ci->devname, channum);
1265 return -ENOBUFS; /* this should not happen */
1267 addr = c4_fifo_alloc (pi, gchan, &nbuf);
1270 /* Setup the Time Slot Map */
1271 musycc_update_timeslots (pi);
1273 /* ch->tx_limit = nts; */
1274 ch->s.tx_pending = 0;
1276 /* Set Channel Configuration Descriptors */
1280 ccd = musycc_chan_proto (ch->p.chan_mode) << MUSYCC_CCD_PROTO_SHIFT;
1281 if ((ch->p.chan_mode == CFG_CH_PROTO_ISLP_MODE) ||
1282 (ch->p.chan_mode == CFG_CH_PROTO_TRANS))
1284 ccd |= MUSYCC_CCD_FCS_XFER; /* Non FSC Mode */
1286 ccd |= 2 << MUSYCC_CCD_MAX_LENGTH; /* Select second MTU */
1287 ccd |= ch->p.intr_mask;
1288 ccd |= addr << MUSYCC_CCD_BUFFER_LOC;
1289 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1290 ccd |= (nbuf) << MUSYCC_CCD_BUFFER_LENGTH;
1292 ccd |= (nbuf - 1) << MUSYCC_CCD_BUFFER_LENGTH;
1294 if (ch->p.data_inv & CFG_CH_DINV_TX)
1295 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1296 pi->regram->tcct[gchan] = cpu_to_le32 (ccd);
1298 if (ch->p.data_inv & CFG_CH_DINV_RX)
1299 ccd |= MUSYCC_CCD_INVERT_DATA; /* Invert data */
1301 ccd &= ~MUSYCC_CCD_INVERT_DATA; /* take away data inversion */
1302 pi->regram->rcct[gchan] = cpu_to_le32 (ccd);
1306 /* Reread the Channel Configuration Descriptor for this channel */
1307 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_RX_DIRECTION | gchan);
1308 musycc_serv_req (pi, SR_CHANNEL_CONFIG | SR_TX_DIRECTION | gchan);
1311 * Figure out how many buffers we want. If the customer has changed from
1312 * the defaults, then use the changed values. Otherwise, use Transparent
1313 * mode's specific minimum default settings.
1315 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1317 if (max_rxdesc_used == max_rxdesc_default) /* use default setting */
1318 max_rxdesc_used = MUSYCC_RXDESC_TRANS;
1319 if (max_txdesc_used == max_txdesc_default) /* use default setting */
1320 max_txdesc_used = MUSYCC_TXDESC_TRANS;
1323 * Increase counts when hyperchanneling, since this implies an increase
1324 * in throughput per channel
1326 rxnum = max_rxdesc_used + (nts / 4);
1327 txnum = max_txdesc_used + (nts / 4);
1331 if (cxt1e1_log_level >= LOG_MONITOR)
1332 pr_info("%s: mode %x rxnum %d (rxused %d def %d) txnum %d (txused %d def %d)\n",
1333 ci->devname, ch->p.chan_mode,
1334 rxnum, max_rxdesc_used, max_rxdesc_default,
1335 txnum, max_txdesc_used, max_txdesc_default);
1338 ch->rxd_num = rxnum;
1339 ch->txd_num = txnum;
1340 ch->rxix_irq_srv = 0;
1342 ch->mdr = kzalloc(sizeof(struct mdesc) * rxnum, GFP_KERNEL | GFP_DMA);
1343 ch->mdt = kzalloc(sizeof(struct mdesc) * txnum, GFP_KERNEL | GFP_DMA);
1344 if (ch->p.chan_mode == CFG_CH_PROTO_TRANS)
1345 tmp = __constant_cpu_to_le32 (cxt1e1_max_mru | EOBIRQ_ENABLE);
1347 tmp = __constant_cpu_to_le32 (cxt1e1_max_mru);
1349 for (i = 0, md = ch->mdr; i < rxnum; i++, md++)
1351 if (i == (rxnum - 1))
1353 md->snext = &ch->mdr[0];/* wrapness */
1356 md->snext = &ch->mdr[i + 1];
1358 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1360 m = OS_mem_token_alloc(cxt1e1_max_mru);
1362 if (cxt1e1_log_level >= LOG_MONITOR)
1364 "%s: c4_chan_up[%d] - token alloc failure, size = %d.\n",
1365 ci->devname, channum, cxt1e1_max_mru);
1369 md->data = cpu_to_le32 (OS_vtophys (OS_mem_token_data (m)));
1370 md->status = tmp | MUSYCC_RX_OWNED; /* MUSYCC owns RX descriptor **
1372 * MUSYCC_RX_OWNED = 0 so no
1373 * need to byteSwap */
1376 for (i = 0, md = ch->mdt; i < txnum; i++, md++)
1378 md->status = HOST_TX_OWNED; /* Host owns TX descriptor ** CODING
1379 * NOTE: HOST_TX_OWNED = 0 so no need to
1381 md->mem_token = NULL;
1383 if (i == (txnum - 1))
1385 md->snext = &ch->mdt[0];/* wrapness */
1388 md->snext = &ch->mdt[i + 1];
1390 md->next = cpu_to_le32 (OS_vtophys (md->snext));
1392 ch->txd_irq_srv = ch->txd_usr_add = &ch->mdt[0];
1393 ch->txd_free = txnum;
1395 ch->txd_required = 0;
1397 /* Configure it into the chip */
1398 tmp = cpu_to_le32 (OS_vtophys (&ch->mdt[0]));
1399 pi->regram->thp[gchan] = tmp;
1400 pi->regram->tmp[gchan] = tmp;
1402 tmp = cpu_to_le32 (OS_vtophys (&ch->mdr[0]));
1403 pi->regram->rhp[gchan] = tmp;
1404 pi->regram->rmp[gchan] = tmp;
1406 /* Activate the Channel */
1408 if (ch->p.status & RX_ENABLED)
1410 #ifdef RLD_TRANS_DEBUG
1411 pr_info("++ c4_chan_up() CHAN RX ACTIVATE: chan %d\n", ch->channum);
1413 ch->ch_start_rx = 0; /* we are restarting RX... */
1414 musycc_serv_req (pi, SR_CHANNEL_ACTIVATE | SR_RX_DIRECTION | gchan);
1416 if (ch->p.status & TX_ENABLED)
1418 #ifdef RLD_TRANS_DEBUG
1419 pr_info("++ c4_chan_up() CHAN TX ACTIVATE: chan %d <delayed>\n", ch->channum);
1421 ch->ch_start_tx = CH_START_TX_1ST; /* we are delaying start
1422 * until receipt from user of
1423 * first packet to transmit. */
1425 ch->status = ch->p.status;
1432 /* Don't leak all the previously allocated mbufs in this loop */
1434 OS_mem_token_free (ch->mdr[i].mem_token);
1446 /* stop the hardware from servicing & interrupting */
1449 c4_stopwd (ci_t *ci)
1451 OS_stop_watchdog (&ci->wd);
1452 SD_SEM_TAKE (&ci->sem_wdbusy, "_stop_"); /* ensure WD not running */
1453 SD_SEM_GIVE (&ci->sem_wdbusy);
1458 sbecom_get_brdinfo (ci_t *ci, struct sbe_brd_info *bip, u_int8_t *bsn)
1464 bip->brdno = ci->brdno; /* our board number */
1465 bip->brd_id = ci->brd_id;
1466 bip->brd_hdw_id = ci->hdw_bid;
1467 bip->brd_chan_cnt = MUSYCC_NCHANS *ci->max_port; /* number of channels
1469 bip->brd_port_cnt = ci->max_port; /* number of ports being used */
1470 bip->brd_pci_speed = BINFO_PCI_SPEED_unk; /* PCI speed not yet
1476 struct net_device *dev;
1478 dev = (struct net_device *) ci->first_if;
1479 np = (char *) dev->name;
1481 strncpy (bip->first_iname, np, CHNM_STRLEN - 1);
1483 strcpy (bip->first_iname, "<NULL>");
1487 struct net_device *dev;
1489 dev = (struct net_device *) ci->last_if;
1490 np = (char *) dev->name;
1492 strncpy (bip->last_iname, np, CHNM_STRLEN - 1);
1494 strcpy (bip->last_iname, "<NULL>");
1498 for (i = 0; i < 3; i++)
1500 bip->brd_mac_addr[i] = *bsn++;
1504 bip->brd_mac_addr[i] = *bsn;
1505 sn = (sn << 8) | *bsn++;
1509 for (i = 0; i < 6; i++)
1510 bip->brd_mac_addr[i] = 0;
1517 c4_get_iidinfo (ci_t *ci, struct sbe_iid_info *iip)
1519 struct net_device *dev;
1522 dev = getuserbychan(iip->channum);
1527 strncpy (iip->iname, np, CHNM_STRLEN - 1);
1528 iip->iname[CHNM_STRLEN - 1] = '\0';
1533 #ifdef CONFIG_SBE_PMCC4_NCOMM
1534 void (*nciInterrupt[MAX_BOARDS][4]) (void);
1535 extern void wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler);
1538 wanpmcC4T1E1_hookInterrupt (int cardID, int deviceID, void *handler)
1540 if (cardID < MAX_BOARDS) /* sanity check */
1541 nciInterrupt[cardID][deviceID] = handler;
1545 c4_ebus_intr_th_handler (void *devp)
1547 ci_t *ci = (ci_t *) devp;
1548 volatile u_int32_t ists;
1552 /* which COMET caused the interrupt */
1554 ists = pci_read_32 ((u_int32_t *) &ci->cpldbase->intr);
1555 if (ists & PMCC4_CPLD_INTR_CMT_1)
1558 if (nciInterrupt[brdno][0] != NULL)
1559 (*nciInterrupt[brdno][0]) ();
1561 if (ists & PMCC4_CPLD_INTR_CMT_2)
1564 if (nciInterrupt[brdno][1] != NULL)
1565 (*nciInterrupt[brdno][1]) ();
1567 if (ists & PMCC4_CPLD_INTR_CMT_3)
1570 if (nciInterrupt[brdno][2] != NULL)
1571 (*nciInterrupt[brdno][2]) ();
1573 if (ists & PMCC4_CPLD_INTR_CMT_4)
1576 if (nciInterrupt[brdno][3] != NULL)
1577 (*nciInterrupt[brdno][3]) ();
1580 /*** Test code just de-implements the asserted interrupt. Alternate
1581 vendor will supply COMET interrupt handling code herein or such.
1583 pci_write_32 ((u_int32_t *) &ci->reg->glcd, GCD_MAGIC | MUSYCC_GCD_INTB_DISABLE);
1586 return IRQ_RETVAL (handled);
1591 wanpmcC4T1E1_getBaseAddress (int cardID, int deviceID)
1594 unsigned long base = 0;
1599 if (ci->brdno == cardID) /* found valid device */
1601 if (deviceID < ci->max_port) /* comet is supported */
1602 base = ((unsigned long) ci->port[deviceID].cometbase);
1605 ci = ci->next; /* next board, if any */
1610 #endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
1613 /*** End-of-File ***/