1 #ifndef _INC_PMCC4_PRIVATE_H_
2 #define _INC_PMCC4_PRIVATE_H_
4 /*-----------------------------------------------------------------------------
7 * Copyright (C) 2005 SBE, Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 #include <linux/kernel.h>
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h> /* support for tasklets */
26 #include <linux/timer.h> /* support for timer */
27 #include <linux/workqueue.h>
28 #include <linux/hdlc.h>
31 #include "pmcc4_defs.h"
32 #include "pmcc4_cpld.h"
34 #include "sbe_promformat.h"
39 #define SBE_DRVR_INIT 0x0
40 #define SBE_DRVR_AVAILABLE 0x69734F4E
41 #define SBE_DRVR_DOWN 0x1
43 /******************************************************************************
44 * MUSYCC Message Descriptor - coupled to hardware implementation, the first
45 * three u_int32 must not be reordered.
50 volatile u_int32_t status; /* Buffer Descriptor */
51 u_int32_t data; /* Data Pointer */
52 u_int32_t next; /* MUSYCC view of Next Pointer */
53 void *mem_token; /* Data */
58 /*************************************************************************
59 * Private driver data structures, internal use only.
64 int gchan; /* channel number within group/port 0-31 */
65 int channum; /* absolute channel number 0-128 */
67 #define TX_RECOVERY_MASK 0x0f
68 #define TX_ONR_RECOVERY 0x01
69 #define TX_BUFF_RECOVERY 0x02
70 #define RX_RECOVERY_MASK 0xf0
71 #define RX_ONR_RECOVERY 0x10
73 unsigned char ch_start_rx;
74 #define CH_START_RX_NOW 1
75 #define CH_START_RX_ONR 2
76 #define CH_START_RX_BUF 3
78 unsigned char ch_start_tx;
79 #define CH_START_TX_1ST 1
80 #define CH_START_TX_ONR 2
81 #define CH_START_TX_BUF 3
83 char tx_full; /* boolean */
84 short txd_free; /* count of TX Desc available */
85 short txd_required; /* count of TX Desc needed by mesg */
86 unsigned short rxd_num; /* must support range up to 2000 */
87 unsigned short txd_num; /* must support range up to 1000 */
92 UNASSIGNED, /* AVAILABLE, NOTINUSE */
93 DOWN, /* ASSIGNED, NOTINUSE */
94 UP /* ASSIGNED and INUSE */
97 struct c4_port_info *up;
100 struct work_struct ch_work;
103 struct mdesc *txd_irq_srv;
104 struct mdesc *txd_usr_add;
108 * FUTURE CODE MIGHT SEPARATE TIMESLOT MAP SETUPS INTO SINGLE IOCTL and
109 * REMOVE MAPS FROM CHANNEL PARAMETER STRUCTURE
112 * each byte in bitmask below represents one timeslot (bitmask[0] is for
113 * timeslot 0 and so on), each bit in the byte selects timeslot bits for
114 * this channel (0xff - whole timeslot, 0x7f - 56kbps mode)
117 u_int8_t ts_bitmask[32];
119 spinlock_t ch_rxlock;
120 spinlock_t ch_txlock;
123 struct sbecom_chan_stats s;
124 struct sbecom_chan_param p;
126 typedef struct c4_chan_info mch_t;
131 struct musycc_globalr *reg;
132 struct musycc_groupr *regram;
133 void *regram_saved; /* Original malloc value may have non-2KB
134 * boundary. Need to save for use when
136 struct s_comet_reg *cometbase;
137 struct sbe_card_info *up;
140 * The workqueue is used for TX restart of ONR'd channels when in
144 struct workqueue_struct *wq_port; /* chan restart work queue */
145 struct semaphore sr_sem_busy; /* service request exclusion
147 struct semaphore sr_sem_wait; /* service request handshake
152 char group_is_set; /* GROUP_INIT command issued to MUSYCC,
153 * otherwise SET_CHAN Ioctl fails */
155 mch_t *chan[MUSYCC_NCHANS];
156 struct sbecom_port_param p;
159 * The MUSYCC timeslot mappings are maintained within the driver and are
160 * modified and reloaded as each of a group's channels are configured.
162 u_int8_t tsm[32]; /* tsm (time slot map) */
165 typedef struct c4_port_info mpi_t;
168 #define COMET_OFFSET(x) (0x80000+(x)*0x10000)
169 #define EEPROM_OFFSET 0xC0000
170 #define ISPLD_OFFSET 0xD0000
172 /* iSPLD control chip registers */
173 #define ISPLD_MCSR 0x0
174 #define ISPLD_MCLK 0x1
175 #define ISPLD_LEDS 0x2
176 #define ISPLD_INTR 0x3
177 #define ISPLD_MAX 0x3
181 struct musycc_globalr *reg;
182 struct musycc_groupr *regram;
183 u_int32_t *iqd_p; /* pointer to dword aligned interrupt queue
185 void *iqd_p_saved; /* Original malloc value may have non-dword
186 * aligned boundary. Need to save for use
188 unsigned int iqp_headx, iqp_tailx;
190 struct semaphore sem_wdbusy;/* watchdog exclusion semaphore */
191 struct watchdog wd; /* statically allocated watchdog structure */
192 atomic_t bh_pending; /* bh queued, but not yet running */
193 u_int32_t brd_id; /* unique PCI ID */
194 u_int16_t hdw_bid; /* on/board hardware ID */
195 unsigned short wdcount;
196 unsigned char max_port;
197 unsigned char brdno; /* our board number */
198 unsigned char wd_notify;
199 #define WD_NOTIFY_1TX 1
200 #define WD_NOTIFY_BUF 2
201 #define WD_NOTIFY_ONR 4
202 enum /* state as regards interrupt processing */
204 C_INIT, /* of-board-address not configured or are in
205 * process of being removed, don't access
207 C_IDLE, /* off-board-addresses are configured, but
208 * don't service interrupts, just clear them
210 C_RUNNING /* life is good, service away */
213 struct sbe_card_info *next;
214 u_int32_t *eeprombase; /* mapped address of board's EEPROM */
215 c4cpld_t *cpldbase; /* mapped address of board's CPLD hardware */
217 #ifdef CONFIG_PROC_FS
218 struct proc_dir_entry *dir_dev;
221 /* saved off interface assignments which bound a board */
222 hdlc_device *first_if;
223 hdlc_device *last_if;
224 short first_channum, last_channum;
228 u_int32_t this_status_new;
229 u_int32_t last_status_new;
230 u_int32_t drvr_intr_thcount;
231 u_int32_t drvr_intr_bhcount;
232 u_int32_t drvr_int_failure;
235 mpi_t port[MUSYCC_NPORTS];
236 char devname[SBE_IFACETMPL_SIZE + 1];
238 u_int32_t alarmed[4]; /* dpm211 */
240 #if defined(SBE_ISR_TASKLET)
241 struct tasklet_struct ci_musycc_isr_tasklet;
242 #elif defined(SBE_ISR_IMMEDIATE)
243 struct tq_struct ci_musycc_isr_tq;
246 typedef struct sbe_card_info ci_t;
254 u_int8_t mfg_info_sts;
255 #define EEPROM_OK 0x00
256 #define EEPROM_CRCERR 0x01
257 char promfmt; /* prom type, from sbe_promformat.h */
259 char devname[SBE_IFACETMPL_SIZE];
261 struct net_device *ndev;
262 struct pci_dev *pdev[2];
264 unsigned long addr[2];
265 unsigned long addr_mapped[2];
266 unsigned long len[2];
271 FLD_TYPE1 pft1; /* prom field, type #1 */
272 FLD_TYPE2 pft2; /* prom field, type #2 */
275 typedef struct s_hdw_info hdw_info_t;
277 /*****************************************************************/
282 struct sbe_card_info *ci;
286 /*****************************************************************/
288 extern ci_t *c4_list;
290 mch_t *c4_find_chan (int);
291 int c4_set_chan (int channum, struct sbecom_chan_param *);
292 int c4_get_chan (int channum, struct sbecom_chan_param *);
293 int c4_get_chan_stats (int channum, struct sbecom_chan_stats *);
295 #endif /* _INC_PMCC4_PRIVATE_H_ */