2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 * NOTE: THIS IS A SHARED HEADER. DO NOT CHANGE CODING STYLE!!!
22 /* $Id: dgap_pci.h,v 1.1 2009/10/23 14:01:57 markh Exp $ */
27 #define PCIMAX 32 /* maximum number of PCI boards */
29 #define DIGI_VID 0x114F
31 #define PCI_DEVICE_EPC_DID 0x0002
32 #define PCI_DEVICE_XEM_DID 0x0004
33 #define PCI_DEVICE_XR_DID 0x0005
34 #define PCI_DEVICE_CX_DID 0x0006
35 #define PCI_DEVICE_XRJ_DID 0x0009 /* PLX-based Xr adapter */
36 #define PCI_DEVICE_XR_IBM_DID 0x0011 /* IBM 8-port Async Adapter */
37 #define PCI_DEVICE_XR_BULL_DID 0x0013 /* BULL 8-port Async Adapter */
38 #define PCI_DEVICE_XR_SAIP_DID 0x001c /* SAIP card - Xr adapter */
39 #define PCI_DEVICE_XR_422_DID 0x0012 /* Xr-422 */
40 #define PCI_DEVICE_920_2_DID 0x0034 /* XR-Plus 920 K, 2 port */
41 #define PCI_DEVICE_920_4_DID 0x0026 /* XR-Plus 920 K, 4 port */
42 #define PCI_DEVICE_920_8_DID 0x0027 /* XR-Plus 920 K, 8 port */
43 #define PCI_DEVICE_EPCJ_DID 0x000a /* PLX 9060 chip for PCI */
44 #define PCI_DEVICE_CX_IBM_DID 0x001b /* IBM 128-port Async Adapter */
45 #define PCI_DEVICE_920_8_HP_DID 0x0058 /* HP XR-Plus 920 K, 8 port */
46 #define PCI_DEVICE_XEM_HP_DID 0x0059 /* HP Xem PCI */
48 #define PCI_DEVICE_XEM_NAME "AccelePort XEM"
49 #define PCI_DEVICE_CX_NAME "AccelePort CX"
50 #define PCI_DEVICE_XR_NAME "AccelePort Xr"
51 #define PCI_DEVICE_XRJ_NAME "AccelePort Xr (PLX)"
52 #define PCI_DEVICE_XR_SAIP_NAME "AccelePort Xr (SAIP)"
53 #define PCI_DEVICE_920_2_NAME "AccelePort Xr920 2 port"
54 #define PCI_DEVICE_920_4_NAME "AccelePort Xr920 4 port"
55 #define PCI_DEVICE_920_8_NAME "AccelePort Xr920 8 port"
56 #define PCI_DEVICE_XR_422_NAME "AccelePort Xr 422"
57 #define PCI_DEVICE_EPCJ_NAME "AccelePort EPC (PLX)"
58 #define PCI_DEVICE_XR_BULL_NAME "AccelePort Xr (BULL)"
59 #define PCI_DEVICE_XR_IBM_NAME "AccelePort Xr (IBM)"
60 #define PCI_DEVICE_CX_IBM_NAME "AccelePort CX (IBM)"
61 #define PCI_DEVICE_920_8_HP_NAME "AccelePort Xr920 8 port (HP)"
62 #define PCI_DEVICE_XEM_HP_NAME "AccelePort XEM (HP)"
66 * On the PCI boards, there is no IO space allocated
67 * The I/O registers will be in the first 3 bytes of the
68 * upper 2MB of the 4MB memory space. The board memory
69 * will be mapped into the low 2MB of the 4MB memory space
72 /* Potential location of PCI Bios from E0000 to FFFFF*/
73 #define PCI_BIOS_SIZE 0x00020000
75 /* Size of Memory and I/O for PCI (4MB) */
76 #define PCI_RAM_SIZE 0x00400000
78 /* Size of Memory (2MB) */
79 #define PCI_MEM_SIZE 0x00200000
81 /* Max PCI Window Size (2MB) */
82 #define PCI_WIN_SIZE 0x00200000
84 #define PCI_WIN_SHIFT 21 /* 21 bits max */
86 /* Offset of I/0 in Memory (2MB) */
87 #define PCI_IO_OFFSET 0x00200000
89 /* Size of IO (2MB) */
90 #define PCI_IO_SIZE 0x00200000