2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h> /* For jiffies, task states */
18 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19 #include <linux/delay.h> /* For udelay */
20 #include <linux/io.h> /* For read[bwl]/write[bwl] */
21 #include <linux/serial.h> /* For struct async_serial */
22 #include <linux/serial_reg.h> /* For the various UART offsets */
23 #include <linux/pci.h>
25 #include "dgnc_driver.h" /* Driver main header file */
29 static inline void cls_parse_isr(struct dgnc_board *brd, uint port);
30 static inline void cls_clear_break(struct channel_t *ch, int force);
31 static inline void cls_set_cts_flow_control(struct channel_t *ch);
32 static inline void cls_set_rts_flow_control(struct channel_t *ch);
33 static inline void cls_set_ixon_flow_control(struct channel_t *ch);
34 static inline void cls_set_ixoff_flow_control(struct channel_t *ch);
35 static inline void cls_set_no_output_flow_control(struct channel_t *ch);
36 static inline void cls_set_no_input_flow_control(struct channel_t *ch);
37 static void cls_parse_modem(struct channel_t *ch, unsigned char signals);
38 static void cls_tasklet(unsigned long data);
39 static void cls_vpd(struct dgnc_board *brd);
40 static void cls_uart_init(struct channel_t *ch);
41 static void cls_uart_off(struct channel_t *ch);
42 static int cls_drain(struct tty_struct *tty, uint seconds);
43 static void cls_param(struct tty_struct *tty);
44 static void cls_assert_modem_signals(struct channel_t *ch);
45 static void cls_flush_uart_write(struct channel_t *ch);
46 static void cls_flush_uart_read(struct channel_t *ch);
47 static void cls_disable_receiver(struct channel_t *ch);
48 static void cls_enable_receiver(struct channel_t *ch);
49 static void cls_send_break(struct channel_t *ch, int msecs);
50 static void cls_send_start_character(struct channel_t *ch);
51 static void cls_send_stop_character(struct channel_t *ch);
52 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch);
53 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch);
54 static uint cls_get_uart_bytes_left(struct channel_t *ch);
55 static void cls_send_immediate_char(struct channel_t *ch, unsigned char);
56 static irqreturn_t cls_intr(int irq, void *voidbrd);
58 struct board_ops dgnc_cls_ops = {
59 .tasklet = cls_tasklet,
61 .uart_init = cls_uart_init,
62 .uart_off = cls_uart_off,
66 .assert_modem_signals = cls_assert_modem_signals,
67 .flush_uart_write = cls_flush_uart_write,
68 .flush_uart_read = cls_flush_uart_read,
69 .disable_receiver = cls_disable_receiver,
70 .enable_receiver = cls_enable_receiver,
71 .send_break = cls_send_break,
72 .send_start_character = cls_send_start_character,
73 .send_stop_character = cls_send_stop_character,
74 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
75 .get_uart_bytes_left = cls_get_uart_bytes_left,
76 .send_immediate_char = cls_send_immediate_char
79 static inline void cls_set_cts_flow_control(struct channel_t *ch)
81 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
82 unsigned char ier = readb(&ch->ch_cls_uart->ier);
83 unsigned char isr_fcr = 0;
86 * The Enhanced Register Set may only be accessed when
87 * the Line Control Register is set to 0xBFh.
89 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
91 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
93 /* Turn on CTS flow control, turn off IXON flow control */
94 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
95 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
97 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
99 /* Write old LCR value back out, which turns enhanced access off */
100 writeb(lcrb, &ch->ch_cls_uart->lcr);
103 * Enable interrupts for CTS flow, turn off interrupts for
104 * received XOFF chars
106 ier |= (UART_EXAR654_IER_CTSDSR);
107 ier &= ~(UART_EXAR654_IER_XOFF);
108 writeb(ier, &ch->ch_cls_uart->ier);
110 /* Set the usual FIFO values */
111 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
113 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
114 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
115 &ch->ch_cls_uart->isr_fcr);
117 ch->ch_t_tlevel = 16;
121 static inline void cls_set_ixon_flow_control(struct channel_t *ch)
123 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
124 unsigned char ier = readb(&ch->ch_cls_uart->ier);
125 unsigned char isr_fcr = 0;
128 * The Enhanced Register Set may only be accessed when
129 * the Line Control Register is set to 0xBFh.
131 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
133 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
135 /* Turn on IXON flow control, turn off CTS flow control */
136 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
137 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
139 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
141 /* Now set our current start/stop chars while in enhanced mode */
142 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
143 writeb(0, &ch->ch_cls_uart->lsr);
144 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
145 writeb(0, &ch->ch_cls_uart->spr);
147 /* Write old LCR value back out, which turns enhanced access off */
148 writeb(lcrb, &ch->ch_cls_uart->lcr);
151 * Disable interrupts for CTS flow, turn on interrupts for
152 * received XOFF chars
154 ier &= ~(UART_EXAR654_IER_CTSDSR);
155 ier |= (UART_EXAR654_IER_XOFF);
156 writeb(ier, &ch->ch_cls_uart->ier);
158 /* Set the usual FIFO values */
159 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
161 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
162 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
163 &ch->ch_cls_uart->isr_fcr);
167 static inline void cls_set_no_output_flow_control(struct channel_t *ch)
169 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
170 unsigned char ier = readb(&ch->ch_cls_uart->ier);
171 unsigned char isr_fcr = 0;
174 * The Enhanced Register Set may only be accessed when
175 * the Line Control Register is set to 0xBFh.
177 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
179 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
181 /* Turn off IXON flow control, turn off CTS flow control */
182 isr_fcr |= (UART_EXAR654_EFR_ECB);
183 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
185 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
187 /* Write old LCR value back out, which turns enhanced access off */
188 writeb(lcrb, &ch->ch_cls_uart->lcr);
191 * Disable interrupts for CTS flow, turn off interrupts for
192 * received XOFF chars
194 ier &= ~(UART_EXAR654_IER_CTSDSR);
195 ier &= ~(UART_EXAR654_IER_XOFF);
196 writeb(ier, &ch->ch_cls_uart->ier);
198 /* Set the usual FIFO values */
199 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
201 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
202 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
203 &ch->ch_cls_uart->isr_fcr);
205 ch->ch_r_watermark = 0;
206 ch->ch_t_tlevel = 16;
207 ch->ch_r_tlevel = 16;
211 static inline void cls_set_rts_flow_control(struct channel_t *ch)
213 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
214 unsigned char ier = readb(&ch->ch_cls_uart->ier);
215 unsigned char isr_fcr = 0;
218 * The Enhanced Register Set may only be accessed when
219 * the Line Control Register is set to 0xBFh.
221 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
223 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
225 /* Turn on RTS flow control, turn off IXOFF flow control */
226 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
227 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
229 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
231 /* Write old LCR value back out, which turns enhanced access off */
232 writeb(lcrb, &ch->ch_cls_uart->lcr);
234 /* Enable interrupts for RTS flow */
235 ier |= (UART_EXAR654_IER_RTSDTR);
236 writeb(ier, &ch->ch_cls_uart->ier);
238 /* Set the usual FIFO values */
239 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
241 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
242 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
243 &ch->ch_cls_uart->isr_fcr);
245 ch->ch_r_watermark = 4;
250 static inline void cls_set_ixoff_flow_control(struct channel_t *ch)
252 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
253 unsigned char ier = readb(&ch->ch_cls_uart->ier);
254 unsigned char isr_fcr = 0;
257 * The Enhanced Register Set may only be accessed when
258 * the Line Control Register is set to 0xBFh.
260 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
262 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
264 /* Turn on IXOFF flow control, turn off RTS flow control */
265 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
266 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
268 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
270 /* Now set our current start/stop chars while in enhanced mode */
271 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
272 writeb(0, &ch->ch_cls_uart->lsr);
273 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
274 writeb(0, &ch->ch_cls_uart->spr);
276 /* Write old LCR value back out, which turns enhanced access off */
277 writeb(lcrb, &ch->ch_cls_uart->lcr);
279 /* Disable interrupts for RTS flow */
280 ier &= ~(UART_EXAR654_IER_RTSDTR);
281 writeb(ier, &ch->ch_cls_uart->ier);
283 /* Set the usual FIFO values */
284 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
286 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
287 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
288 &ch->ch_cls_uart->isr_fcr);
292 static inline void cls_set_no_input_flow_control(struct channel_t *ch)
294 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
295 unsigned char ier = readb(&ch->ch_cls_uart->ier);
296 unsigned char isr_fcr = 0;
299 * The Enhanced Register Set may only be accessed when
300 * the Line Control Register is set to 0xBFh.
302 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
304 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
306 /* Turn off IXOFF flow control, turn off RTS flow control */
307 isr_fcr |= (UART_EXAR654_EFR_ECB);
308 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
310 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
312 /* Write old LCR value back out, which turns enhanced access off */
313 writeb(lcrb, &ch->ch_cls_uart->lcr);
315 /* Disable interrupts for RTS flow */
316 ier &= ~(UART_EXAR654_IER_RTSDTR);
317 writeb(ier, &ch->ch_cls_uart->ier);
319 /* Set the usual FIFO values */
320 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
322 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
323 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
324 &ch->ch_cls_uart->isr_fcr);
326 ch->ch_t_tlevel = 16;
327 ch->ch_r_tlevel = 16;
333 * Determines whether its time to shut off break condition.
335 * No locks are assumed to be held when calling this function.
336 * channel lock is held and released in this function.
338 static inline void cls_clear_break(struct channel_t *ch, int force)
342 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
345 spin_lock_irqsave(&ch->ch_lock, flags);
347 /* Bail if we aren't currently sending a break. */
348 if (!ch->ch_stop_sending_break) {
349 spin_unlock_irqrestore(&ch->ch_lock, flags);
353 /* Turn break off, and unset some variables */
354 if (ch->ch_flags & CH_BREAK_SENDING) {
355 if (time_after(jiffies, ch->ch_stop_sending_break) || force) {
356 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
358 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
359 ch->ch_flags &= ~(CH_BREAK_SENDING);
360 ch->ch_stop_sending_break = 0;
363 spin_unlock_irqrestore(&ch->ch_lock, flags);
366 /* Parse the ISR register for the specific port */
367 static inline void cls_parse_isr(struct dgnc_board *brd, uint port)
369 struct channel_t *ch;
370 unsigned char isr = 0;
374 * No need to verify board pointer, it was already
375 * verified in the interrupt routine.
378 if (port >= brd->nasync)
381 ch = brd->channels[port];
382 if (ch->magic != DGNC_CHANNEL_MAGIC)
385 /* Here we try to figure out what caused the interrupt to happen */
388 isr = readb(&ch->ch_cls_uart->isr_fcr);
390 /* Bail if no pending interrupt on port */
391 if (isr & UART_IIR_NO_INT)
394 /* Receive Interrupt pending */
395 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
396 /* Read data from uart -> queue */
399 cls_copy_data_from_uart_to_queue(ch);
400 dgnc_check_queue_flow_control(ch);
403 /* Transmit Hold register empty pending */
404 if (isr & UART_IIR_THRI) {
405 /* Transfer data (if any) from Write Queue -> UART. */
406 spin_lock_irqsave(&ch->ch_lock, flags);
407 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
410 spin_unlock_irqrestore(&ch->ch_lock, flags);
411 cls_copy_data_from_queue_to_uart(ch);
414 /* CTS/RTS change of state */
415 if (isr & UART_IIR_CTSRTS) {
419 * Don't need to do anything, the cls_parse_modem
420 * below will grab the updated modem signals.
424 /* Parse any modem signal changes */
425 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
431 * Send any/all changes to the line to the UART.
433 static void cls_param(struct tty_struct *tty)
435 unsigned char lcr = 0;
436 unsigned char uart_lcr = 0;
437 unsigned char ier = 0;
438 unsigned char uart_ier = 0;
441 struct dgnc_board *bd;
442 struct channel_t *ch;
445 if (!tty || tty->magic != TTY_MAGIC)
448 un = (struct un_t *) tty->driver_data;
449 if (!un || un->magic != DGNC_UNIT_MAGIC)
453 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
457 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
461 * If baud rate is zero, flush queues, and set mval to drop DTR.
463 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
471 cls_flush_uart_write(ch);
472 cls_flush_uart_read(ch);
474 /* The baudrate is B0 so all modem lines are to be dropped. */
475 ch->ch_flags |= (CH_BAUD0);
476 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
477 cls_assert_modem_signals(ch);
480 } else if (ch->ch_custom_speed) {
482 baud = ch->ch_custom_speed;
483 /* Handle transition from B0 */
484 if (ch->ch_flags & CH_BAUD0) {
485 ch->ch_flags &= ~(CH_BAUD0);
488 * Bring back up RTS and DTR...
489 * Also handle RTS or DTR toggle if set.
491 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
492 ch->ch_mostat |= (UART_MCR_RTS);
493 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
494 ch->ch_mostat |= (UART_MCR_DTR);
501 ulong bauds[4][16] = {
505 600, 1200, 1800, 2400,
506 4800, 9600, 19200, 38400 },
507 { /* slowbaud & CBAUDEX */
508 0, 57600, 115200, 230400,
509 460800, 150, 200, 921600,
510 600, 1200, 1800, 2400,
511 4800, 9600, 19200, 38400 },
513 0, 57600, 76800, 115200,
514 131657, 153600, 230400, 460800,
515 921600, 1200, 1800, 2400,
516 4800, 9600, 19200, 38400 },
517 { /* fastbaud & CBAUDEX */
518 0, 57600, 115200, 230400,
519 460800, 150, 200, 921600,
520 600, 1200, 1800, 2400,
521 4800, 9600, 19200, 38400 }
525 * Only use the TXPrint baud rate if the terminal
528 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
529 (un->un_type == DGNC_PRINT))
530 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
532 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
534 if (ch->ch_c_cflag & CBAUDEX)
537 if (ch->ch_digi.digi_flags & DIGI_FAST)
542 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) &&
544 baud = bauds[iindex][jindex];
552 /* Handle transition from B0 */
553 if (ch->ch_flags & CH_BAUD0) {
554 ch->ch_flags &= ~(CH_BAUD0);
557 * Bring back up RTS and DTR...
558 * Also handle RTS or DTR toggle if set.
560 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
561 ch->ch_mostat |= (UART_MCR_RTS);
562 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
563 ch->ch_mostat |= (UART_MCR_DTR);
567 if (ch->ch_c_cflag & PARENB)
568 lcr |= UART_LCR_PARITY;
570 if (!(ch->ch_c_cflag & PARODD))
571 lcr |= UART_LCR_EPAR;
574 * Not all platforms support mark/space parity,
575 * so this will hide behind an ifdef.
578 if (ch->ch_c_cflag & CMSPAR)
579 lcr |= UART_LCR_SPAR;
582 if (ch->ch_c_cflag & CSTOPB)
583 lcr |= UART_LCR_STOP;
585 switch (ch->ch_c_cflag & CSIZE) {
587 lcr |= UART_LCR_WLEN5;
590 lcr |= UART_LCR_WLEN6;
593 lcr |= UART_LCR_WLEN7;
597 lcr |= UART_LCR_WLEN8;
601 uart_ier = readb(&ch->ch_cls_uart->ier);
603 uart_lcr = readb(&ch->ch_cls_uart->lcr);
608 quot = ch->ch_bd->bd_dividend / baud;
610 if (quot != 0 && ch->ch_old_baud != baud) {
611 ch->ch_old_baud = baud;
612 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
613 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
614 writeb((quot >> 8), &ch->ch_cls_uart->ier);
615 writeb(lcr, &ch->ch_cls_uart->lcr);
619 writeb(lcr, &ch->ch_cls_uart->lcr);
621 if (ch->ch_c_cflag & CREAD)
622 ier |= (UART_IER_RDI | UART_IER_RLSI);
624 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
627 * Have the UART interrupt on modem signal changes ONLY when
628 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
630 if ((ch->ch_digi.digi_flags & CTSPACE) ||
631 (ch->ch_digi.digi_flags & RTSPACE) ||
632 (ch->ch_c_cflag & CRTSCTS) ||
633 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
634 !(ch->ch_c_cflag & CLOCAL))
637 ier &= ~UART_IER_MSI;
639 ier |= UART_IER_THRI;
642 writeb(ier, &ch->ch_cls_uart->ier);
644 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
645 cls_set_cts_flow_control(ch);
646 } else if (ch->ch_c_iflag & IXON) {
648 * If start/stop is set to disable, then we should
649 * disable flow control
651 if ((ch->ch_startc == _POSIX_VDISABLE) ||
652 (ch->ch_stopc == _POSIX_VDISABLE))
653 cls_set_no_output_flow_control(ch);
655 cls_set_ixon_flow_control(ch);
657 cls_set_no_output_flow_control(ch);
660 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
661 cls_set_rts_flow_control(ch);
662 } else if (ch->ch_c_iflag & IXOFF) {
664 * If start/stop is set to disable, then we should disable
667 if ((ch->ch_startc == _POSIX_VDISABLE) ||
668 (ch->ch_stopc == _POSIX_VDISABLE))
669 cls_set_no_input_flow_control(ch);
671 cls_set_ixoff_flow_control(ch);
673 cls_set_no_input_flow_control(ch);
676 cls_assert_modem_signals(ch);
678 /* Get current status of the modem signals now */
679 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
683 * Our board poller function.
685 static void cls_tasklet(unsigned long data)
687 struct dgnc_board *bd = (struct dgnc_board *) data;
688 struct channel_t *ch;
694 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
697 /* Cache a couple board values */
698 spin_lock_irqsave(&bd->bd_lock, flags);
701 spin_unlock_irqrestore(&bd->bd_lock, flags);
704 * Do NOT allow the interrupt routine to read the intr registers
705 * Until we release this lock.
707 spin_lock_irqsave(&bd->bd_intr_lock, flags);
710 * If board is ready, parse deeper to see if there is anything to do.
712 if ((state == BOARD_READY) && (ports > 0)) {
714 /* Loop on each port */
715 for (i = 0; i < ports; i++) {
716 ch = bd->channels[i];
719 * NOTE: Remember you CANNOT hold any channel
720 * locks when calling input.
721 * During input processing, its possible we
722 * will call ld, which might do callbacks back
728 * Channel lock is grabbed and then released
729 * inside this routine.
731 cls_copy_data_from_queue_to_uart(ch);
732 dgnc_wakeup_writes(ch);
735 * Check carrier function.
740 * The timing check of turning off the break is done
741 * inside clear_break()
743 if (ch->ch_stop_sending_break)
744 cls_clear_break(ch, 0);
748 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
755 * Classic specific interrupt handler.
757 static irqreturn_t cls_intr(int irq, void *voidbrd)
759 struct dgnc_board *brd = voidbrd;
761 unsigned char poll_reg;
765 * Check to make sure it didn't receive interrupt with a null board
766 * associated or a board pointer that wasn't ours.
768 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
771 spin_lock_irqsave(&brd->bd_intr_lock, flags);
776 * Check the board's global interrupt offset to see if we
777 * we actually do have an interrupt pending for us.
779 poll_reg = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
781 /* If 0, no interrupts pending */
783 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
787 /* Parse each port to find out what caused the interrupt */
788 for (i = 0; i < brd->nasync; i++)
789 cls_parse_isr(brd, i);
792 * Schedule tasklet to more in-depth servicing at a better time.
794 tasklet_schedule(&brd->helper_tasklet);
796 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
801 static void cls_disable_receiver(struct channel_t *ch)
803 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
805 tmp &= ~(UART_IER_RDI);
806 writeb(tmp, &ch->ch_cls_uart->ier);
809 static void cls_enable_receiver(struct channel_t *ch)
811 unsigned char tmp = readb(&ch->ch_cls_uart->ier);
813 tmp |= (UART_IER_RDI);
814 writeb(tmp, &ch->ch_cls_uart->ier);
817 static void cls_copy_data_from_uart_to_queue(struct channel_t *ch)
820 unsigned char linestatus = 0;
821 unsigned char error_mask = 0;
826 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
829 spin_lock_irqsave(&ch->ch_lock, flags);
831 /* cache head and tail of queue */
832 head = ch->ch_r_head;
833 tail = ch->ch_r_tail;
835 /* Store how much space we have left in the queue */
836 qleft = (tail - head - 1);
838 qleft += RQUEUEMASK + 1;
841 * Create a mask to determine whether we should
842 * insert the character (if any) into our queue.
844 if (ch->ch_c_iflag & IGNBRK)
845 error_mask |= UART_LSR_BI;
848 linestatus = readb(&ch->ch_cls_uart->lsr);
850 if (!(linestatus & (UART_LSR_DR)))
854 * Discard character if we are ignoring the error mask.
856 if (linestatus & error_mask) {
857 unsigned char discard;
860 discard = readb(&ch->ch_cls_uart->txrx);
865 * If our queue is full, we have no choice but to drop some
866 * data. The assumption is that HWFLOW or SWFLOW should have
867 * stopped things way way before we got to this point.
869 * I decided that I wanted to ditch the oldest data first,
870 * I hope thats okay with everyone? Yes? Good.
873 tail = (tail + 1) & RQUEUEMASK;
874 ch->ch_r_tail = tail;
875 ch->ch_err_overrun++;
879 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
881 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
885 if (ch->ch_equeue[head] & UART_LSR_PE)
887 if (ch->ch_equeue[head] & UART_LSR_BI)
889 if (ch->ch_equeue[head] & UART_LSR_FE)
892 /* Add to, and flip head if needed */
893 head = (head + 1) & RQUEUEMASK;
898 * Write new final heads to channel structure.
900 ch->ch_r_head = head & RQUEUEMASK;
901 ch->ch_e_head = head & EQUEUEMASK;
903 spin_unlock_irqrestore(&ch->ch_lock, flags);
907 * This function basically goes to sleep for secs, or until
908 * it gets signalled that the port has fully drained.
910 static int cls_drain(struct tty_struct *tty, uint seconds)
913 struct channel_t *ch;
916 if (!tty || tty->magic != TTY_MAGIC)
919 un = (struct un_t *) tty->driver_data;
920 if (!un || un->magic != DGNC_UNIT_MAGIC)
924 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
927 spin_lock_irqsave(&ch->ch_lock, flags);
928 un->un_flags |= UN_EMPTY;
929 spin_unlock_irqrestore(&ch->ch_lock, flags);
932 * NOTE: Do something with time passed in.
935 /* If ret is non-zero, user ctrl-c'ed us */
937 return wait_event_interruptible(un->un_flags_wait,
938 ((un->un_flags & UN_EMPTY) == 0));
941 /* Channel lock MUST be held before calling this function! */
942 static void cls_flush_uart_write(struct channel_t *ch)
944 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
947 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
948 &ch->ch_cls_uart->isr_fcr);
951 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
954 /* Channel lock MUST be held before calling this function! */
955 static void cls_flush_uart_read(struct channel_t *ch)
957 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
961 * For complete POSIX compatibility, we should be purging the
962 * read FIFO in the UART here.
964 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
965 * incorrectly flushes write data as well as just basically trashing the
968 * Presumably, this is a bug in this UART.
974 static void cls_copy_data_from_queue_to_uart(struct channel_t *ch)
980 uint len_written = 0;
983 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
986 spin_lock_irqsave(&ch->ch_lock, flags);
988 /* No data to write to the UART */
989 if (ch->ch_w_tail == ch->ch_w_head)
992 /* If port is "stopped", don't send any data to the UART */
993 if ((ch->ch_flags & CH_FORCED_STOP) ||
994 (ch->ch_flags & CH_BREAK_SENDING))
997 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1002 /* cache head and tail of queue */
1003 head = ch->ch_w_head & WQUEUEMASK;
1004 tail = ch->ch_w_tail & WQUEUEMASK;
1005 qlen = (head - tail) & WQUEUEMASK;
1007 /* Find minimum of the FIFO space, versus queue length */
1013 * If RTS Toggle mode is on, turn on RTS now if not already set,
1014 * and make sure we get an event when the data transfer has
1017 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1018 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1019 ch->ch_mostat |= (UART_MCR_RTS);
1020 cls_assert_modem_signals(ch);
1022 ch->ch_tun.un_flags |= (UN_EMPTY);
1026 * If DTR Toggle mode is on, turn on DTR now if not already set,
1027 * and make sure we get an event when the data transfer has
1030 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1031 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1032 ch->ch_mostat |= (UART_MCR_DTR);
1033 cls_assert_modem_signals(ch);
1035 ch->ch_tun.un_flags |= (UN_EMPTY);
1037 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_cls_uart->txrx);
1039 ch->ch_w_tail &= WQUEUEMASK;
1045 if (len_written > 0)
1046 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1049 spin_unlock_irqrestore(&ch->ch_lock, flags);
1052 static void cls_parse_modem(struct channel_t *ch, unsigned char signals)
1054 unsigned char msignals = signals;
1055 unsigned long flags;
1057 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1061 * Do altpin switching. Altpin switches DCD and DSR.
1062 * This prolly breaks DSRPACE, so we should be more clever here.
1064 spin_lock_irqsave(&ch->ch_lock, flags);
1065 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1066 unsigned char mswap = signals;
1068 if (mswap & UART_MSR_DDCD) {
1069 msignals &= ~UART_MSR_DDCD;
1070 msignals |= UART_MSR_DDSR;
1072 if (mswap & UART_MSR_DDSR) {
1073 msignals &= ~UART_MSR_DDSR;
1074 msignals |= UART_MSR_DDCD;
1076 if (mswap & UART_MSR_DCD) {
1077 msignals &= ~UART_MSR_DCD;
1078 msignals |= UART_MSR_DSR;
1080 if (mswap & UART_MSR_DSR) {
1081 msignals &= ~UART_MSR_DSR;
1082 msignals |= UART_MSR_DCD;
1085 spin_unlock_irqrestore(&ch->ch_lock, flags);
1088 * Scrub off lower bits. They signify delta's, which I don't
1093 spin_lock_irqsave(&ch->ch_lock, flags);
1094 if (msignals & UART_MSR_DCD)
1095 ch->ch_mistat |= UART_MSR_DCD;
1097 ch->ch_mistat &= ~UART_MSR_DCD;
1099 if (msignals & UART_MSR_DSR)
1100 ch->ch_mistat |= UART_MSR_DSR;
1102 ch->ch_mistat &= ~UART_MSR_DSR;
1104 if (msignals & UART_MSR_RI)
1105 ch->ch_mistat |= UART_MSR_RI;
1107 ch->ch_mistat &= ~UART_MSR_RI;
1109 if (msignals & UART_MSR_CTS)
1110 ch->ch_mistat |= UART_MSR_CTS;
1112 ch->ch_mistat &= ~UART_MSR_CTS;
1113 spin_unlock_irqrestore(&ch->ch_lock, flags);
1116 /* Make the UART raise any of the output signals we want up */
1117 static void cls_assert_modem_signals(struct channel_t *ch)
1121 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1124 out = ch->ch_mostat;
1126 if (ch->ch_flags & CH_LOOPBACK)
1127 out |= UART_MCR_LOOP;
1129 writeb(out, &ch->ch_cls_uart->mcr);
1131 /* Give time for the UART to actually drop the signals */
1135 static void cls_send_start_character(struct channel_t *ch)
1137 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1140 if (ch->ch_startc != _POSIX_VDISABLE) {
1142 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
1146 static void cls_send_stop_character(struct channel_t *ch)
1148 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1151 if (ch->ch_stopc != _POSIX_VDISABLE) {
1152 ch->ch_xoff_sends++;
1153 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
1158 static void cls_uart_init(struct channel_t *ch)
1160 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
1161 unsigned char isr_fcr = 0;
1163 writeb(0, &ch->ch_cls_uart->ier);
1166 * The Enhanced Register Set may only be accessed when
1167 * the Line Control Register is set to 0xBFh.
1169 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
1171 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
1173 /* Turn on Enhanced/Extended controls */
1174 isr_fcr |= (UART_EXAR654_EFR_ECB);
1176 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
1178 /* Write old LCR value back out, which turns enhanced access off */
1179 writeb(lcrb, &ch->ch_cls_uart->lcr);
1181 /* Clear out UART and FIFO */
1182 readb(&ch->ch_cls_uart->txrx);
1184 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
1185 &ch->ch_cls_uart->isr_fcr);
1188 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1190 readb(&ch->ch_cls_uart->lsr);
1191 readb(&ch->ch_cls_uart->msr);
1197 static void cls_uart_off(struct channel_t *ch)
1199 writeb(0, &ch->ch_cls_uart->ier);
1203 * cls_get_uarts_bytes_left.
1204 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
1206 * The channel lock MUST be held by the calling function.
1208 static uint cls_get_uart_bytes_left(struct channel_t *ch)
1210 unsigned char left = 0;
1211 unsigned char lsr = 0;
1213 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1216 lsr = readb(&ch->ch_cls_uart->lsr);
1218 /* Determine whether the Transmitter is empty or not */
1219 if (!(lsr & UART_LSR_TEMT)) {
1220 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1221 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1224 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1233 * Starts sending a break thru the UART.
1235 * The channel lock MUST be held by the calling function.
1237 static void cls_send_break(struct channel_t *ch, int msecs)
1239 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1243 * If we receive a time of 0, this means turn off the break.
1246 /* Turn break off, and unset some variables */
1247 if (ch->ch_flags & CH_BREAK_SENDING) {
1248 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1250 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1251 ch->ch_flags &= ~(CH_BREAK_SENDING);
1252 ch->ch_stop_sending_break = 0;
1258 * Set the time we should stop sending the break.
1259 * If we are already sending a break, toss away the existing
1260 * time to stop, and use this new value instead.
1262 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1264 /* Tell the UART to start sending the break */
1265 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1266 unsigned char temp = readb(&ch->ch_cls_uart->lcr);
1268 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
1269 ch->ch_flags |= (CH_BREAK_SENDING);
1274 * cls_send_immediate_char.
1275 * Sends a specific character as soon as possible to the UART,
1276 * jumping over any bytes that might be in the write queue.
1278 * The channel lock MUST be held by the calling function.
1280 static void cls_send_immediate_char(struct channel_t *ch, unsigned char c)
1282 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1285 writeb(c, &ch->ch_cls_uart->txrx);
1288 static void cls_vpd(struct dgnc_board *brd)
1290 ulong vpdbase; /* Start of io base of the card */
1291 u8 __iomem *re_map_vpdbase;/* Remapped memory of the card */
1294 vpdbase = pci_resource_start(brd->pdev, 3);
1300 re_map_vpdbase = ioremap(vpdbase, 0x400);
1302 if (!re_map_vpdbase)
1305 /* Store the VPD into our buffer */
1306 for (i = 0; i < 0x40; i++) {
1307 brd->vpd[i] = readb(re_map_vpdbase + i);
1308 pr_info("%x ", brd->vpd[i]);
1313 iounmap(re_map_vpdbase);