2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h> /* For jiffies, task states */
18 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19 #include <linux/delay.h> /* For udelay */
20 #include <linux/io.h> /* For read[bwl]/write[bwl] */
21 #include <linux/serial.h> /* For struct async_serial */
22 #include <linux/serial_reg.h> /* For the various UART offsets */
24 #include "dgnc_driver.h" /* Driver main header file */
25 #include "dgnc_neo.h" /* Our header file */
28 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31 static inline void neo_clear_break(struct channel_t *ch, int force);
32 static inline void neo_set_cts_flow_control(struct channel_t *ch);
33 static inline void neo_set_rts_flow_control(struct channel_t *ch);
34 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40 static void neo_tasklet(unsigned long data);
41 static void neo_vpd(struct dgnc_board *brd);
42 static void neo_uart_init(struct channel_t *ch);
43 static void neo_uart_off(struct channel_t *ch);
44 static int neo_drain(struct tty_struct *tty, uint seconds);
45 static void neo_param(struct tty_struct *tty);
46 static void neo_assert_modem_signals(struct channel_t *ch);
47 static void neo_flush_uart_write(struct channel_t *ch);
48 static void neo_flush_uart_read(struct channel_t *ch);
49 static void neo_disable_receiver(struct channel_t *ch);
50 static void neo_enable_receiver(struct channel_t *ch);
51 static void neo_send_break(struct channel_t *ch, int msecs);
52 static void neo_send_start_character(struct channel_t *ch);
53 static void neo_send_stop_character(struct channel_t *ch);
54 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55 static uint neo_get_uart_bytes_left(struct channel_t *ch);
56 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57 static irqreturn_t neo_intr(int irq, void *voidbrd);
59 struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
81 * This function allows calls to ensure that all outstanding
82 * PCI writes have been completed, by doing a PCI read against
83 * a non-destructive, read-only location on the Neo card.
85 * In this case, we are reading the DVID (Read-only Device Identification)
86 * value of the Neo card.
88 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
90 readb(bd->re_map_membase + 0x8D);
93 static inline void neo_set_cts_flow_control(struct channel_t *ch)
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
98 /* Turn on auto CTS flow control */
100 ier |= UART_17158_IER_CTSDSR;
102 ier &= ~(UART_17158_IER_CTSDSR);
105 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
107 /* Turn off auto Xon flow control */
108 efr &= ~UART_17158_EFR_IXON;
111 * Why? Because Exar's spec says we have to zero it
112 * out before setting it
114 writeb(0, &ch->ch_neo_uart->efr);
116 /* Turn on UART enhanced bits */
117 writeb(efr, &ch->ch_neo_uart->efr);
119 /* Turn on table D, with 8 char hi/low watermarks */
120 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
121 &ch->ch_neo_uart->fctr);
123 /* Feed the UART our trigger levels */
124 writeb(8, &ch->ch_neo_uart->tfifo);
127 writeb(ier, &ch->ch_neo_uart->ier);
129 neo_pci_posting_flush(ch->ch_bd);
132 static inline void neo_set_rts_flow_control(struct channel_t *ch)
134 unsigned char ier = readb(&ch->ch_neo_uart->ier);
135 unsigned char efr = readb(&ch->ch_neo_uart->efr);
137 /* Turn on auto RTS flow control */
139 ier |= UART_17158_IER_RTSDTR;
141 ier &= ~(UART_17158_IER_RTSDTR);
143 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
145 /* Turn off auto Xoff flow control */
146 ier &= ~UART_17158_IER_XOFF;
147 efr &= ~UART_17158_EFR_IXOFF;
150 * Why? Because Exar's spec says we have to zero it
151 * out before setting it
153 writeb(0, &ch->ch_neo_uart->efr);
155 /* Turn on UART enhanced bits */
156 writeb(efr, &ch->ch_neo_uart->efr);
158 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
159 &ch->ch_neo_uart->fctr);
160 ch->ch_r_watermark = 4;
162 writeb(32, &ch->ch_neo_uart->rfifo);
163 ch->ch_r_tlevel = 32;
165 writeb(ier, &ch->ch_neo_uart->ier);
168 * From the Neo UART spec sheet:
169 * The auto RTS/DTR function must be started by asserting
170 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
173 ch->ch_mostat |= UART_MCR_RTS;
175 neo_pci_posting_flush(ch->ch_bd);
178 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
180 unsigned char ier = readb(&ch->ch_neo_uart->ier);
181 unsigned char efr = readb(&ch->ch_neo_uart->efr);
183 /* Turn off auto CTS flow control */
184 ier &= ~UART_17158_IER_CTSDSR;
185 efr &= ~UART_17158_EFR_CTSDSR;
187 /* Turn on auto Xon flow control */
188 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
191 * Why? Because Exar's spec says we have to zero it
192 * out before setting it
194 writeb(0, &ch->ch_neo_uart->efr);
196 /* Turn on UART enhanced bits */
197 writeb(efr, &ch->ch_neo_uart->efr);
199 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
200 &ch->ch_neo_uart->fctr);
201 ch->ch_r_watermark = 4;
203 writeb(32, &ch->ch_neo_uart->rfifo);
204 ch->ch_r_tlevel = 32;
206 /* Tell UART what start/stop chars it should be looking for */
207 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
208 writeb(0, &ch->ch_neo_uart->xonchar2);
210 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
211 writeb(0, &ch->ch_neo_uart->xoffchar2);
213 writeb(ier, &ch->ch_neo_uart->ier);
215 neo_pci_posting_flush(ch->ch_bd);
218 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
220 unsigned char ier = readb(&ch->ch_neo_uart->ier);
221 unsigned char efr = readb(&ch->ch_neo_uart->efr);
223 /* Turn off auto RTS flow control */
224 ier &= ~UART_17158_IER_RTSDTR;
225 efr &= ~UART_17158_EFR_RTSDTR;
227 /* Turn on auto Xoff flow control */
228 ier |= UART_17158_IER_XOFF;
229 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
232 * Why? Because Exar's spec says we have to zero it
233 * out before setting it
235 writeb(0, &ch->ch_neo_uart->efr);
237 /* Turn on UART enhanced bits */
238 writeb(efr, &ch->ch_neo_uart->efr);
240 /* Turn on table D, with 8 char hi/low watermarks */
241 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
242 &ch->ch_neo_uart->fctr);
244 writeb(8, &ch->ch_neo_uart->tfifo);
247 /* Tell UART what start/stop chars it should be looking for */
248 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
249 writeb(0, &ch->ch_neo_uart->xonchar2);
251 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
252 writeb(0, &ch->ch_neo_uart->xoffchar2);
254 writeb(ier, &ch->ch_neo_uart->ier);
256 neo_pci_posting_flush(ch->ch_bd);
259 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
261 unsigned char ier = readb(&ch->ch_neo_uart->ier);
262 unsigned char efr = readb(&ch->ch_neo_uart->efr);
264 /* Turn off auto RTS flow control */
265 ier &= ~UART_17158_IER_RTSDTR;
266 efr &= ~UART_17158_EFR_RTSDTR;
268 /* Turn off auto Xoff flow control */
269 ier &= ~UART_17158_IER_XOFF;
270 if (ch->ch_c_iflag & IXON)
271 efr &= ~(UART_17158_EFR_IXOFF);
273 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
276 * Why? Because Exar's spec says we have to zero
277 * it out before setting it
279 writeb(0, &ch->ch_neo_uart->efr);
281 /* Turn on UART enhanced bits */
282 writeb(efr, &ch->ch_neo_uart->efr);
284 /* Turn on table D, with 8 char hi/low watermarks */
285 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
286 &ch->ch_neo_uart->fctr);
288 ch->ch_r_watermark = 0;
290 writeb(16, &ch->ch_neo_uart->tfifo);
291 ch->ch_t_tlevel = 16;
293 writeb(16, &ch->ch_neo_uart->rfifo);
294 ch->ch_r_tlevel = 16;
296 writeb(ier, &ch->ch_neo_uart->ier);
298 neo_pci_posting_flush(ch->ch_bd);
301 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
303 unsigned char ier = readb(&ch->ch_neo_uart->ier);
304 unsigned char efr = readb(&ch->ch_neo_uart->efr);
306 /* Turn off auto CTS flow control */
307 ier &= ~UART_17158_IER_CTSDSR;
308 efr &= ~UART_17158_EFR_CTSDSR;
310 /* Turn off auto Xon flow control */
311 if (ch->ch_c_iflag & IXOFF)
312 efr &= ~UART_17158_EFR_IXON;
314 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
317 * Why? Because Exar's spec says we have to zero it
318 * out before setting it
320 writeb(0, &ch->ch_neo_uart->efr);
322 /* Turn on UART enhanced bits */
323 writeb(efr, &ch->ch_neo_uart->efr);
325 /* Turn on table D, with 8 char hi/low watermarks */
326 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
327 &ch->ch_neo_uart->fctr);
329 ch->ch_r_watermark = 0;
331 writeb(16, &ch->ch_neo_uart->tfifo);
332 ch->ch_t_tlevel = 16;
334 writeb(16, &ch->ch_neo_uart->rfifo);
335 ch->ch_r_tlevel = 16;
337 writeb(ier, &ch->ch_neo_uart->ier);
339 neo_pci_posting_flush(ch->ch_bd);
342 /* change UARTs start/stop chars */
343 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
345 /* if hardware flow control is set, then skip this whole thing */
346 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
347 ch->ch_c_cflag & CRTSCTS)
350 /* Tell UART what start/stop chars it should be looking for */
351 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
352 writeb(0, &ch->ch_neo_uart->xonchar2);
354 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
355 writeb(0, &ch->ch_neo_uart->xoffchar2);
357 neo_pci_posting_flush(ch->ch_bd);
360 /* No locks are assumed to be held when calling this function. */
362 static inline void neo_clear_break(struct channel_t *ch, int force)
366 spin_lock_irqsave(&ch->ch_lock, flags);
368 /* Bail if we aren't currently sending a break. */
369 if (!ch->ch_stop_sending_break) {
370 spin_unlock_irqrestore(&ch->ch_lock, flags);
374 /* Turn break off, and unset some variables */
375 if (ch->ch_flags & CH_BREAK_SENDING) {
377 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
378 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
380 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
381 neo_pci_posting_flush(ch->ch_bd);
382 ch->ch_flags &= ~(CH_BREAK_SENDING);
383 ch->ch_stop_sending_break = 0;
386 spin_unlock_irqrestore(&ch->ch_lock, flags);
389 /* Parse the ISR register. */
391 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
393 struct channel_t *ch;
398 ch = brd->channels[port];
399 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
402 /* Here we try to figure out what caused the interrupt to happen */
404 isr = readb(&ch->ch_neo_uart->isr_fcr);
406 /* Bail if no pending interrupt */
407 if (isr & UART_IIR_NO_INT)
411 * Yank off the upper 2 bits,
412 * which just show that the FIFO's are enabled.
414 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
416 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
417 /* Read data from uart -> queue */
418 neo_copy_data_from_uart_to_queue(ch);
420 * Call our tty layer to enforce queue
421 * flow control if needed.
423 spin_lock_irqsave(&ch->ch_lock, flags);
424 dgnc_check_queue_flow_control(ch);
425 spin_unlock_irqrestore(&ch->ch_lock, flags);
428 if (isr & UART_IIR_THRI) {
429 /* Transfer data (if any) from Write Queue -> UART. */
430 spin_lock_irqsave(&ch->ch_lock, flags);
431 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
432 spin_unlock_irqrestore(&ch->ch_lock, flags);
433 neo_copy_data_from_queue_to_uart(ch);
436 if (isr & UART_17158_IIR_XONXOFF) {
437 cause = readb(&ch->ch_neo_uart->xoffchar1);
440 * Since the UART detected either an XON or
441 * XOFF match, we need to figure out which
442 * one it was, so we can suspend or resume data flow.
444 if (cause == UART_17158_XON_DETECT) {
446 * Is output stopped right now, if so,
449 if (brd->channels[port]->ch_flags & CH_STOP) {
450 spin_lock_irqsave(&ch->ch_lock,
452 ch->ch_flags &= ~(CH_STOP);
453 spin_unlock_irqrestore(&ch->ch_lock,
456 } else if (cause == UART_17158_XOFF_DETECT) {
457 if (!(brd->channels[port]->ch_flags &
459 spin_lock_irqsave(&ch->ch_lock,
461 ch->ch_flags |= CH_STOP;
462 spin_unlock_irqrestore(&ch->ch_lock,
468 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
470 * If we get here, this means the hardware is
471 * doing auto flow control. Check to see whether
472 * RTS/DTR or CTS/DSR caused this interrupt.
474 cause = readb(&ch->ch_neo_uart->mcr);
475 /* Which pin is doing auto flow? RTS or DTR? */
476 if ((cause & 0x4) == 0) {
477 if (cause & UART_MCR_RTS) {
478 spin_lock_irqsave(&ch->ch_lock,
480 ch->ch_mostat |= UART_MCR_RTS;
481 spin_unlock_irqrestore(&ch->ch_lock,
484 spin_lock_irqsave(&ch->ch_lock,
486 ch->ch_mostat &= ~(UART_MCR_RTS);
487 spin_unlock_irqrestore(&ch->ch_lock,
491 if (cause & UART_MCR_DTR) {
492 spin_lock_irqsave(&ch->ch_lock,
494 ch->ch_mostat |= UART_MCR_DTR;
495 spin_unlock_irqrestore(&ch->ch_lock,
498 spin_lock_irqsave(&ch->ch_lock,
500 ch->ch_mostat &= ~(UART_MCR_DTR);
501 spin_unlock_irqrestore(&ch->ch_lock,
507 /* Parse any modem signal changes */
508 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
512 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
514 struct channel_t *ch;
519 * Check to make sure it didn't receive interrupt with a null board
520 * associated or a board pointer that wasn't ours.
522 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
525 if (port >= brd->maxports)
528 ch = brd->channels[port];
529 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
532 linestatus = readb(&ch->ch_neo_uart->lsr);
534 ch->ch_cached_lsr |= linestatus;
536 if (ch->ch_cached_lsr & UART_LSR_DR) {
537 /* Read data from uart -> queue */
538 neo_copy_data_from_uart_to_queue(ch);
539 spin_lock_irqsave(&ch->ch_lock, flags);
540 dgnc_check_queue_flow_control(ch);
541 spin_unlock_irqrestore(&ch->ch_lock, flags);
545 * The next 3 tests should *NOT* happen, as the above test
546 * should encapsulate all 3... At least, thats what Exar says.
549 if (linestatus & UART_LSR_PE)
552 if (linestatus & UART_LSR_FE)
555 if (linestatus & UART_LSR_BI)
558 if (linestatus & UART_LSR_OE) {
560 * Rx Oruns. Exar says that an orun will NOT corrupt
561 * the FIFO. It will just replace the holding register
562 * with this new data byte. So basically just ignore this.
563 * Probably we should eventually have an orun stat in our
566 ch->ch_err_overrun++;
569 if (linestatus & UART_LSR_THRE) {
570 spin_lock_irqsave(&ch->ch_lock, flags);
571 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
572 spin_unlock_irqrestore(&ch->ch_lock, flags);
574 /* Transfer data (if any) from Write Queue -> UART. */
575 neo_copy_data_from_queue_to_uart(ch);
576 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
577 spin_lock_irqsave(&ch->ch_lock, flags);
578 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
579 spin_unlock_irqrestore(&ch->ch_lock, flags);
581 /* Transfer data (if any) from Write Queue -> UART. */
582 neo_copy_data_from_queue_to_uart(ch);
588 * Send any/all changes to the line to the UART.
590 static void neo_param(struct tty_struct *tty)
592 unsigned char lcr = 0;
593 unsigned char uart_lcr = 0;
594 unsigned char ier = 0;
595 unsigned char uart_ier = 0;
598 struct dgnc_board *bd;
599 struct channel_t *ch;
602 if (!tty || tty->magic != TTY_MAGIC)
605 un = (struct un_t *)tty->driver_data;
606 if (!un || un->magic != DGNC_UNIT_MAGIC)
610 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
614 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
617 /* If baud rate is zero, flush queues, and set mval to drop DTR. */
619 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
627 neo_flush_uart_write(ch);
628 neo_flush_uart_read(ch);
630 /* The baudrate is B0 so all modem lines are to be dropped. */
631 ch->ch_flags |= (CH_BAUD0);
632 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
633 neo_assert_modem_signals(ch);
637 } else if (ch->ch_custom_speed) {
638 baud = ch->ch_custom_speed;
639 /* Handle transition from B0 */
640 if (ch->ch_flags & CH_BAUD0) {
641 ch->ch_flags &= ~(CH_BAUD0);
644 * Bring back up RTS and DTR...
645 * Also handle RTS or DTR toggle if set.
647 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
648 ch->ch_mostat |= (UART_MCR_RTS);
649 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
650 ch->ch_mostat |= (UART_MCR_DTR);
656 ulong bauds[4][16] = {
660 600, 1200, 1800, 2400,
661 4800, 9600, 19200, 38400 },
662 { /* slowbaud & CBAUDEX */
663 0, 57600, 115200, 230400,
664 460800, 150, 200, 921600,
665 600, 1200, 1800, 2400,
666 4800, 9600, 19200, 38400 },
668 0, 57600, 76800, 115200,
669 131657, 153600, 230400, 460800,
670 921600, 1200, 1800, 2400,
671 4800, 9600, 19200, 38400 },
672 { /* fastbaud & CBAUDEX */
673 0, 57600, 115200, 230400,
674 460800, 150, 200, 921600,
675 600, 1200, 1800, 2400,
676 4800, 9600, 19200, 38400 }
680 * Only use the TXPrint baud rate if the terminal unit
683 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
684 (un->un_type == DGNC_PRINT))
685 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
687 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
689 if (ch->ch_c_cflag & CBAUDEX)
692 if (ch->ch_digi.digi_flags & DIGI_FAST)
697 if ((iindex >= 0) && (iindex < 4) &&
698 (jindex >= 0) && (jindex < 16))
699 baud = bauds[iindex][jindex];
706 /* Handle transition from B0 */
707 if (ch->ch_flags & CH_BAUD0) {
708 ch->ch_flags &= ~(CH_BAUD0);
711 * Bring back up RTS and DTR...
712 * Also handle RTS or DTR toggle if set.
714 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
715 ch->ch_mostat |= (UART_MCR_RTS);
716 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
717 ch->ch_mostat |= (UART_MCR_DTR);
721 if (ch->ch_c_cflag & PARENB)
722 lcr |= UART_LCR_PARITY;
724 if (!(ch->ch_c_cflag & PARODD))
725 lcr |= UART_LCR_EPAR;
728 * Not all platforms support mark/space parity,
729 * so this will hide behind an ifdef.
732 if (ch->ch_c_cflag & CMSPAR)
733 lcr |= UART_LCR_SPAR;
736 if (ch->ch_c_cflag & CSTOPB)
737 lcr |= UART_LCR_STOP;
739 switch (ch->ch_c_cflag & CSIZE) {
741 lcr |= UART_LCR_WLEN5;
744 lcr |= UART_LCR_WLEN6;
747 lcr |= UART_LCR_WLEN7;
751 lcr |= UART_LCR_WLEN8;
755 uart_ier = readb(&ch->ch_neo_uart->ier);
758 uart_lcr = readb(&ch->ch_neo_uart->lcr);
763 quot = ch->ch_bd->bd_dividend / baud;
765 if (quot != 0 && ch->ch_old_baud != baud) {
766 ch->ch_old_baud = baud;
767 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
768 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
769 writeb((quot >> 8), &ch->ch_neo_uart->ier);
770 writeb(lcr, &ch->ch_neo_uart->lcr);
774 writeb(lcr, &ch->ch_neo_uart->lcr);
776 if (ch->ch_c_cflag & CREAD)
777 ier |= (UART_IER_RDI | UART_IER_RLSI);
779 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
782 * Have the UART interrupt on modem signal changes ONLY when
783 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
785 if ((ch->ch_digi.digi_flags & CTSPACE) ||
786 (ch->ch_digi.digi_flags & RTSPACE) ||
787 (ch->ch_c_cflag & CRTSCTS) ||
788 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
789 !(ch->ch_c_cflag & CLOCAL))
792 ier &= ~UART_IER_MSI;
794 ier |= UART_IER_THRI;
797 writeb(ier, &ch->ch_neo_uart->ier);
799 /* Set new start/stop chars */
800 neo_set_new_start_stop_chars(ch);
802 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
803 neo_set_cts_flow_control(ch);
804 } else if (ch->ch_c_iflag & IXON) {
806 * If start/stop is set to disable, then we should
807 * disable flow control
809 if ((ch->ch_startc == _POSIX_VDISABLE) ||
810 (ch->ch_stopc == _POSIX_VDISABLE))
811 neo_set_no_output_flow_control(ch);
813 neo_set_ixon_flow_control(ch);
815 neo_set_no_output_flow_control(ch);
818 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
819 neo_set_rts_flow_control(ch);
820 } else if (ch->ch_c_iflag & IXOFF) {
822 * If start/stop is set to disable, then we should
823 * disable flow control
825 if ((ch->ch_startc == _POSIX_VDISABLE) ||
826 (ch->ch_stopc == _POSIX_VDISABLE))
827 neo_set_no_input_flow_control(ch);
829 neo_set_ixoff_flow_control(ch);
831 neo_set_no_input_flow_control(ch);
835 * Adjust the RX FIFO Trigger level if baud is less than 9600.
836 * Not exactly elegant, but this is needed because of the Exar chip's
837 * delay on firing off the RX FIFO interrupt on slower baud rates.
840 writeb(1, &ch->ch_neo_uart->rfifo);
844 neo_assert_modem_signals(ch);
846 /* Get current status of the modem signals now */
847 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
850 /* Our board poller function. */
852 static void neo_tasklet(unsigned long data)
854 struct dgnc_board *bd = (struct dgnc_board *)data;
855 struct channel_t *ch;
861 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
864 /* Cache a couple board values */
865 spin_lock_irqsave(&bd->bd_lock, flags);
868 spin_unlock_irqrestore(&bd->bd_lock, flags);
871 * Do NOT allow the interrupt routine to read the intr registers
872 * Until we release this lock.
874 spin_lock_irqsave(&bd->bd_intr_lock, flags);
876 /* If board is ready, parse deeper to see if there is anything to do. */
878 if ((state == BOARD_READY) && (ports > 0)) {
879 /* Loop on each port */
880 for (i = 0; i < ports; i++) {
881 ch = bd->channels[i];
883 /* Just being careful... */
884 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
888 * NOTE: Remember you CANNOT hold any channel
889 * locks when calling the input routine.
891 * During input processing, its possible we
892 * will call the Linux ld, which might in turn,
893 * do a callback right back into us, resulting
894 * in us trying to grab the channel lock twice!
899 * Channel lock is grabbed and then released
900 * inside both of these routines, but neither
901 * call anything else that could call back into us.
903 neo_copy_data_from_queue_to_uart(ch);
904 dgnc_wakeup_writes(ch);
907 * Call carrier carrier function, in case something
913 * Check to see if we need to turn off a sending break.
914 * The timing check is done inside clear_break()
916 if (ch->ch_stop_sending_break)
917 neo_clear_break(ch, 0);
921 /* Allow interrupt routine to access the interrupt register again */
922 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
928 * Neo specific interrupt handler.
930 static irqreturn_t neo_intr(int irq, void *voidbrd)
932 struct dgnc_board *brd = voidbrd;
933 struct channel_t *ch;
938 unsigned long flags2;
941 * Check to make sure it didn't receive interrupt with a null board
942 * associated or a board pointer that wasn't ours.
944 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
947 /* Lock out the slow poller from running on this board. */
948 spin_lock_irqsave(&brd->bd_intr_lock, flags);
951 * Read in "extended" IRQ information from the 32bit Neo register.
952 * Bits 0-7: What port triggered the interrupt.
953 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
955 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
958 * If 0, no interrupts pending.
959 * This can happen if the IRQ is shared among a couple Neo/Classic
963 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
968 * At this point, we have at least SOMETHING to service, dig
972 /* Loop on each port */
973 while ((uart_poll & 0xff) != 0) {
974 type = uart_poll >> (8 + (port * 3));
977 uart_poll &= ~(0x01 << port);
979 /* Switch on type of interrupt we have */
981 case UART_17158_RXRDY_TIMEOUT:
983 * RXRDY Time-out is cleared by reading data in the
984 * RX FIFO until it falls below the trigger level.
987 /* Verify the port is in range. */
988 if (port >= brd->nasync)
991 ch = brd->channels[port];
992 neo_copy_data_from_uart_to_queue(ch);
995 * Call our tty layer to enforce queue flow control if
998 spin_lock_irqsave(&ch->ch_lock, flags2);
999 dgnc_check_queue_flow_control(ch);
1000 spin_unlock_irqrestore(&ch->ch_lock, flags2);
1004 case UART_17158_RX_LINE_STATUS:
1006 /* RXRDY and RX LINE Status (logic OR of LSR[4:1]) */
1008 neo_parse_lsr(brd, port);
1011 case UART_17158_TXRDY:
1013 * TXRDY interrupt clears after reading ISR register
1014 * for the UART channel.
1018 * Yes, this is odd...
1019 * Why would I check EVERY possibility of type of
1020 * interrupt, when we know its TXRDY???
1021 * Becuz for some reason, even tho we got triggered for
1022 * TXRDY, it seems to be occasionally wrong. Instead of
1023 * TX, which it should be, I was getting things like
1026 neo_parse_isr(brd, port);
1029 case UART_17158_MSR:
1031 /* MSR or flow control was seen. */
1033 neo_parse_isr(brd, port);
1038 * The UART triggered us with a bogus interrupt type.
1039 * It appears the Exar chip, when REALLY bogged down,
1040 * will throw these once and awhile.
1041 * Its harmless, just ignore it and move on.
1049 /* Schedule tasklet to more in-depth servicing at a better time. */
1051 tasklet_schedule(&brd->helper_tasklet);
1053 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1059 * Neo specific way of turning off the receiver.
1060 * Used as a way to enforce queue flow control when in
1061 * hardware flow control mode.
1063 static void neo_disable_receiver(struct channel_t *ch)
1065 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1067 tmp &= ~(UART_IER_RDI);
1068 writeb(tmp, &ch->ch_neo_uart->ier);
1069 neo_pci_posting_flush(ch->ch_bd);
1073 * Neo specific way of turning on the receiver.
1074 * Used as a way to un-enforce queue flow control when in
1075 * hardware flow control mode.
1077 static void neo_enable_receiver(struct channel_t *ch)
1079 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1081 tmp |= (UART_IER_RDI);
1082 writeb(tmp, &ch->ch_neo_uart->ier);
1083 neo_pci_posting_flush(ch->ch_bd);
1086 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1089 unsigned char linestatus = 0;
1090 unsigned char error_mask = 0;
1095 unsigned long flags;
1097 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1100 spin_lock_irqsave(&ch->ch_lock, flags);
1102 /* cache head and tail of queue */
1103 head = ch->ch_r_head & RQUEUEMASK;
1104 tail = ch->ch_r_tail & RQUEUEMASK;
1106 /* Get our cached LSR */
1107 linestatus = ch->ch_cached_lsr;
1108 ch->ch_cached_lsr = 0;
1110 /* Store how much space we have left in the queue */
1111 qleft = tail - head - 1;
1113 qleft += RQUEUEMASK + 1;
1116 * If the UART is not in FIFO mode, force the FIFO copy to
1117 * NOT be run, by setting total to 0.
1119 * On the other hand, if the UART IS in FIFO mode, then ask
1120 * the UART to give us an approximation of data it has RX'ed.
1122 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1125 total = readb(&ch->ch_neo_uart->rfifo);
1128 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1130 * This resolves a problem/bug with the Exar chip that sometimes
1131 * returns a bogus value in the rfifo register.
1132 * The count can be any where from 0-3 bytes "off".
1133 * Bizarre, but true.
1135 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1142 * Finally, bound the copy to make sure we don't overflow
1144 * The byte by byte copy loop below this loop this will
1145 * deal with the queue overflow possibility.
1147 total = min(total, qleft);
1151 * Grab the linestatus register, we need to check
1152 * to see if there are any errors in the FIFO.
1154 linestatus = readb(&ch->ch_neo_uart->lsr);
1157 * Break out if there is a FIFO error somewhere.
1158 * This will allow us to go byte by byte down below,
1159 * finding the exact location of the error.
1161 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1164 /* Make sure we don't go over the end of our queue */
1165 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1168 * Cut down n even further if needed, this is to fix
1169 * a problem with memcpy_fromio() with the Neo on the
1170 * IBM pSeries platform.
1171 * 15 bytes max appears to be the magic number.
1173 n = min_t(uint, n, 12);
1176 * Since we are grabbing the linestatus register, which
1177 * will reset some bits after our read, we need to ensure
1178 * we don't miss our TX FIFO emptys.
1180 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1181 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1185 /* Copy data from uart to the queue */
1186 memcpy_fromio(ch->ch_rqueue + head,
1187 &ch->ch_neo_uart->txrxburst, n);
1190 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
1191 * that all the data currently in the FIFO is free of
1192 * breaks and parity/frame/orun errors.
1194 memset(ch->ch_equeue + head, 0, n);
1196 /* Add to and flip head if needed */
1197 head = (head + n) & RQUEUEMASK;
1200 ch->ch_rxcount += n;
1204 * Create a mask to determine whether we should
1205 * insert the character (if any) into our queue.
1207 if (ch->ch_c_iflag & IGNBRK)
1208 error_mask |= UART_LSR_BI;
1211 * Now cleanup any leftover bytes still in the UART.
1212 * Also deal with any possible queue overflow here as well.
1216 * Its possible we have a linestatus from the loop above
1217 * this, so we "OR" on any extra bits.
1219 linestatus |= readb(&ch->ch_neo_uart->lsr);
1222 * If the chip tells us there is no more data pending to
1223 * be read, we can then leave.
1224 * But before we do, cache the linestatus, just in case.
1226 if (!(linestatus & UART_LSR_DR)) {
1227 ch->ch_cached_lsr = linestatus;
1231 /* No need to store this bit */
1232 linestatus &= ~UART_LSR_DR;
1235 * Since we are grabbing the linestatus register, which
1236 * will reset some bits after our read, we need to ensure
1237 * we don't miss our TX FIFO emptys.
1239 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1240 linestatus &= ~(UART_LSR_THRE |
1241 UART_17158_TX_AND_FIFO_CLR);
1242 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1245 /* Discard character if we are ignoring the error mask. */
1247 if (linestatus & error_mask) {
1248 unsigned char discard;
1251 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1256 * If our queue is full, we have no choice but to drop some
1258 * The assumption is that HWFLOW or SWFLOW should have stopped
1259 * things way way before we got to this point.
1261 * I decided that I wanted to ditch the oldest data first,
1262 * I hope thats okay with everyone? Yes? Good.
1265 tail = (tail + 1) & RQUEUEMASK;
1266 ch->ch_r_tail = tail;
1267 ch->ch_err_overrun++;
1271 memcpy_fromio(ch->ch_rqueue + head,
1272 &ch->ch_neo_uart->txrxburst, 1);
1273 ch->ch_equeue[head] = (unsigned char)linestatus;
1275 /* Ditch any remaining linestatus value. */
1278 /* Add to and flip head if needed */
1279 head = (head + 1) & RQUEUEMASK;
1285 /* Write new final heads to channel structure. */
1287 ch->ch_r_head = head & RQUEUEMASK;
1288 ch->ch_e_head = head & EQUEUEMASK;
1290 spin_unlock_irqrestore(&ch->ch_lock, flags);
1294 * This function basically goes to sleep for secs, or until
1295 * it gets signalled that the port has fully drained.
1297 static int neo_drain(struct tty_struct *tty, uint seconds)
1299 unsigned long flags;
1300 struct channel_t *ch;
1304 if (!tty || tty->magic != TTY_MAGIC)
1307 un = (struct un_t *)tty->driver_data;
1308 if (!un || un->magic != DGNC_UNIT_MAGIC)
1312 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1315 spin_lock_irqsave(&ch->ch_lock, flags);
1316 un->un_flags |= UN_EMPTY;
1317 spin_unlock_irqrestore(&ch->ch_lock, flags);
1320 * Go to sleep waiting for the tty layer to wake me back up when
1321 * the empty flag goes away.
1323 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1324 ((un->un_flags & UN_EMPTY) == 0),
1325 msecs_to_jiffies(seconds * 1000));
1327 /* If ret is non-zero, user ctrl-c'ed us */
1332 * Flush the WRITE FIFO on the Neo.
1334 * NOTE: Channel lock MUST be held before calling this function!
1336 static void neo_flush_uart_write(struct channel_t *ch)
1338 unsigned char tmp = 0;
1341 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1344 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1345 &ch->ch_neo_uart->isr_fcr);
1346 neo_pci_posting_flush(ch->ch_bd);
1348 for (i = 0; i < 10; i++) {
1350 * Check to see if the UART feels it completely flushed the
1353 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1364 * Flush the READ FIFO on the Neo.
1366 * NOTE: Channel lock MUST be held before calling this function!
1368 static void neo_flush_uart_read(struct channel_t *ch)
1370 unsigned char tmp = 0;
1373 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1376 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1377 &ch->ch_neo_uart->isr_fcr);
1378 neo_pci_posting_flush(ch->ch_bd);
1380 for (i = 0; i < 10; i++) {
1382 * Check to see if the UART feels it completely flushed the
1385 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1393 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1400 uint len_written = 0;
1401 unsigned long flags;
1403 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1406 spin_lock_irqsave(&ch->ch_lock, flags);
1408 /* No data to write to the UART */
1409 if (ch->ch_w_tail == ch->ch_w_head)
1412 /* If port is "stopped", don't send any data to the UART */
1413 if ((ch->ch_flags & CH_FORCED_STOP) ||
1414 (ch->ch_flags & CH_BREAK_SENDING))
1417 /* If FIFOs are disabled. Send data directly to txrx register */
1419 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1420 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1422 /* Cache the LSR bits for later parsing */
1423 ch->ch_cached_lsr |= lsrbits;
1424 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1425 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1428 * If RTS Toggle mode is on, turn on RTS now if not
1429 * already set, and make sure we get an event when the
1430 * data transfer has completed.
1432 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1433 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1434 ch->ch_mostat |= (UART_MCR_RTS);
1435 neo_assert_modem_signals(ch);
1437 ch->ch_tun.un_flags |= (UN_EMPTY);
1440 * If DTR Toggle mode is on, turn on DTR now if not
1441 * already set, and make sure we get an event when the
1442 * data transfer has completed.
1444 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1445 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1446 ch->ch_mostat |= (UART_MCR_DTR);
1447 neo_assert_modem_signals(ch);
1449 ch->ch_tun.un_flags |= (UN_EMPTY);
1452 writeb(ch->ch_wqueue[ch->ch_w_tail],
1453 &ch->ch_neo_uart->txrx);
1455 ch->ch_w_tail &= WQUEUEMASK;
1462 /* We have to do it this way, because of the EXAR TXFIFO count bug. */
1464 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1465 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1470 n = readb(&ch->ch_neo_uart->tfifo);
1472 if ((unsigned int)n > ch->ch_t_tlevel)
1475 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1477 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1480 /* cache head and tail of queue */
1481 head = ch->ch_w_head & WQUEUEMASK;
1482 tail = ch->ch_w_tail & WQUEUEMASK;
1483 qlen = (head - tail) & WQUEUEMASK;
1485 /* Find minimum of the FIFO space, versus queue length */
1489 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1496 * If RTS Toggle mode is on, turn on RTS now if not already set,
1497 * and make sure we get an event when the data transfer has
1500 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1501 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1502 ch->ch_mostat |= (UART_MCR_RTS);
1503 neo_assert_modem_signals(ch);
1505 ch->ch_tun.un_flags |= (UN_EMPTY);
1509 * If DTR Toggle mode is on, turn on DTR now if not already set,
1510 * and make sure we get an event when the data transfer has
1513 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1514 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1515 ch->ch_mostat |= (UART_MCR_DTR);
1516 neo_assert_modem_signals(ch);
1518 ch->ch_tun.un_flags |= (UN_EMPTY);
1521 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1522 ch->ch_wqueue + tail, s);
1524 /* Add and flip queue if needed */
1525 tail = (tail + s) & WQUEUEMASK;
1527 ch->ch_txcount += s;
1531 /* Update the final tail */
1532 ch->ch_w_tail = tail & WQUEUEMASK;
1534 if (len_written > 0) {
1535 neo_pci_posting_flush(ch->ch_bd);
1536 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1540 spin_unlock_irqrestore(&ch->ch_lock, flags);
1543 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1545 unsigned char msignals = signals;
1547 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1551 * Do altpin switching. Altpin switches DCD and DSR.
1552 * This prolly breaks DSRPACE, so we should be more clever here.
1554 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1555 unsigned char mswap = msignals;
1557 if (mswap & UART_MSR_DDCD) {
1558 msignals &= ~UART_MSR_DDCD;
1559 msignals |= UART_MSR_DDSR;
1561 if (mswap & UART_MSR_DDSR) {
1562 msignals &= ~UART_MSR_DDSR;
1563 msignals |= UART_MSR_DDCD;
1565 if (mswap & UART_MSR_DCD) {
1566 msignals &= ~UART_MSR_DCD;
1567 msignals |= UART_MSR_DSR;
1569 if (mswap & UART_MSR_DSR) {
1570 msignals &= ~UART_MSR_DSR;
1571 msignals |= UART_MSR_DCD;
1576 * Scrub off lower bits. They signify delta's, which I don't care
1581 if (msignals & UART_MSR_DCD)
1582 ch->ch_mistat |= UART_MSR_DCD;
1584 ch->ch_mistat &= ~UART_MSR_DCD;
1586 if (msignals & UART_MSR_DSR)
1587 ch->ch_mistat |= UART_MSR_DSR;
1589 ch->ch_mistat &= ~UART_MSR_DSR;
1591 if (msignals & UART_MSR_RI)
1592 ch->ch_mistat |= UART_MSR_RI;
1594 ch->ch_mistat &= ~UART_MSR_RI;
1596 if (msignals & UART_MSR_CTS)
1597 ch->ch_mistat |= UART_MSR_CTS;
1599 ch->ch_mistat &= ~UART_MSR_CTS;
1602 /* Make the UART raise any of the output signals we want up */
1603 static void neo_assert_modem_signals(struct channel_t *ch)
1607 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1610 out = ch->ch_mostat;
1612 if (ch->ch_flags & CH_LOOPBACK)
1613 out |= UART_MCR_LOOP;
1615 writeb(out, &ch->ch_neo_uart->mcr);
1616 neo_pci_posting_flush(ch->ch_bd);
1618 /* Give time for the UART to actually raise/drop the signals */
1622 static void neo_send_start_character(struct channel_t *ch)
1624 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1627 if (ch->ch_startc != _POSIX_VDISABLE) {
1629 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1630 neo_pci_posting_flush(ch->ch_bd);
1635 static void neo_send_stop_character(struct channel_t *ch)
1637 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1640 if (ch->ch_stopc != _POSIX_VDISABLE) {
1641 ch->ch_xoff_sends++;
1642 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1643 neo_pci_posting_flush(ch->ch_bd);
1650 static void neo_uart_init(struct channel_t *ch)
1652 writeb(0, &ch->ch_neo_uart->ier);
1653 writeb(0, &ch->ch_neo_uart->efr);
1654 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1656 /* Clear out UART and FIFO */
1657 readb(&ch->ch_neo_uart->txrx);
1658 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1659 &ch->ch_neo_uart->isr_fcr);
1660 readb(&ch->ch_neo_uart->lsr);
1661 readb(&ch->ch_neo_uart->msr);
1663 ch->ch_flags |= CH_FIFO_ENABLED;
1665 /* Assert any signals we want up */
1666 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1667 neo_pci_posting_flush(ch->ch_bd);
1670 /* Make the UART completely turn off. */
1672 static void neo_uart_off(struct channel_t *ch)
1674 /* Turn off UART enhanced bits */
1675 writeb(0, &ch->ch_neo_uart->efr);
1677 /* Stop all interrupts from occurring. */
1678 writeb(0, &ch->ch_neo_uart->ier);
1679 neo_pci_posting_flush(ch->ch_bd);
1682 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1684 unsigned char left = 0;
1685 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1687 /* We must cache the LSR as some of the bits get reset once read... */
1688 ch->ch_cached_lsr |= lsr;
1690 /* Determine whether the Transmitter is empty or not */
1691 if (!(lsr & UART_LSR_TEMT)) {
1692 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1693 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1696 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1703 /* Channel lock MUST be held by the calling function! */
1704 static void neo_send_break(struct channel_t *ch, int msecs)
1706 /* If we receive a time of 0, this means turn off the break. */
1709 if (ch->ch_flags & CH_BREAK_SENDING) {
1710 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1712 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1713 neo_pci_posting_flush(ch->ch_bd);
1714 ch->ch_flags &= ~(CH_BREAK_SENDING);
1715 ch->ch_stop_sending_break = 0;
1721 * Set the time we should stop sending the break.
1722 * If we are already sending a break, toss away the existing
1723 * time to stop, and use this new value instead.
1725 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1727 /* Tell the UART to start sending the break */
1728 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1729 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1731 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1732 neo_pci_posting_flush(ch->ch_bd);
1733 ch->ch_flags |= (CH_BREAK_SENDING);
1738 * neo_send_immediate_char.
1740 * Sends a specific character as soon as possible to the UART,
1741 * jumping over any bytes that might be in the write queue.
1743 * The channel lock MUST be held by the calling function.
1745 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1747 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1750 writeb(c, &ch->ch_neo_uart->txrx);
1751 neo_pci_posting_flush(ch->ch_bd);
1754 static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1755 unsigned int address)
1757 unsigned int enable;
1759 unsigned int databit;
1762 /* enable chip select */
1763 writeb(NEO_EECS, base + NEO_EEREG);
1765 enable = address | 0x180;
1767 for (bits = 9; bits--; ) {
1768 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1769 /* Set read address */
1770 writeb(databit | NEO_EECS, base + NEO_EEREG);
1771 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1776 for (bits = 17; bits--; ) {
1777 /* clock to EEPROM */
1778 writeb(NEO_EECS, base + NEO_EEREG);
1779 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1782 if (readb(base + NEO_EEREG) & NEO_EEDO)
1786 /* clock falling edge */
1787 writeb(NEO_EECS, base + NEO_EEREG);
1789 /* drop chip select */
1790 writeb(0x00, base + NEO_EEREG);
1795 static void neo_vpd(struct dgnc_board *brd)
1800 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1803 if (!brd->re_map_membase)
1806 /* Store the VPD into our buffer */
1807 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1808 a = neo_read_eeprom(brd->re_map_membase, i);
1809 brd->vpd[i * 2] = a & 0xff;
1810 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1814 * brd->vpd has different name tags by below index.
1815 * 0x08 : long resource name tag
1816 * 0x10 : long resource name tage (PCI-66 files)
1817 * 0x7F : small resource end tag
1819 if (((brd->vpd[0x08] != 0x82) &&
1820 (brd->vpd[0x10] != 0x82)) ||
1821 (brd->vpd[0x7F] != 0x78)) {
1822 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1824 /* Search for the serial number */
1825 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1826 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1827 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);