2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
33 #include <linux/kernel.h>
34 #include <linux/sched.h> /* For jiffies, task states */
35 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
36 #include <linux/delay.h> /* For udelay */
37 #include <asm/io.h> /* For read[bwl]/write[bwl] */
38 #include <linux/serial.h> /* For struct async_serial */
39 #include <linux/serial_reg.h> /* For the various UART offsets */
41 #include "dgnc_driver.h" /* Driver main header file */
42 #include "dgnc_neo.h" /* Our header file */
44 #include "dgnc_trace.h"
46 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
47 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
48 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
49 static inline void neo_clear_break(struct channel_t *ch, int force);
50 static inline void neo_set_cts_flow_control(struct channel_t *ch);
51 static inline void neo_set_rts_flow_control(struct channel_t *ch);
52 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
53 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
54 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
55 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
56 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
57 static void neo_parse_modem(struct channel_t *ch, uchar signals);
58 static void neo_tasklet(unsigned long data);
59 static void neo_vpd(struct dgnc_board *brd);
60 static void neo_uart_init(struct channel_t *ch);
61 static void neo_uart_off(struct channel_t *ch);
62 static int neo_drain(struct tty_struct *tty, uint seconds);
63 static void neo_param(struct tty_struct *tty);
64 static void neo_assert_modem_signals(struct channel_t *ch);
65 static void neo_flush_uart_write(struct channel_t *ch);
66 static void neo_flush_uart_read(struct channel_t *ch);
67 static void neo_disable_receiver(struct channel_t *ch);
68 static void neo_enable_receiver(struct channel_t *ch);
69 static void neo_send_break(struct channel_t *ch, int msecs);
70 static void neo_send_start_character(struct channel_t *ch);
71 static void neo_send_stop_character(struct channel_t *ch);
72 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
73 static uint neo_get_uart_bytes_left(struct channel_t *ch);
74 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
75 static irqreturn_t neo_intr(int irq, void *voidbrd);
78 struct board_ops dgnc_neo_ops = {
79 .tasklet = neo_tasklet,
81 .uart_init = neo_uart_init,
82 .uart_off = neo_uart_off,
86 .assert_modem_signals = neo_assert_modem_signals,
87 .flush_uart_write = neo_flush_uart_write,
88 .flush_uart_read = neo_flush_uart_read,
89 .disable_receiver = neo_disable_receiver,
90 .enable_receiver = neo_enable_receiver,
91 .send_break = neo_send_break,
92 .send_start_character = neo_send_start_character,
93 .send_stop_character = neo_send_stop_character,
94 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
95 .get_uart_bytes_left = neo_get_uart_bytes_left,
96 .send_immediate_char = neo_send_immediate_char
99 static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
103 * This function allows calls to ensure that all outstanding
104 * PCI writes have been completed, by doing a PCI read against
105 * a non-destructive, read-only location on the Neo card.
107 * In this case, we are reading the DVID (Read-only Device Identification)
108 * value of the Neo card.
110 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
112 readb(bd->re_map_membase + 0x8D);
115 static inline void neo_set_cts_flow_control(struct channel_t *ch)
117 uchar ier = readb(&ch->ch_neo_uart->ier);
118 uchar efr = readb(&ch->ch_neo_uart->efr);
121 DPR_PARAM(("Setting CTSFLOW\n"));
123 /* Turn on auto CTS flow control */
125 ier |= (UART_17158_IER_CTSDSR);
127 ier &= ~(UART_17158_IER_CTSDSR);
130 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
132 /* Turn off auto Xon flow control */
133 efr &= ~(UART_17158_EFR_IXON);
135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136 writeb(0, &ch->ch_neo_uart->efr);
138 /* Turn on UART enhanced bits */
139 writeb(efr, &ch->ch_neo_uart->efr);
141 /* Turn on table D, with 8 char hi/low watermarks */
142 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
144 /* Feed the UART our trigger levels */
145 writeb(8, &ch->ch_neo_uart->tfifo);
148 writeb(ier, &ch->ch_neo_uart->ier);
150 neo_pci_posting_flush(ch->ch_bd);
154 static inline void neo_set_rts_flow_control(struct channel_t *ch)
156 uchar ier = readb(&ch->ch_neo_uart->ier);
157 uchar efr = readb(&ch->ch_neo_uart->efr);
159 DPR_PARAM(("Setting RTSFLOW\n"));
161 /* Turn on auto RTS flow control */
163 ier |= (UART_17158_IER_RTSDTR);
165 ier &= ~(UART_17158_IER_RTSDTR);
167 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
169 /* Turn off auto Xoff flow control */
170 ier &= ~(UART_17158_IER_XOFF);
171 efr &= ~(UART_17158_EFR_IXOFF);
173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174 writeb(0, &ch->ch_neo_uart->efr);
176 /* Turn on UART enhanced bits */
177 writeb(efr, &ch->ch_neo_uart->efr);
179 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
180 ch->ch_r_watermark = 4;
182 writeb(32, &ch->ch_neo_uart->rfifo);
183 ch->ch_r_tlevel = 32;
185 writeb(ier, &ch->ch_neo_uart->ier);
188 * From the Neo UART spec sheet:
189 * The auto RTS/DTR function must be started by asserting
190 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
193 ch->ch_mostat |= (UART_MCR_RTS);
195 neo_pci_posting_flush(ch->ch_bd);
199 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
201 uchar ier = readb(&ch->ch_neo_uart->ier);
202 uchar efr = readb(&ch->ch_neo_uart->efr);
204 DPR_PARAM(("Setting IXON FLOW\n"));
206 /* Turn off auto CTS flow control */
207 ier &= ~(UART_17158_IER_CTSDSR);
208 efr &= ~(UART_17158_EFR_CTSDSR);
210 /* Turn on auto Xon flow control */
211 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
213 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
214 writeb(0, &ch->ch_neo_uart->efr);
216 /* Turn on UART enhanced bits */
217 writeb(efr, &ch->ch_neo_uart->efr);
219 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
220 ch->ch_r_watermark = 4;
222 writeb(32, &ch->ch_neo_uart->rfifo);
223 ch->ch_r_tlevel = 32;
225 /* Tell UART what start/stop chars it should be looking for */
226 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
227 writeb(0, &ch->ch_neo_uart->xonchar2);
229 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
230 writeb(0, &ch->ch_neo_uart->xoffchar2);
232 writeb(ier, &ch->ch_neo_uart->ier);
234 neo_pci_posting_flush(ch->ch_bd);
238 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
240 uchar ier = readb(&ch->ch_neo_uart->ier);
241 uchar efr = readb(&ch->ch_neo_uart->efr);
243 DPR_PARAM(("Setting IXOFF FLOW\n"));
245 /* Turn off auto RTS flow control */
246 ier &= ~(UART_17158_IER_RTSDTR);
247 efr &= ~(UART_17158_EFR_RTSDTR);
249 /* Turn on auto Xoff flow control */
250 ier |= (UART_17158_IER_XOFF);
251 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
253 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
254 writeb(0, &ch->ch_neo_uart->efr);
256 /* Turn on UART enhanced bits */
257 writeb(efr, &ch->ch_neo_uart->efr);
259 /* Turn on table D, with 8 char hi/low watermarks */
260 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
262 writeb(8, &ch->ch_neo_uart->tfifo);
265 /* Tell UART what start/stop chars it should be looking for */
266 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
267 writeb(0, &ch->ch_neo_uart->xonchar2);
269 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
270 writeb(0, &ch->ch_neo_uart->xoffchar2);
272 writeb(ier, &ch->ch_neo_uart->ier);
274 neo_pci_posting_flush(ch->ch_bd);
278 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
280 uchar ier = readb(&ch->ch_neo_uart->ier);
281 uchar efr = readb(&ch->ch_neo_uart->efr);
283 DPR_PARAM(("Unsetting Input FLOW\n"));
285 /* Turn off auto RTS flow control */
286 ier &= ~(UART_17158_IER_RTSDTR);
287 efr &= ~(UART_17158_EFR_RTSDTR);
289 /* Turn off auto Xoff flow control */
290 ier &= ~(UART_17158_IER_XOFF);
291 if (ch->ch_c_iflag & IXON)
292 efr &= ~(UART_17158_EFR_IXOFF);
294 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
297 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
298 writeb(0, &ch->ch_neo_uart->efr);
300 /* Turn on UART enhanced bits */
301 writeb(efr, &ch->ch_neo_uart->efr);
303 /* Turn on table D, with 8 char hi/low watermarks */
304 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
306 ch->ch_r_watermark = 0;
308 writeb(16, &ch->ch_neo_uart->tfifo);
309 ch->ch_t_tlevel = 16;
311 writeb(16, &ch->ch_neo_uart->rfifo);
312 ch->ch_r_tlevel = 16;
314 writeb(ier, &ch->ch_neo_uart->ier);
316 neo_pci_posting_flush(ch->ch_bd);
320 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
322 uchar ier = readb(&ch->ch_neo_uart->ier);
323 uchar efr = readb(&ch->ch_neo_uart->efr);
325 DPR_PARAM(("Unsetting Output FLOW\n"));
327 /* Turn off auto CTS flow control */
328 ier &= ~(UART_17158_IER_CTSDSR);
329 efr &= ~(UART_17158_EFR_CTSDSR);
331 /* Turn off auto Xon flow control */
332 if (ch->ch_c_iflag & IXOFF)
333 efr &= ~(UART_17158_EFR_IXON);
335 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
337 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
338 writeb(0, &ch->ch_neo_uart->efr);
340 /* Turn on UART enhanced bits */
341 writeb(efr, &ch->ch_neo_uart->efr);
343 /* Turn on table D, with 8 char hi/low watermarks */
344 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
346 ch->ch_r_watermark = 0;
348 writeb(16, &ch->ch_neo_uart->tfifo);
349 ch->ch_t_tlevel = 16;
351 writeb(16, &ch->ch_neo_uart->rfifo);
352 ch->ch_r_tlevel = 16;
354 writeb(ier, &ch->ch_neo_uart->ier);
356 neo_pci_posting_flush(ch->ch_bd);
360 /* change UARTs start/stop chars */
361 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
364 /* if hardware flow control is set, then skip this whole thing */
365 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
368 DPR_PARAM(("In new start stop chars\n"));
370 /* Tell UART what start/stop chars it should be looking for */
371 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
372 writeb(0, &ch->ch_neo_uart->xonchar2);
374 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
375 writeb(0, &ch->ch_neo_uart->xoffchar2);
377 neo_pci_posting_flush(ch->ch_bd);
382 * No locks are assumed to be held when calling this function.
384 static inline void neo_clear_break(struct channel_t *ch, int force)
388 DGNC_LOCK(ch->ch_lock, lock_flags);
390 /* Bail if we aren't currently sending a break. */
391 if (!ch->ch_stop_sending_break) {
392 DGNC_UNLOCK(ch->ch_lock, lock_flags);
396 /* Turn break off, and unset some variables */
397 if (ch->ch_flags & CH_BREAK_SENDING) {
398 if (time_after_eq(jiffies, ch->ch_stop_sending_break)
400 uchar temp = readb(&ch->ch_neo_uart->lcr);
401 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
402 neo_pci_posting_flush(ch->ch_bd);
403 ch->ch_flags &= ~(CH_BREAK_SENDING);
404 ch->ch_stop_sending_break = 0;
405 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
408 DGNC_UNLOCK(ch->ch_lock, lock_flags);
413 * Parse the ISR register.
415 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
417 struct channel_t *ch;
422 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
425 if (port > brd->maxports)
428 ch = brd->channels[port];
429 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
432 /* Here we try to figure out what caused the interrupt to happen */
435 isr = readb(&ch->ch_neo_uart->isr_fcr);
437 /* Bail if no pending interrupt */
438 if (isr & UART_IIR_NO_INT)
442 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
444 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
446 DPR_INTR(("%s:%d isr: %x\n", __FILE__, __LINE__, isr));
448 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
449 /* Read data from uart -> queue */
452 neo_copy_data_from_uart_to_queue(ch);
454 /* Call our tty layer to enforce queue flow control if needed. */
455 DGNC_LOCK(ch->ch_lock, lock_flags);
456 dgnc_check_queue_flow_control(ch);
457 DGNC_UNLOCK(ch->ch_lock, lock_flags);
460 if (isr & UART_IIR_THRI) {
463 /* Transfer data (if any) from Write Queue -> UART. */
464 DGNC_LOCK(ch->ch_lock, lock_flags);
465 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
466 DGNC_UNLOCK(ch->ch_lock, lock_flags);
467 neo_copy_data_from_queue_to_uart(ch);
470 if (isr & UART_17158_IIR_XONXOFF) {
471 cause = readb(&ch->ch_neo_uart->xoffchar1);
473 DPR_INTR(("Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause));
476 * Since the UART detected either an XON or
477 * XOFF match, we need to figure out which
478 * one it was, so we can suspend or resume data flow.
480 if (cause == UART_17158_XON_DETECT) {
481 /* Is output stopped right now, if so, resume it */
482 if (brd->channels[port]->ch_flags & CH_STOP) {
483 DGNC_LOCK(ch->ch_lock, lock_flags);
484 ch->ch_flags &= ~(CH_STOP);
485 DGNC_UNLOCK(ch->ch_lock, lock_flags);
487 DPR_INTR(("Port %d. XON detected in incoming data\n", port));
488 } else if (cause == UART_17158_XOFF_DETECT) {
489 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
490 DGNC_LOCK(ch->ch_lock, lock_flags);
491 ch->ch_flags |= CH_STOP;
492 DGNC_UNLOCK(ch->ch_lock, lock_flags);
493 DPR_INTR(("Setting CH_STOP\n"));
495 DPR_INTR(("Port: %d. XOFF detected in incoming data\n", port));
499 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
501 * If we get here, this means the hardware is doing auto flow control.
502 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
506 cause = readb(&ch->ch_neo_uart->mcr);
507 /* Which pin is doing auto flow? RTS or DTR? */
508 if ((cause & 0x4) == 0) {
509 if (cause & UART_MCR_RTS) {
510 DGNC_LOCK(ch->ch_lock, lock_flags);
511 ch->ch_mostat |= UART_MCR_RTS;
512 DGNC_UNLOCK(ch->ch_lock, lock_flags);
514 DGNC_LOCK(ch->ch_lock, lock_flags);
515 ch->ch_mostat &= ~(UART_MCR_RTS);
516 DGNC_UNLOCK(ch->ch_lock, lock_flags);
519 if (cause & UART_MCR_DTR) {
520 DGNC_LOCK(ch->ch_lock, lock_flags);
521 ch->ch_mostat |= UART_MCR_DTR;
522 DGNC_UNLOCK(ch->ch_lock, lock_flags);
524 DGNC_LOCK(ch->ch_lock, lock_flags);
525 ch->ch_mostat &= ~(UART_MCR_DTR);
526 DGNC_UNLOCK(ch->ch_lock, lock_flags);
531 /* Parse any modem signal changes */
532 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
533 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
538 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
540 struct channel_t *ch;
547 if (brd->magic != DGNC_BOARD_MAGIC)
550 if (port > brd->maxports)
553 ch = brd->channels[port];
554 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
557 linestatus = readb(&ch->ch_neo_uart->lsr);
559 DPR_INTR(("%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus));
561 ch->ch_cached_lsr |= linestatus;
563 if (ch->ch_cached_lsr & UART_LSR_DR) {
566 /* Read data from uart -> queue */
567 neo_copy_data_from_uart_to_queue(ch);
568 DGNC_LOCK(ch->ch_lock, lock_flags);
569 dgnc_check_queue_flow_control(ch);
570 DGNC_UNLOCK(ch->ch_lock, lock_flags);
574 * This is a special flag. It indicates that at least 1
575 * RX error (parity, framing, or break) has happened.
576 * Mark this in our struct, which will tell me that I have
577 *to do the special RX+LSR read for this FIFO load.
579 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) {
580 DPR_INTR(("%s:%d Port: %d Got an RX error, need to parse LSR\n",
581 __FILE__, __LINE__, port));
585 * The next 3 tests should *NOT* happen, as the above test
586 * should encapsulate all 3... At least, thats what Exar says.
589 if (linestatus & UART_LSR_PE) {
591 DPR_INTR(("%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port));
594 if (linestatus & UART_LSR_FE) {
596 DPR_INTR(("%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port));
599 if (linestatus & UART_LSR_BI) {
601 DPR_INTR(("%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port));
604 if (linestatus & UART_LSR_OE) {
606 * Rx Oruns. Exar says that an orun will NOT corrupt
607 * the FIFO. It will just replace the holding register
608 * with this new data byte. So basically just ignore this.
609 * Probably we should eventually have an orun stat in our driver...
611 ch->ch_err_overrun++;
612 DPR_INTR(("%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port));
615 if (linestatus & UART_LSR_THRE) {
618 DGNC_LOCK(ch->ch_lock, lock_flags);
619 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
620 DGNC_UNLOCK(ch->ch_lock, lock_flags);
622 /* Transfer data (if any) from Write Queue -> UART. */
623 neo_copy_data_from_queue_to_uart(ch);
624 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
627 DGNC_LOCK(ch->ch_lock, lock_flags);
628 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
629 DGNC_UNLOCK(ch->ch_lock, lock_flags);
631 /* Transfer data (if any) from Write Queue -> UART. */
632 neo_copy_data_from_queue_to_uart(ch);
639 * Send any/all changes to the line to the UART.
641 static void neo_param(struct tty_struct *tty)
649 struct dgnc_board *bd;
650 struct channel_t *ch;
653 if (!tty || tty->magic != TTY_MAGIC)
656 un = (struct un_t *) tty->driver_data;
657 if (!un || un->magic != DGNC_UNIT_MAGIC)
661 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
665 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
668 DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
669 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag, ch->ch_c_iflag));
672 * If baud rate is zero, flush queues, and set mval to drop DTR.
674 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
675 ch->ch_r_head = ch->ch_r_tail = 0;
676 ch->ch_e_head = ch->ch_e_tail = 0;
677 ch->ch_w_head = ch->ch_w_tail = 0;
679 neo_flush_uart_write(ch);
680 neo_flush_uart_read(ch);
682 /* The baudrate is B0 so all modem lines are to be dropped. */
683 ch->ch_flags |= (CH_BAUD0);
684 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
685 neo_assert_modem_signals(ch);
689 } else if (ch->ch_custom_speed) {
691 baud = ch->ch_custom_speed;
692 /* Handle transition from B0 */
693 if (ch->ch_flags & CH_BAUD0) {
694 ch->ch_flags &= ~(CH_BAUD0);
697 * Bring back up RTS and DTR...
698 * Also handle RTS or DTR toggle if set.
700 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
701 ch->ch_mostat |= (UART_MCR_RTS);
702 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
703 ch->ch_mostat |= (UART_MCR_DTR);
709 ulong bauds[4][16] = {
713 600, 1200, 1800, 2400,
714 4800, 9600, 19200, 38400 },
715 { /* slowbaud & CBAUDEX */
716 0, 57600, 115200, 230400,
717 460800, 150, 200, 921600,
718 600, 1200, 1800, 2400,
719 4800, 9600, 19200, 38400 },
721 0, 57600, 76800, 115200,
722 131657, 153600, 230400, 460800,
723 921600, 1200, 1800, 2400,
724 4800, 9600, 19200, 38400 },
725 { /* fastbaud & CBAUDEX */
726 0, 57600, 115200, 230400,
727 460800, 150, 200, 921600,
728 600, 1200, 1800, 2400,
729 4800, 9600, 19200, 38400 }
732 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
733 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
734 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
736 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
738 if (ch->ch_c_cflag & CBAUDEX)
741 if (ch->ch_digi.digi_flags & DIGI_FAST)
746 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
747 baud = bauds[iindex][jindex];
749 DPR_IOCTL(("baud indices were out of range (%d)(%d)",
757 /* Handle transition from B0 */
758 if (ch->ch_flags & CH_BAUD0) {
759 ch->ch_flags &= ~(CH_BAUD0);
762 * Bring back up RTS and DTR...
763 * Also handle RTS or DTR toggle if set.
765 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
766 ch->ch_mostat |= (UART_MCR_RTS);
767 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
768 ch->ch_mostat |= (UART_MCR_DTR);
772 if (ch->ch_c_cflag & PARENB)
773 lcr |= UART_LCR_PARITY;
775 if (!(ch->ch_c_cflag & PARODD))
776 lcr |= UART_LCR_EPAR;
779 * Not all platforms support mark/space parity,
780 * so this will hide behind an ifdef.
783 if (ch->ch_c_cflag & CMSPAR)
784 lcr |= UART_LCR_SPAR;
787 if (ch->ch_c_cflag & CSTOPB)
788 lcr |= UART_LCR_STOP;
790 switch (ch->ch_c_cflag & CSIZE) {
792 lcr |= UART_LCR_WLEN5;
795 lcr |= UART_LCR_WLEN6;
798 lcr |= UART_LCR_WLEN7;
802 lcr |= UART_LCR_WLEN8;
806 ier = uart_ier = readb(&ch->ch_neo_uart->ier);
807 uart_lcr = readb(&ch->ch_neo_uart->lcr);
812 quot = ch->ch_bd->bd_dividend / baud;
814 if (quot != 0 && ch->ch_old_baud != baud) {
815 ch->ch_old_baud = baud;
816 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
817 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
818 writeb((quot >> 8), &ch->ch_neo_uart->ier);
819 writeb(lcr, &ch->ch_neo_uart->lcr);
823 writeb(lcr, &ch->ch_neo_uart->lcr);
825 if (ch->ch_c_cflag & CREAD)
826 ier |= (UART_IER_RDI | UART_IER_RLSI);
828 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
831 * Have the UART interrupt on modem signal changes ONLY when
832 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
834 if ((ch->ch_digi.digi_flags & CTSPACE) ||
835 (ch->ch_digi.digi_flags & RTSPACE) ||
836 (ch->ch_c_cflag & CRTSCTS) ||
837 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
838 !(ch->ch_c_cflag & CLOCAL))
841 ier &= ~UART_IER_MSI;
843 ier |= UART_IER_THRI;
846 writeb(ier, &ch->ch_neo_uart->ier);
848 /* Set new start/stop chars */
849 neo_set_new_start_stop_chars(ch);
851 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
852 neo_set_cts_flow_control(ch);
853 } else if (ch->ch_c_iflag & IXON) {
854 /* If start/stop is set to disable, then we should disable flow control */
855 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
856 neo_set_no_output_flow_control(ch);
858 neo_set_ixon_flow_control(ch);
860 neo_set_no_output_flow_control(ch);
863 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
864 neo_set_rts_flow_control(ch);
865 } else if (ch->ch_c_iflag & IXOFF) {
866 /* If start/stop is set to disable, then we should disable flow control */
867 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
868 neo_set_no_input_flow_control(ch);
870 neo_set_ixoff_flow_control(ch);
872 neo_set_no_input_flow_control(ch);
876 * Adjust the RX FIFO Trigger level if baud is less than 9600.
877 * Not exactly elegant, but this is needed because of the Exar chip's
878 * delay on firing off the RX FIFO interrupt on slower baud rates.
881 writeb(1, &ch->ch_neo_uart->rfifo);
885 neo_assert_modem_signals(ch);
887 /* Get current status of the modem signals now */
888 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
893 * Our board poller function.
895 static void neo_tasklet(unsigned long data)
897 struct dgnc_board *bd = (struct dgnc_board *) data;
898 struct channel_t *ch;
904 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
905 APR(("poll_tasklet() - NULL or bad bd.\n"));
909 /* Cache a couple board values */
910 DGNC_LOCK(bd->bd_lock, lock_flags);
913 DGNC_UNLOCK(bd->bd_lock, lock_flags);
916 * Do NOT allow the interrupt routine to read the intr registers
917 * Until we release this lock.
919 DGNC_LOCK(bd->bd_intr_lock, lock_flags);
922 * If board is ready, parse deeper to see if there is anything to do.
924 if ((state == BOARD_READY) && (ports > 0)) {
925 /* Loop on each port */
926 for (i = 0; i < ports; i++) {
927 ch = bd->channels[i];
929 /* Just being careful... */
930 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
934 * NOTE: Remember you CANNOT hold any channel
935 * locks when calling the input routine.
937 * During input processing, its possible we
938 * will call the Linux ld, which might in turn,
939 * do a callback right back into us, resulting
940 * in us trying to grab the channel lock twice!
945 * Channel lock is grabbed and then released
946 * inside both of these routines, but neither
947 * call anything else that could call back into us.
949 neo_copy_data_from_queue_to_uart(ch);
950 dgnc_wakeup_writes(ch);
953 * Call carrier carrier function, in case something
959 * Check to see if we need to turn off a sending break.
960 * The timing check is done inside clear_break()
962 if (ch->ch_stop_sending_break)
963 neo_clear_break(ch, 0);
967 /* Allow interrupt routine to access the interrupt register again */
968 DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
976 * Neo specific interrupt handler.
978 static irqreturn_t neo_intr(int irq, void *voidbrd)
980 struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
981 struct channel_t *ch;
987 unsigned long lock_flags;
988 unsigned long lock_flags2;
991 APR(("Received interrupt (%d) with null board associated\n", irq));
996 * Check to make sure its for us.
998 if (brd->magic != DGNC_BOARD_MAGIC) {
999 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq));
1005 /* Lock out the slow poller from running on this board. */
1006 DGNC_LOCK(brd->bd_intr_lock, lock_flags);
1009 * Read in "extended" IRQ information from the 32bit Neo register.
1010 * Bits 0-7: What port triggered the interrupt.
1011 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1013 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1015 DPR_INTR(("%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll));
1018 * If 0, no interrupts pending.
1019 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
1022 DPR_INTR(("Kernel interrupted to me, but no pending interrupts...\n"));
1023 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1027 /* At this point, we have at least SOMETHING to service, dig further... */
1031 /* Loop on each port */
1032 while ((uart_poll & 0xff) != 0) {
1036 /* Check current port to see if it has interrupt pending */
1037 if ((tmp & dgnc_offset_table[current_port]) != 0) {
1038 port = current_port;
1039 type = tmp >> (8 + (port * 3));
1046 DPR_INTR(("%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type));
1048 /* Remove this port + type from uart_poll */
1049 uart_poll &= ~(dgnc_offset_table[port]);
1052 /* If no type, just ignore it, and move onto next port */
1053 DPR_INTR(("Interrupt with no type! port: %d\n", port));
1057 /* Switch on type of interrupt we have */
1060 case UART_17158_RXRDY_TIMEOUT:
1062 * RXRDY Time-out is cleared by reading data in the
1063 * RX FIFO until it falls below the trigger level.
1066 /* Verify the port is in range. */
1067 if (port > brd->nasync)
1070 ch = brd->channels[port];
1071 neo_copy_data_from_uart_to_queue(ch);
1073 /* Call our tty layer to enforce queue flow control if needed. */
1074 DGNC_LOCK(ch->ch_lock, lock_flags2);
1075 dgnc_check_queue_flow_control(ch);
1076 DGNC_UNLOCK(ch->ch_lock, lock_flags2);
1080 case UART_17158_RX_LINE_STATUS:
1082 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1084 neo_parse_lsr(brd, port);
1087 case UART_17158_TXRDY:
1089 * TXRDY interrupt clears after reading ISR register for the UART channel.
1093 * Yes, this is odd...
1094 * Why would I check EVERY possibility of type of
1095 * interrupt, when we know its TXRDY???
1096 * Becuz for some reason, even tho we got triggered for TXRDY,
1097 * it seems to be occasionally wrong. Instead of TX, which
1098 * it should be, I was getting things like RXDY too. Weird.
1100 neo_parse_isr(brd, port);
1103 case UART_17158_MSR:
1105 * MSR or flow control was seen.
1107 neo_parse_isr(brd, port);
1112 * The UART triggered us with a bogus interrupt type.
1113 * It appears the Exar chip, when REALLY bogged down, will throw
1114 * these once and awhile.
1115 * Its harmless, just ignore it and move on.
1117 DPR_INTR(("%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type));
1123 * Schedule tasklet to more in-depth servicing at a better time.
1125 tasklet_schedule(&brd->helper_tasklet);
1127 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1129 DPR_INTR(("dgnc_intr finish.\n"));
1135 * Neo specific way of turning off the receiver.
1136 * Used as a way to enforce queue flow control when in
1137 * hardware flow control mode.
1139 static void neo_disable_receiver(struct channel_t *ch)
1141 uchar tmp = readb(&ch->ch_neo_uart->ier);
1142 tmp &= ~(UART_IER_RDI);
1143 writeb(tmp, &ch->ch_neo_uart->ier);
1144 neo_pci_posting_flush(ch->ch_bd);
1149 * Neo specific way of turning on the receiver.
1150 * Used as a way to un-enforce queue flow control when in
1151 * hardware flow control mode.
1153 static void neo_enable_receiver(struct channel_t *ch)
1155 uchar tmp = readb(&ch->ch_neo_uart->ier);
1156 tmp |= (UART_IER_RDI);
1157 writeb(tmp, &ch->ch_neo_uart->ier);
1158 neo_pci_posting_flush(ch->ch_bd);
1162 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1165 uchar linestatus = 0;
1166 uchar error_mask = 0;
1173 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1176 DGNC_LOCK(ch->ch_lock, lock_flags);
1178 /* cache head and tail of queue */
1179 head = ch->ch_r_head & RQUEUEMASK;
1180 tail = ch->ch_r_tail & RQUEUEMASK;
1182 /* Get our cached LSR */
1183 linestatus = ch->ch_cached_lsr;
1184 ch->ch_cached_lsr = 0;
1186 /* Store how much space we have left in the queue */
1187 qleft = tail - head - 1;
1189 qleft += RQUEUEMASK + 1;
1192 * If the UART is not in FIFO mode, force the FIFO copy to
1193 * NOT be run, by setting total to 0.
1195 * On the other hand, if the UART IS in FIFO mode, then ask
1196 * the UART to give us an approximation of data it has RX'ed.
1198 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1201 total = readb(&ch->ch_neo_uart->rfifo);
1204 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1206 * This resolves a problem/bug with the Exar chip that sometimes
1207 * returns a bogus value in the rfifo register.
1208 * The count can be any where from 0-3 bytes "off".
1209 * Bizarre, but true.
1211 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1219 * Finally, bound the copy to make sure we don't overflow
1221 * The byte by byte copy loop below this loop this will
1222 * deal with the queue overflow possibility.
1224 total = min(total, qleft);
1229 * Grab the linestatus register, we need to check
1230 * to see if there are any errors in the FIFO.
1232 linestatus = readb(&ch->ch_neo_uart->lsr);
1235 * Break out if there is a FIFO error somewhere.
1236 * This will allow us to go byte by byte down below,
1237 * finding the exact location of the error.
1239 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1242 /* Make sure we don't go over the end of our queue */
1243 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1246 * Cut down n even further if needed, this is to fix
1247 * a problem with memcpy_fromio() with the Neo on the
1248 * IBM pSeries platform.
1249 * 15 bytes max appears to be the magic number.
1251 n = min((uint) n, (uint) 12);
1254 * Since we are grabbing the linestatus register, which
1255 * will reset some bits after our read, we need to ensure
1256 * we don't miss our TX FIFO emptys.
1258 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1259 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1263 /* Copy data from uart to the queue */
1264 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
1265 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, n);
1268 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1269 * that all the data currently in the FIFO is free of
1270 * breaks and parity/frame/orun errors.
1272 memset(ch->ch_equeue + head, 0, n);
1274 /* Add to and flip head if needed */
1275 head = (head + n) & RQUEUEMASK;
1278 ch->ch_rxcount += n;
1282 * Create a mask to determine whether we should
1283 * insert the character (if any) into our queue.
1285 if (ch->ch_c_iflag & IGNBRK)
1286 error_mask |= UART_LSR_BI;
1289 * Now cleanup any leftover bytes still in the UART.
1290 * Also deal with any possible queue overflow here as well.
1295 * Its possible we have a linestatus from the loop above
1296 * this, so we "OR" on any extra bits.
1298 linestatus |= readb(&ch->ch_neo_uart->lsr);
1301 * If the chip tells us there is no more data pending to
1302 * be read, we can then leave.
1303 * But before we do, cache the linestatus, just in case.
1305 if (!(linestatus & UART_LSR_DR)) {
1306 ch->ch_cached_lsr = linestatus;
1310 /* No need to store this bit */
1311 linestatus &= ~UART_LSR_DR;
1314 * Since we are grabbing the linestatus register, which
1315 * will reset some bits after our read, we need to ensure
1316 * we don't miss our TX FIFO emptys.
1318 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1319 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1320 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1324 * Discard character if we are ignoring the error mask.
1326 if (linestatus & error_mask) {
1329 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1334 * If our queue is full, we have no choice but to drop some data.
1335 * The assumption is that HWFLOW or SWFLOW should have stopped
1336 * things way way before we got to this point.
1338 * I decided that I wanted to ditch the oldest data first,
1339 * I hope thats okay with everyone? Yes? Good.
1342 DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
1343 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
1345 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
1346 ch->ch_err_overrun++;
1350 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
1351 ch->ch_equeue[head] = (uchar) linestatus;
1352 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1);
1354 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]));
1356 /* Ditch any remaining linestatus value. */
1359 /* Add to and flip head if needed */
1360 head = (head + 1) & RQUEUEMASK;
1367 * Write new final heads to channel structure.
1369 ch->ch_r_head = head & RQUEUEMASK;
1370 ch->ch_e_head = head & EQUEUEMASK;
1372 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1377 * This function basically goes to sleep for secs, or until
1378 * it gets signalled that the port has fully drained.
1380 static int neo_drain(struct tty_struct *tty, uint seconds)
1383 struct channel_t *ch;
1387 if (!tty || tty->magic != TTY_MAGIC)
1390 un = (struct un_t *) tty->driver_data;
1391 if (!un || un->magic != DGNC_UNIT_MAGIC)
1395 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1398 DPR_IOCTL(("%d Drain wait started.\n", __LINE__));
1400 DGNC_LOCK(ch->ch_lock, lock_flags);
1401 un->un_flags |= UN_EMPTY;
1402 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1405 * Go to sleep waiting for the tty layer to wake me back up when
1406 * the empty flag goes away.
1408 * NOTE: TODO: Do something with time passed in.
1410 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1412 /* If ret is non-zero, user ctrl-c'ed us */
1414 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1416 DPR_IOCTL(("%d Drain wait finished.\n", __LINE__));
1423 * Flush the WRITE FIFO on the Neo.
1425 * NOTE: Channel lock MUST be held before calling this function!
1427 static void neo_flush_uart_write(struct channel_t *ch)
1432 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1435 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1436 neo_pci_posting_flush(ch->ch_bd);
1438 for (i = 0; i < 10; i++) {
1440 /* Check to see if the UART feels it completely flushed the FIFO. */
1441 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1443 DPR_IOCTL(("Still flushing TX UART... i: %d\n", i));
1449 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1454 * Flush the READ FIFO on the Neo.
1456 * NOTE: Channel lock MUST be held before calling this function!
1458 static void neo_flush_uart_read(struct channel_t *ch)
1463 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1466 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1467 neo_pci_posting_flush(ch->ch_bd);
1469 for (i = 0; i < 10; i++) {
1471 /* Check to see if the UART feels it completely flushed the FIFO. */
1472 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1474 DPR_IOCTL(("Still flushing RX UART... i: %d\n", i));
1482 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1489 uint len_written = 0;
1492 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1495 DGNC_LOCK(ch->ch_lock, lock_flags);
1497 /* No data to write to the UART */
1498 if (ch->ch_w_tail == ch->ch_w_head) {
1499 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1503 /* If port is "stopped", don't send any data to the UART */
1504 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
1505 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1510 * If FIFOs are disabled. Send data directly to txrx register
1512 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1513 uchar lsrbits = readb(&ch->ch_neo_uart->lsr);
1515 /* Cache the LSR bits for later parsing */
1516 ch->ch_cached_lsr |= lsrbits;
1517 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1518 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1521 * If RTS Toggle mode is on, turn on RTS now if not already set,
1522 * and make sure we get an event when the data transfer has completed.
1524 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1525 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1526 ch->ch_mostat |= (UART_MCR_RTS);
1527 neo_assert_modem_signals(ch);
1529 ch->ch_tun.un_flags |= (UN_EMPTY);
1532 * If DTR Toggle mode is on, turn on DTR now if not already set,
1533 * and make sure we get an event when the data transfer has completed.
1535 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1536 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1537 ch->ch_mostat |= (UART_MCR_DTR);
1538 neo_assert_modem_signals(ch);
1540 ch->ch_tun.un_flags |= (UN_EMPTY);
1543 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
1544 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]));
1546 ch->ch_w_tail &= WQUEUEMASK;
1549 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1554 * We have to do it this way, because of the EXAR TXFIFO count bug.
1556 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1557 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1558 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1564 n = readb(&ch->ch_neo_uart->tfifo);
1566 if ((unsigned int) n > ch->ch_t_tlevel) {
1567 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1571 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1573 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1576 /* cache head and tail of queue */
1577 head = ch->ch_w_head & WQUEUEMASK;
1578 tail = ch->ch_w_tail & WQUEUEMASK;
1579 qlen = (head - tail) & WQUEUEMASK;
1581 /* Find minimum of the FIFO space, versus queue length */
1586 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1593 * If RTS Toggle mode is on, turn on RTS now if not already set,
1594 * and make sure we get an event when the data transfer has completed.
1596 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1597 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1598 ch->ch_mostat |= (UART_MCR_RTS);
1599 neo_assert_modem_signals(ch);
1601 ch->ch_tun.un_flags |= (UN_EMPTY);
1605 * If DTR Toggle mode is on, turn on DTR now if not already set,
1606 * and make sure we get an event when the data transfer has completed.
1608 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1609 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1610 ch->ch_mostat |= (UART_MCR_DTR);
1611 neo_assert_modem_signals(ch);
1613 ch->ch_tun.un_flags |= (UN_EMPTY);
1616 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
1617 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + tail, s);
1619 /* Add and flip queue if needed */
1620 tail = (tail + s) & WQUEUEMASK;
1622 ch->ch_txcount += s;
1626 /* Update the final tail */
1627 ch->ch_w_tail = tail & WQUEUEMASK;
1629 if (len_written > 0) {
1630 neo_pci_posting_flush(ch->ch_bd);
1631 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1634 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1638 static void neo_parse_modem(struct channel_t *ch, uchar signals)
1640 volatile uchar msignals = signals;
1642 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1645 DPR_MSIGS(("neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals));
1648 * Do altpin switching. Altpin switches DCD and DSR.
1649 * This prolly breaks DSRPACE, so we should be more clever here.
1651 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1652 uchar mswap = msignals;
1654 if (mswap & UART_MSR_DDCD) {
1655 msignals &= ~UART_MSR_DDCD;
1656 msignals |= UART_MSR_DDSR;
1658 if (mswap & UART_MSR_DDSR) {
1659 msignals &= ~UART_MSR_DDSR;
1660 msignals |= UART_MSR_DDCD;
1662 if (mswap & UART_MSR_DCD) {
1663 msignals &= ~UART_MSR_DCD;
1664 msignals |= UART_MSR_DSR;
1666 if (mswap & UART_MSR_DSR) {
1667 msignals &= ~UART_MSR_DSR;
1668 msignals |= UART_MSR_DCD;
1672 /* Scrub off lower bits. They signify delta's, which I don't care about */
1675 if (msignals & UART_MSR_DCD)
1676 ch->ch_mistat |= UART_MSR_DCD;
1678 ch->ch_mistat &= ~UART_MSR_DCD;
1680 if (msignals & UART_MSR_DSR)
1681 ch->ch_mistat |= UART_MSR_DSR;
1683 ch->ch_mistat &= ~UART_MSR_DSR;
1685 if (msignals & UART_MSR_RI)
1686 ch->ch_mistat |= UART_MSR_RI;
1688 ch->ch_mistat &= ~UART_MSR_RI;
1690 if (msignals & UART_MSR_CTS)
1691 ch->ch_mistat |= UART_MSR_CTS;
1693 ch->ch_mistat &= ~UART_MSR_CTS;
1695 DPR_MSIGS(("Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1697 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1698 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1699 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1700 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1701 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1702 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1706 /* Make the UART raise any of the output signals we want up */
1707 static void neo_assert_modem_signals(struct channel_t *ch)
1711 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1714 out = ch->ch_mostat;
1716 if (ch->ch_flags & CH_LOOPBACK)
1717 out |= UART_MCR_LOOP;
1719 writeb(out, &ch->ch_neo_uart->mcr);
1720 neo_pci_posting_flush(ch->ch_bd);
1722 /* Give time for the UART to actually raise/drop the signals */
1727 static void neo_send_start_character(struct channel_t *ch)
1729 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1732 if (ch->ch_startc != _POSIX_VDISABLE) {
1734 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1735 neo_pci_posting_flush(ch->ch_bd);
1741 static void neo_send_stop_character(struct channel_t *ch)
1743 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1746 if (ch->ch_stopc != _POSIX_VDISABLE) {
1747 ch->ch_xoff_sends++;
1748 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1749 neo_pci_posting_flush(ch->ch_bd);
1758 static void neo_uart_init(struct channel_t *ch)
1761 writeb(0, &ch->ch_neo_uart->ier);
1762 writeb(0, &ch->ch_neo_uart->efr);
1763 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1766 /* Clear out UART and FIFO */
1767 readb(&ch->ch_neo_uart->txrx);
1768 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1769 readb(&ch->ch_neo_uart->lsr);
1770 readb(&ch->ch_neo_uart->msr);
1772 ch->ch_flags |= CH_FIFO_ENABLED;
1774 /* Assert any signals we want up */
1775 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1776 neo_pci_posting_flush(ch->ch_bd);
1781 * Make the UART completely turn off.
1783 static void neo_uart_off(struct channel_t *ch)
1785 /* Turn off UART enhanced bits */
1786 writeb(0, &ch->ch_neo_uart->efr);
1788 /* Stop all interrupts from occurring. */
1789 writeb(0, &ch->ch_neo_uart->ier);
1790 neo_pci_posting_flush(ch->ch_bd);
1794 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1797 uchar lsr = readb(&ch->ch_neo_uart->lsr);
1799 /* We must cache the LSR as some of the bits get reset once read... */
1800 ch->ch_cached_lsr |= lsr;
1802 /* Determine whether the Transmitter is empty or not */
1803 if (!(lsr & UART_LSR_TEMT)) {
1804 if (ch->ch_flags & CH_TX_FIFO_EMPTY) {
1805 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1809 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1817 /* Channel lock MUST be held by the calling function! */
1818 static void neo_send_break(struct channel_t *ch, int msecs)
1821 * If we receive a time of 0, this means turn off the break.
1824 if (ch->ch_flags & CH_BREAK_SENDING) {
1825 uchar temp = readb(&ch->ch_neo_uart->lcr);
1826 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1827 neo_pci_posting_flush(ch->ch_bd);
1828 ch->ch_flags &= ~(CH_BREAK_SENDING);
1829 ch->ch_stop_sending_break = 0;
1830 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
1836 * Set the time we should stop sending the break.
1837 * If we are already sending a break, toss away the existing
1838 * time to stop, and use this new value instead.
1840 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1842 /* Tell the UART to start sending the break */
1843 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1844 uchar temp = readb(&ch->ch_neo_uart->lcr);
1845 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1846 neo_pci_posting_flush(ch->ch_bd);
1847 ch->ch_flags |= (CH_BREAK_SENDING);
1848 DPR_IOCTL(("Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1849 ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1855 * neo_send_immediate_char.
1857 * Sends a specific character as soon as possible to the UART,
1858 * jumping over any bytes that might be in the write queue.
1860 * The channel lock MUST be held by the calling function.
1862 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1864 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1867 writeb(c, &ch->ch_neo_uart->txrx);
1868 neo_pci_posting_flush(ch->ch_bd);
1872 static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
1874 unsigned int enable;
1876 unsigned int databit;
1879 /* enable chip select */
1880 writeb(NEO_EECS, base + NEO_EEREG);
1882 enable = (address | 0x180);
1884 for (bits = 9; bits--; ) {
1885 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1886 /* Set read address */
1887 writeb(databit | NEO_EECS, base + NEO_EEREG);
1888 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1893 for (bits = 17; bits--; ) {
1894 /* clock to EEPROM */
1895 writeb(NEO_EECS, base + NEO_EEREG);
1896 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1899 if (readb(base + NEO_EEREG) & NEO_EEDO)
1903 /* clock falling edge */
1904 writeb(NEO_EECS, base + NEO_EEREG);
1906 /* drop chip select */
1907 writeb(0x00, base + NEO_EEREG);
1913 static void neo_vpd(struct dgnc_board *brd)
1918 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1921 if (!brd->re_map_membase)
1924 /* Store the VPD into our buffer */
1925 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1926 a = neo_read_eeprom(brd->re_map_membase, i);
1927 brd->vpd[i*2] = a & 0xff;
1928 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1931 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1932 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
1933 || (brd->vpd[0x7F] != 0x78)) /* small resource end tag */
1935 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1937 /* Search for the serial number */
1938 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1939 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1940 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);