2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
16 #include <linux/kernel.h>
17 #include <linux/sched.h> /* For jiffies, task states */
18 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
19 #include <linux/delay.h> /* For udelay */
20 #include <linux/io.h> /* For read[bwl]/write[bwl] */
21 #include <linux/serial.h> /* For struct async_serial */
22 #include <linux/serial_reg.h> /* For the various UART offsets */
24 #include "dgnc_driver.h" /* Driver main header file */
25 #include "dgnc_neo.h" /* Our header file */
28 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
29 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
30 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
31 static inline void neo_clear_break(struct channel_t *ch, int force);
32 static inline void neo_set_cts_flow_control(struct channel_t *ch);
33 static inline void neo_set_rts_flow_control(struct channel_t *ch);
34 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
36 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
38 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
39 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
40 static void neo_tasklet(unsigned long data);
41 static void neo_vpd(struct dgnc_board *brd);
42 static void neo_uart_init(struct channel_t *ch);
43 static void neo_uart_off(struct channel_t *ch);
44 static int neo_drain(struct tty_struct *tty, uint seconds);
45 static void neo_param(struct tty_struct *tty);
46 static void neo_assert_modem_signals(struct channel_t *ch);
47 static void neo_flush_uart_write(struct channel_t *ch);
48 static void neo_flush_uart_read(struct channel_t *ch);
49 static void neo_disable_receiver(struct channel_t *ch);
50 static void neo_enable_receiver(struct channel_t *ch);
51 static void neo_send_break(struct channel_t *ch, int msecs);
52 static void neo_send_start_character(struct channel_t *ch);
53 static void neo_send_stop_character(struct channel_t *ch);
54 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
55 static uint neo_get_uart_bytes_left(struct channel_t *ch);
56 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
57 static irqreturn_t neo_intr(int irq, void *voidbrd);
59 struct board_ops dgnc_neo_ops = {
60 .tasklet = neo_tasklet,
62 .uart_init = neo_uart_init,
63 .uart_off = neo_uart_off,
67 .assert_modem_signals = neo_assert_modem_signals,
68 .flush_uart_write = neo_flush_uart_write,
69 .flush_uart_read = neo_flush_uart_read,
70 .disable_receiver = neo_disable_receiver,
71 .enable_receiver = neo_enable_receiver,
72 .send_break = neo_send_break,
73 .send_start_character = neo_send_start_character,
74 .send_stop_character = neo_send_stop_character,
75 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
76 .get_uart_bytes_left = neo_get_uart_bytes_left,
77 .send_immediate_char = neo_send_immediate_char
81 * This function allows calls to ensure that all outstanding
82 * PCI writes have been completed, by doing a PCI read against
83 * a non-destructive, read-only location on the Neo card.
85 * In this case, we are reading the DVID (Read-only Device Identification)
86 * value of the Neo card.
88 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
90 readb(bd->re_map_membase + 0x8D);
93 static inline void neo_set_cts_flow_control(struct channel_t *ch)
95 unsigned char ier = readb(&ch->ch_neo_uart->ier);
96 unsigned char efr = readb(&ch->ch_neo_uart->efr);
98 /* Turn on auto CTS flow control */
100 ier |= UART_17158_IER_CTSDSR;
102 ier &= ~(UART_17158_IER_CTSDSR);
105 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
107 /* Turn off auto Xon flow control */
108 efr &= ~UART_17158_EFR_IXON;
110 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
111 writeb(0, &ch->ch_neo_uart->efr);
113 /* Turn on UART enhanced bits */
114 writeb(efr, &ch->ch_neo_uart->efr);
116 /* Turn on table D, with 8 char hi/low watermarks */
117 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
118 &ch->ch_neo_uart->fctr);
120 /* Feed the UART our trigger levels */
121 writeb(8, &ch->ch_neo_uart->tfifo);
124 writeb(ier, &ch->ch_neo_uart->ier);
126 neo_pci_posting_flush(ch->ch_bd);
129 static inline void neo_set_rts_flow_control(struct channel_t *ch)
131 unsigned char ier = readb(&ch->ch_neo_uart->ier);
132 unsigned char efr = readb(&ch->ch_neo_uart->efr);
134 /* Turn on auto RTS flow control */
136 ier |= UART_17158_IER_RTSDTR;
138 ier &= ~(UART_17158_IER_RTSDTR);
140 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
142 /* Turn off auto Xoff flow control */
143 ier &= ~UART_17158_IER_XOFF;
144 efr &= ~UART_17158_EFR_IXOFF;
146 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
147 writeb(0, &ch->ch_neo_uart->efr);
149 /* Turn on UART enhanced bits */
150 writeb(efr, &ch->ch_neo_uart->efr);
152 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY,
153 &ch->ch_neo_uart->fctr);
154 ch->ch_r_watermark = 4;
156 writeb(32, &ch->ch_neo_uart->rfifo);
157 ch->ch_r_tlevel = 32;
159 writeb(ier, &ch->ch_neo_uart->ier);
162 * From the Neo UART spec sheet:
163 * The auto RTS/DTR function must be started by asserting
164 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
167 ch->ch_mostat |= UART_MCR_RTS;
169 neo_pci_posting_flush(ch->ch_bd);
172 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
174 unsigned char ier = readb(&ch->ch_neo_uart->ier);
175 unsigned char efr = readb(&ch->ch_neo_uart->efr);
177 /* Turn off auto CTS flow control */
178 ier &= ~UART_17158_IER_CTSDSR;
179 efr &= ~UART_17158_EFR_CTSDSR;
181 /* Turn on auto Xon flow control */
182 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
184 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
185 writeb(0, &ch->ch_neo_uart->efr);
187 /* Turn on UART enhanced bits */
188 writeb(efr, &ch->ch_neo_uart->efr);
190 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
191 &ch->ch_neo_uart->fctr);
192 ch->ch_r_watermark = 4;
194 writeb(32, &ch->ch_neo_uart->rfifo);
195 ch->ch_r_tlevel = 32;
197 /* Tell UART what start/stop chars it should be looking for */
198 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
199 writeb(0, &ch->ch_neo_uart->xonchar2);
201 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
202 writeb(0, &ch->ch_neo_uart->xoffchar2);
204 writeb(ier, &ch->ch_neo_uart->ier);
206 neo_pci_posting_flush(ch->ch_bd);
209 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
211 unsigned char ier = readb(&ch->ch_neo_uart->ier);
212 unsigned char efr = readb(&ch->ch_neo_uart->efr);
214 /* Turn off auto RTS flow control */
215 ier &= ~UART_17158_IER_RTSDTR;
216 efr &= ~UART_17158_EFR_RTSDTR;
218 /* Turn on auto Xoff flow control */
219 ier |= UART_17158_IER_XOFF;
220 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
222 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
223 writeb(0, &ch->ch_neo_uart->efr);
225 /* Turn on UART enhanced bits */
226 writeb(efr, &ch->ch_neo_uart->efr);
228 /* Turn on table D, with 8 char hi/low watermarks */
229 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
230 &ch->ch_neo_uart->fctr);
232 writeb(8, &ch->ch_neo_uart->tfifo);
235 /* Tell UART what start/stop chars it should be looking for */
236 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
237 writeb(0, &ch->ch_neo_uart->xonchar2);
239 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
240 writeb(0, &ch->ch_neo_uart->xoffchar2);
242 writeb(ier, &ch->ch_neo_uart->ier);
244 neo_pci_posting_flush(ch->ch_bd);
247 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
249 unsigned char ier = readb(&ch->ch_neo_uart->ier);
250 unsigned char efr = readb(&ch->ch_neo_uart->efr);
252 /* Turn off auto RTS flow control */
253 ier &= ~UART_17158_IER_RTSDTR;
254 efr &= ~UART_17158_EFR_RTSDTR;
256 /* Turn off auto Xoff flow control */
257 ier &= ~UART_17158_IER_XOFF;
258 if (ch->ch_c_iflag & IXON)
259 efr &= ~(UART_17158_EFR_IXOFF);
261 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
263 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
264 writeb(0, &ch->ch_neo_uart->efr);
266 /* Turn on UART enhanced bits */
267 writeb(efr, &ch->ch_neo_uart->efr);
269 /* Turn on table D, with 8 char hi/low watermarks */
270 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
271 &ch->ch_neo_uart->fctr);
273 ch->ch_r_watermark = 0;
275 writeb(16, &ch->ch_neo_uart->tfifo);
276 ch->ch_t_tlevel = 16;
278 writeb(16, &ch->ch_neo_uart->rfifo);
279 ch->ch_r_tlevel = 16;
281 writeb(ier, &ch->ch_neo_uart->ier);
283 neo_pci_posting_flush(ch->ch_bd);
286 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
288 unsigned char ier = readb(&ch->ch_neo_uart->ier);
289 unsigned char efr = readb(&ch->ch_neo_uart->efr);
291 /* Turn off auto CTS flow control */
292 ier &= ~UART_17158_IER_CTSDSR;
293 efr &= ~UART_17158_EFR_CTSDSR;
295 /* Turn off auto Xon flow control */
296 if (ch->ch_c_iflag & IXOFF)
297 efr &= ~UART_17158_EFR_IXON;
299 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
301 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
302 writeb(0, &ch->ch_neo_uart->efr);
304 /* Turn on UART enhanced bits */
305 writeb(efr, &ch->ch_neo_uart->efr);
307 /* Turn on table D, with 8 char hi/low watermarks */
308 writeb(UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY,
309 &ch->ch_neo_uart->fctr);
311 ch->ch_r_watermark = 0;
313 writeb(16, &ch->ch_neo_uart->tfifo);
314 ch->ch_t_tlevel = 16;
316 writeb(16, &ch->ch_neo_uart->rfifo);
317 ch->ch_r_tlevel = 16;
319 writeb(ier, &ch->ch_neo_uart->ier);
321 neo_pci_posting_flush(ch->ch_bd);
324 /* change UARTs start/stop chars */
325 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
327 /* if hardware flow control is set, then skip this whole thing */
328 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) ||
329 ch->ch_c_cflag & CRTSCTS)
332 /* Tell UART what start/stop chars it should be looking for */
333 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
334 writeb(0, &ch->ch_neo_uart->xonchar2);
336 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
337 writeb(0, &ch->ch_neo_uart->xoffchar2);
339 neo_pci_posting_flush(ch->ch_bd);
343 * No locks are assumed to be held when calling this function.
345 static inline void neo_clear_break(struct channel_t *ch, int force)
349 spin_lock_irqsave(&ch->ch_lock, flags);
351 /* Bail if we aren't currently sending a break. */
352 if (!ch->ch_stop_sending_break) {
353 spin_unlock_irqrestore(&ch->ch_lock, flags);
357 /* Turn break off, and unset some variables */
358 if (ch->ch_flags & CH_BREAK_SENDING) {
360 time_after_eq(jiffies, ch->ch_stop_sending_break)) {
361 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
363 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
364 neo_pci_posting_flush(ch->ch_bd);
365 ch->ch_flags &= ~(CH_BREAK_SENDING);
366 ch->ch_stop_sending_break = 0;
369 spin_unlock_irqrestore(&ch->ch_lock, flags);
373 * Parse the ISR register.
375 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
377 struct channel_t *ch;
382 ch = brd->channels[port];
383 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
386 /* Here we try to figure out what caused the interrupt to happen */
388 isr = readb(&ch->ch_neo_uart->isr_fcr);
390 /* Bail if no pending interrupt */
391 if (isr & UART_IIR_NO_INT)
395 * Yank off the upper 2 bits,
396 * which just show that the FIFO's are enabled.
398 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
400 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
401 /* Read data from uart -> queue */
404 neo_copy_data_from_uart_to_queue(ch);
406 /* Call our tty layer to enforce queue flow control if needed. */
407 spin_lock_irqsave(&ch->ch_lock, flags);
408 dgnc_check_queue_flow_control(ch);
409 spin_unlock_irqrestore(&ch->ch_lock, flags);
412 if (isr & UART_IIR_THRI) {
415 /* Transfer data (if any) from Write Queue -> UART. */
416 spin_lock_irqsave(&ch->ch_lock, flags);
417 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
418 spin_unlock_irqrestore(&ch->ch_lock, flags);
419 neo_copy_data_from_queue_to_uart(ch);
422 if (isr & UART_17158_IIR_XONXOFF) {
423 cause = readb(&ch->ch_neo_uart->xoffchar1);
426 * Since the UART detected either an XON or
427 * XOFF match, we need to figure out which
428 * one it was, so we can suspend or resume data flow.
430 if (cause == UART_17158_XON_DETECT) {
431 /* Is output stopped right now, if so, resume it */
432 if (brd->channels[port]->ch_flags & CH_STOP) {
433 spin_lock_irqsave(&ch->ch_lock,
435 ch->ch_flags &= ~(CH_STOP);
436 spin_unlock_irqrestore(&ch->ch_lock,
439 } else if (cause == UART_17158_XOFF_DETECT) {
440 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
441 spin_lock_irqsave(&ch->ch_lock,
443 ch->ch_flags |= CH_STOP;
444 spin_unlock_irqrestore(&ch->ch_lock,
450 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
452 * If we get here, this means the hardware is doing auto flow control.
453 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
457 cause = readb(&ch->ch_neo_uart->mcr);
458 /* Which pin is doing auto flow? RTS or DTR? */
459 if ((cause & 0x4) == 0) {
460 if (cause & UART_MCR_RTS) {
461 spin_lock_irqsave(&ch->ch_lock,
463 ch->ch_mostat |= UART_MCR_RTS;
464 spin_unlock_irqrestore(&ch->ch_lock,
467 spin_lock_irqsave(&ch->ch_lock,
469 ch->ch_mostat &= ~(UART_MCR_RTS);
470 spin_unlock_irqrestore(&ch->ch_lock,
474 if (cause & UART_MCR_DTR) {
475 spin_lock_irqsave(&ch->ch_lock,
477 ch->ch_mostat |= UART_MCR_DTR;
478 spin_unlock_irqrestore(&ch->ch_lock,
481 spin_lock_irqsave(&ch->ch_lock,
483 ch->ch_mostat &= ~(UART_MCR_DTR);
484 spin_unlock_irqrestore(&ch->ch_lock,
490 /* Parse any modem signal changes */
491 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
495 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
497 struct channel_t *ch;
502 * Check to make sure it didn't receive interrupt with a null board
503 * associated or a board pointer that wasn't ours.
505 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
508 if (port >= brd->maxports)
511 ch = brd->channels[port];
512 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
515 linestatus = readb(&ch->ch_neo_uart->lsr);
517 ch->ch_cached_lsr |= linestatus;
519 if (ch->ch_cached_lsr & UART_LSR_DR) {
522 /* Read data from uart -> queue */
523 neo_copy_data_from_uart_to_queue(ch);
524 spin_lock_irqsave(&ch->ch_lock, flags);
525 dgnc_check_queue_flow_control(ch);
526 spin_unlock_irqrestore(&ch->ch_lock, flags);
530 * The next 3 tests should *NOT* happen, as the above test
531 * should encapsulate all 3... At least, thats what Exar says.
534 if (linestatus & UART_LSR_PE)
537 if (linestatus & UART_LSR_FE)
540 if (linestatus & UART_LSR_BI)
543 if (linestatus & UART_LSR_OE) {
545 * Rx Oruns. Exar says that an orun will NOT corrupt
546 * the FIFO. It will just replace the holding register
547 * with this new data byte. So basically just ignore this.
548 * Probably we should eventually have an orun stat in our driver...
550 ch->ch_err_overrun++;
553 if (linestatus & UART_LSR_THRE) {
556 spin_lock_irqsave(&ch->ch_lock, flags);
557 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
558 spin_unlock_irqrestore(&ch->ch_lock, flags);
560 /* Transfer data (if any) from Write Queue -> UART. */
561 neo_copy_data_from_queue_to_uart(ch);
562 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
565 spin_lock_irqsave(&ch->ch_lock, flags);
566 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
567 spin_unlock_irqrestore(&ch->ch_lock, flags);
569 /* Transfer data (if any) from Write Queue -> UART. */
570 neo_copy_data_from_queue_to_uart(ch);
576 * Send any/all changes to the line to the UART.
578 static void neo_param(struct tty_struct *tty)
580 unsigned char lcr = 0;
581 unsigned char uart_lcr = 0;
582 unsigned char ier = 0;
583 unsigned char uart_ier = 0;
586 struct dgnc_board *bd;
587 struct channel_t *ch;
590 if (!tty || tty->magic != TTY_MAGIC)
593 un = (struct un_t *)tty->driver_data;
594 if (!un || un->magic != DGNC_UNIT_MAGIC)
598 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
602 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
606 * If baud rate is zero, flush queues, and set mval to drop DTR.
608 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
616 neo_flush_uart_write(ch);
617 neo_flush_uart_read(ch);
619 /* The baudrate is B0 so all modem lines are to be dropped. */
620 ch->ch_flags |= (CH_BAUD0);
621 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
622 neo_assert_modem_signals(ch);
626 } else if (ch->ch_custom_speed) {
627 baud = ch->ch_custom_speed;
628 /* Handle transition from B0 */
629 if (ch->ch_flags & CH_BAUD0) {
630 ch->ch_flags &= ~(CH_BAUD0);
633 * Bring back up RTS and DTR...
634 * Also handle RTS or DTR toggle if set.
636 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
637 ch->ch_mostat |= (UART_MCR_RTS);
638 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
639 ch->ch_mostat |= (UART_MCR_DTR);
645 ulong bauds[4][16] = {
649 600, 1200, 1800, 2400,
650 4800, 9600, 19200, 38400 },
651 { /* slowbaud & CBAUDEX */
652 0, 57600, 115200, 230400,
653 460800, 150, 200, 921600,
654 600, 1200, 1800, 2400,
655 4800, 9600, 19200, 38400 },
657 0, 57600, 76800, 115200,
658 131657, 153600, 230400, 460800,
659 921600, 1200, 1800, 2400,
660 4800, 9600, 19200, 38400 },
661 { /* fastbaud & CBAUDEX */
662 0, 57600, 115200, 230400,
663 460800, 150, 200, 921600,
664 600, 1200, 1800, 2400,
665 4800, 9600, 19200, 38400 }
668 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
669 if (!(ch->ch_tun.un_flags & UN_ISOPEN) &&
670 (un->un_type == DGNC_PRINT))
671 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
673 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
675 if (ch->ch_c_cflag & CBAUDEX)
678 if (ch->ch_digi.digi_flags & DIGI_FAST)
683 if ((iindex >= 0) && (iindex < 4) &&
684 (jindex >= 0) && (jindex < 16))
685 baud = bauds[iindex][jindex];
692 /* Handle transition from B0 */
693 if (ch->ch_flags & CH_BAUD0) {
694 ch->ch_flags &= ~(CH_BAUD0);
697 * Bring back up RTS and DTR...
698 * Also handle RTS or DTR toggle if set.
700 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
701 ch->ch_mostat |= (UART_MCR_RTS);
702 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
703 ch->ch_mostat |= (UART_MCR_DTR);
707 if (ch->ch_c_cflag & PARENB)
708 lcr |= UART_LCR_PARITY;
710 if (!(ch->ch_c_cflag & PARODD))
711 lcr |= UART_LCR_EPAR;
714 * Not all platforms support mark/space parity,
715 * so this will hide behind an ifdef.
718 if (ch->ch_c_cflag & CMSPAR)
719 lcr |= UART_LCR_SPAR;
722 if (ch->ch_c_cflag & CSTOPB)
723 lcr |= UART_LCR_STOP;
725 switch (ch->ch_c_cflag & CSIZE) {
727 lcr |= UART_LCR_WLEN5;
730 lcr |= UART_LCR_WLEN6;
733 lcr |= UART_LCR_WLEN7;
737 lcr |= UART_LCR_WLEN8;
741 uart_ier = readb(&ch->ch_neo_uart->ier);
744 uart_lcr = readb(&ch->ch_neo_uart->lcr);
749 quot = ch->ch_bd->bd_dividend / baud;
751 if (quot != 0 && ch->ch_old_baud != baud) {
752 ch->ch_old_baud = baud;
753 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
754 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
755 writeb((quot >> 8), &ch->ch_neo_uart->ier);
756 writeb(lcr, &ch->ch_neo_uart->lcr);
760 writeb(lcr, &ch->ch_neo_uart->lcr);
762 if (ch->ch_c_cflag & CREAD)
763 ier |= (UART_IER_RDI | UART_IER_RLSI);
765 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
768 * Have the UART interrupt on modem signal changes ONLY when
769 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
771 if ((ch->ch_digi.digi_flags & CTSPACE) ||
772 (ch->ch_digi.digi_flags & RTSPACE) ||
773 (ch->ch_c_cflag & CRTSCTS) ||
774 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
775 !(ch->ch_c_cflag & CLOCAL))
778 ier &= ~UART_IER_MSI;
780 ier |= UART_IER_THRI;
783 writeb(ier, &ch->ch_neo_uart->ier);
785 /* Set new start/stop chars */
786 neo_set_new_start_stop_chars(ch);
788 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
789 neo_set_cts_flow_control(ch);
790 } else if (ch->ch_c_iflag & IXON) {
791 /* If start/stop is set to disable, then we should disable flow control */
792 if ((ch->ch_startc == _POSIX_VDISABLE) ||
793 (ch->ch_stopc == _POSIX_VDISABLE))
794 neo_set_no_output_flow_control(ch);
796 neo_set_ixon_flow_control(ch);
798 neo_set_no_output_flow_control(ch);
801 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
802 neo_set_rts_flow_control(ch);
803 } else if (ch->ch_c_iflag & IXOFF) {
804 /* If start/stop is set to disable, then we should disable flow control */
805 if ((ch->ch_startc == _POSIX_VDISABLE) ||
806 (ch->ch_stopc == _POSIX_VDISABLE))
807 neo_set_no_input_flow_control(ch);
809 neo_set_ixoff_flow_control(ch);
811 neo_set_no_input_flow_control(ch);
815 * Adjust the RX FIFO Trigger level if baud is less than 9600.
816 * Not exactly elegant, but this is needed because of the Exar chip's
817 * delay on firing off the RX FIFO interrupt on slower baud rates.
820 writeb(1, &ch->ch_neo_uart->rfifo);
824 neo_assert_modem_signals(ch);
826 /* Get current status of the modem signals now */
827 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
831 * Our board poller function.
833 static void neo_tasklet(unsigned long data)
835 struct dgnc_board *bd = (struct dgnc_board *)data;
836 struct channel_t *ch;
842 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
845 /* Cache a couple board values */
846 spin_lock_irqsave(&bd->bd_lock, flags);
849 spin_unlock_irqrestore(&bd->bd_lock, flags);
852 * Do NOT allow the interrupt routine to read the intr registers
853 * Until we release this lock.
855 spin_lock_irqsave(&bd->bd_intr_lock, flags);
858 * If board is ready, parse deeper to see if there is anything to do.
860 if ((state == BOARD_READY) && (ports > 0)) {
861 /* Loop on each port */
862 for (i = 0; i < ports; i++) {
863 ch = bd->channels[i];
865 /* Just being careful... */
866 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
870 * NOTE: Remember you CANNOT hold any channel
871 * locks when calling the input routine.
873 * During input processing, its possible we
874 * will call the Linux ld, which might in turn,
875 * do a callback right back into us, resulting
876 * in us trying to grab the channel lock twice!
881 * Channel lock is grabbed and then released
882 * inside both of these routines, but neither
883 * call anything else that could call back into us.
885 neo_copy_data_from_queue_to_uart(ch);
886 dgnc_wakeup_writes(ch);
889 * Call carrier carrier function, in case something
895 * Check to see if we need to turn off a sending break.
896 * The timing check is done inside clear_break()
898 if (ch->ch_stop_sending_break)
899 neo_clear_break(ch, 0);
903 /* Allow interrupt routine to access the interrupt register again */
904 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
910 * Neo specific interrupt handler.
912 static irqreturn_t neo_intr(int irq, void *voidbrd)
914 struct dgnc_board *brd = voidbrd;
915 struct channel_t *ch;
920 unsigned long flags2;
923 * Check to make sure it didn't receive interrupt with a null board
924 * associated or a board pointer that wasn't ours.
926 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
931 /* Lock out the slow poller from running on this board. */
932 spin_lock_irqsave(&brd->bd_intr_lock, flags);
935 * Read in "extended" IRQ information from the 32bit Neo register.
936 * Bits 0-7: What port triggered the interrupt.
937 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
939 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
942 * If 0, no interrupts pending.
943 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
946 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
950 /* At this point, we have at least SOMETHING to service, dig further... */
952 /* Loop on each port */
953 while ((uart_poll & 0xff) != 0) {
954 type = uart_poll >> (8 + (port * 3));
957 uart_poll &= ~(0x01 << port);
959 /* Switch on type of interrupt we have */
961 case UART_17158_RXRDY_TIMEOUT:
963 * RXRDY Time-out is cleared by reading data in the
964 * RX FIFO until it falls below the trigger level.
967 /* Verify the port is in range. */
968 if (port >= brd->nasync)
971 ch = brd->channels[port];
972 neo_copy_data_from_uart_to_queue(ch);
974 /* Call our tty layer to enforce queue flow control if needed. */
975 spin_lock_irqsave(&ch->ch_lock, flags2);
976 dgnc_check_queue_flow_control(ch);
977 spin_unlock_irqrestore(&ch->ch_lock, flags2);
981 case UART_17158_RX_LINE_STATUS:
983 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
985 neo_parse_lsr(brd, port);
988 case UART_17158_TXRDY:
990 * TXRDY interrupt clears after reading ISR register for the UART channel.
994 * Yes, this is odd...
995 * Why would I check EVERY possibility of type of
996 * interrupt, when we know its TXRDY???
997 * Becuz for some reason, even tho we got triggered for TXRDY,
998 * it seems to be occasionally wrong. Instead of TX, which
999 * it should be, I was getting things like RXDY too. Weird.
1001 neo_parse_isr(brd, port);
1004 case UART_17158_MSR:
1006 * MSR or flow control was seen.
1008 neo_parse_isr(brd, port);
1013 * The UART triggered us with a bogus interrupt type.
1014 * It appears the Exar chip, when REALLY bogged down, will throw
1015 * these once and awhile.
1016 * Its harmless, just ignore it and move on.
1025 * Schedule tasklet to more in-depth servicing at a better time.
1027 tasklet_schedule(&brd->helper_tasklet);
1029 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1035 * Neo specific way of turning off the receiver.
1036 * Used as a way to enforce queue flow control when in
1037 * hardware flow control mode.
1039 static void neo_disable_receiver(struct channel_t *ch)
1041 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1043 tmp &= ~(UART_IER_RDI);
1044 writeb(tmp, &ch->ch_neo_uart->ier);
1045 neo_pci_posting_flush(ch->ch_bd);
1049 * Neo specific way of turning on the receiver.
1050 * Used as a way to un-enforce queue flow control when in
1051 * hardware flow control mode.
1053 static void neo_enable_receiver(struct channel_t *ch)
1055 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1057 tmp |= (UART_IER_RDI);
1058 writeb(tmp, &ch->ch_neo_uart->ier);
1059 neo_pci_posting_flush(ch->ch_bd);
1062 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1065 unsigned char linestatus = 0;
1066 unsigned char error_mask = 0;
1071 unsigned long flags;
1073 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1076 spin_lock_irqsave(&ch->ch_lock, flags);
1078 /* cache head and tail of queue */
1079 head = ch->ch_r_head & RQUEUEMASK;
1080 tail = ch->ch_r_tail & RQUEUEMASK;
1082 /* Get our cached LSR */
1083 linestatus = ch->ch_cached_lsr;
1084 ch->ch_cached_lsr = 0;
1086 /* Store how much space we have left in the queue */
1087 qleft = tail - head - 1;
1089 qleft += RQUEUEMASK + 1;
1092 * If the UART is not in FIFO mode, force the FIFO copy to
1093 * NOT be run, by setting total to 0.
1095 * On the other hand, if the UART IS in FIFO mode, then ask
1096 * the UART to give us an approximation of data it has RX'ed.
1098 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1101 total = readb(&ch->ch_neo_uart->rfifo);
1104 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1106 * This resolves a problem/bug with the Exar chip that sometimes
1107 * returns a bogus value in the rfifo register.
1108 * The count can be any where from 0-3 bytes "off".
1109 * Bizarre, but true.
1111 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1118 * Finally, bound the copy to make sure we don't overflow
1120 * The byte by byte copy loop below this loop this will
1121 * deal with the queue overflow possibility.
1123 total = min(total, qleft);
1127 * Grab the linestatus register, we need to check
1128 * to see if there are any errors in the FIFO.
1130 linestatus = readb(&ch->ch_neo_uart->lsr);
1133 * Break out if there is a FIFO error somewhere.
1134 * This will allow us to go byte by byte down below,
1135 * finding the exact location of the error.
1137 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1140 /* Make sure we don't go over the end of our queue */
1141 n = min(((uint)total), (RQUEUESIZE - (uint)head));
1144 * Cut down n even further if needed, this is to fix
1145 * a problem with memcpy_fromio() with the Neo on the
1146 * IBM pSeries platform.
1147 * 15 bytes max appears to be the magic number.
1149 n = min_t(uint, n, 12);
1152 * Since we are grabbing the linestatus register, which
1153 * will reset some bits after our read, we need to ensure
1154 * we don't miss our TX FIFO emptys.
1156 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1157 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1161 /* Copy data from uart to the queue */
1162 memcpy_fromio(ch->ch_rqueue + head,
1163 &ch->ch_neo_uart->txrxburst, n);
1166 * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
1167 * that all the data currently in the FIFO is free of
1168 * breaks and parity/frame/orun errors.
1170 memset(ch->ch_equeue + head, 0, n);
1172 /* Add to and flip head if needed */
1173 head = (head + n) & RQUEUEMASK;
1176 ch->ch_rxcount += n;
1180 * Create a mask to determine whether we should
1181 * insert the character (if any) into our queue.
1183 if (ch->ch_c_iflag & IGNBRK)
1184 error_mask |= UART_LSR_BI;
1187 * Now cleanup any leftover bytes still in the UART.
1188 * Also deal with any possible queue overflow here as well.
1192 * Its possible we have a linestatus from the loop above
1193 * this, so we "OR" on any extra bits.
1195 linestatus |= readb(&ch->ch_neo_uart->lsr);
1198 * If the chip tells us there is no more data pending to
1199 * be read, we can then leave.
1200 * But before we do, cache the linestatus, just in case.
1202 if (!(linestatus & UART_LSR_DR)) {
1203 ch->ch_cached_lsr = linestatus;
1207 /* No need to store this bit */
1208 linestatus &= ~UART_LSR_DR;
1211 * Since we are grabbing the linestatus register, which
1212 * will reset some bits after our read, we need to ensure
1213 * we don't miss our TX FIFO emptys.
1215 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1216 linestatus &= ~(UART_LSR_THRE |
1217 UART_17158_TX_AND_FIFO_CLR);
1218 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1222 * Discard character if we are ignoring the error mask.
1224 if (linestatus & error_mask) {
1225 unsigned char discard;
1228 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1233 * If our queue is full, we have no choice but to drop some data.
1234 * The assumption is that HWFLOW or SWFLOW should have stopped
1235 * things way way before we got to this point.
1237 * I decided that I wanted to ditch the oldest data first,
1238 * I hope thats okay with everyone? Yes? Good.
1241 tail = (tail + 1) & RQUEUEMASK;
1242 ch->ch_r_tail = tail;
1243 ch->ch_err_overrun++;
1247 memcpy_fromio(ch->ch_rqueue + head,
1248 &ch->ch_neo_uart->txrxburst, 1);
1249 ch->ch_equeue[head] = (unsigned char)linestatus;
1251 /* Ditch any remaining linestatus value. */
1254 /* Add to and flip head if needed */
1255 head = (head + 1) & RQUEUEMASK;
1262 * Write new final heads to channel structure.
1264 ch->ch_r_head = head & RQUEUEMASK;
1265 ch->ch_e_head = head & EQUEUEMASK;
1267 spin_unlock_irqrestore(&ch->ch_lock, flags);
1271 * This function basically goes to sleep for secs, or until
1272 * it gets signalled that the port has fully drained.
1274 static int neo_drain(struct tty_struct *tty, uint seconds)
1276 unsigned long flags;
1277 struct channel_t *ch;
1281 if (!tty || tty->magic != TTY_MAGIC)
1284 un = (struct un_t *)tty->driver_data;
1285 if (!un || un->magic != DGNC_UNIT_MAGIC)
1289 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1292 spin_lock_irqsave(&ch->ch_lock, flags);
1293 un->un_flags |= UN_EMPTY;
1294 spin_unlock_irqrestore(&ch->ch_lock, flags);
1297 * Go to sleep waiting for the tty layer to wake me back up when
1298 * the empty flag goes away.
1300 rc = wait_event_interruptible_timeout(un->un_flags_wait,
1301 ((un->un_flags & UN_EMPTY) == 0),
1302 msecs_to_jiffies(seconds * 1000));
1304 /* If ret is non-zero, user ctrl-c'ed us */
1309 * Flush the WRITE FIFO on the Neo.
1311 * NOTE: Channel lock MUST be held before calling this function!
1313 static void neo_flush_uart_write(struct channel_t *ch)
1315 unsigned char tmp = 0;
1318 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1321 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
1322 &ch->ch_neo_uart->isr_fcr);
1323 neo_pci_posting_flush(ch->ch_bd);
1325 for (i = 0; i < 10; i++) {
1326 /* Check to see if the UART feels it completely flushed the FIFO. */
1327 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1334 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1338 * Flush the READ FIFO on the Neo.
1340 * NOTE: Channel lock MUST be held before calling this function!
1342 static void neo_flush_uart_read(struct channel_t *ch)
1344 unsigned char tmp = 0;
1347 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1350 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR,
1351 &ch->ch_neo_uart->isr_fcr);
1352 neo_pci_posting_flush(ch->ch_bd);
1354 for (i = 0; i < 10; i++) {
1355 /* Check to see if the UART feels it completely flushed the FIFO. */
1356 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1364 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1371 uint len_written = 0;
1372 unsigned long flags;
1374 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1377 spin_lock_irqsave(&ch->ch_lock, flags);
1379 /* No data to write to the UART */
1380 if (ch->ch_w_tail == ch->ch_w_head)
1383 /* If port is "stopped", don't send any data to the UART */
1384 if ((ch->ch_flags & CH_FORCED_STOP) ||
1385 (ch->ch_flags & CH_BREAK_SENDING))
1389 * If FIFOs are disabled. Send data directly to txrx register
1391 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1392 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1394 /* Cache the LSR bits for later parsing */
1395 ch->ch_cached_lsr |= lsrbits;
1396 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1397 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1400 * If RTS Toggle mode is on, turn on RTS now if not already set,
1401 * and make sure we get an event when the data transfer has completed.
1403 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1404 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1405 ch->ch_mostat |= (UART_MCR_RTS);
1406 neo_assert_modem_signals(ch);
1408 ch->ch_tun.un_flags |= (UN_EMPTY);
1411 * If DTR Toggle mode is on, turn on DTR now if not already set,
1412 * and make sure we get an event when the data transfer has completed.
1414 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1415 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1416 ch->ch_mostat |= (UART_MCR_DTR);
1417 neo_assert_modem_signals(ch);
1419 ch->ch_tun.un_flags |= (UN_EMPTY);
1422 writeb(ch->ch_wqueue[ch->ch_w_tail],
1423 &ch->ch_neo_uart->txrx);
1425 ch->ch_w_tail &= WQUEUEMASK;
1433 * We have to do it this way, because of the EXAR TXFIFO count bug.
1435 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1436 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1441 n = readb(&ch->ch_neo_uart->tfifo);
1443 if ((unsigned int)n > ch->ch_t_tlevel)
1446 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1448 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1451 /* cache head and tail of queue */
1452 head = ch->ch_w_head & WQUEUEMASK;
1453 tail = ch->ch_w_tail & WQUEUEMASK;
1454 qlen = (head - tail) & WQUEUEMASK;
1456 /* Find minimum of the FIFO space, versus queue length */
1460 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1467 * If RTS Toggle mode is on, turn on RTS now if not already set,
1468 * and make sure we get an event when the data transfer has completed.
1470 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1471 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1472 ch->ch_mostat |= (UART_MCR_RTS);
1473 neo_assert_modem_signals(ch);
1475 ch->ch_tun.un_flags |= (UN_EMPTY);
1479 * If DTR Toggle mode is on, turn on DTR now if not already set,
1480 * and make sure we get an event when the data transfer has completed.
1482 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1483 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1484 ch->ch_mostat |= (UART_MCR_DTR);
1485 neo_assert_modem_signals(ch);
1487 ch->ch_tun.un_flags |= (UN_EMPTY);
1490 memcpy_toio(&ch->ch_neo_uart->txrxburst,
1491 ch->ch_wqueue + tail, s);
1493 /* Add and flip queue if needed */
1494 tail = (tail + s) & WQUEUEMASK;
1496 ch->ch_txcount += s;
1500 /* Update the final tail */
1501 ch->ch_w_tail = tail & WQUEUEMASK;
1503 if (len_written > 0) {
1504 neo_pci_posting_flush(ch->ch_bd);
1505 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1509 spin_unlock_irqrestore(&ch->ch_lock, flags);
1512 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1514 unsigned char msignals = signals;
1516 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1520 * Do altpin switching. Altpin switches DCD and DSR.
1521 * This prolly breaks DSRPACE, so we should be more clever here.
1523 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1524 unsigned char mswap = msignals;
1526 if (mswap & UART_MSR_DDCD) {
1527 msignals &= ~UART_MSR_DDCD;
1528 msignals |= UART_MSR_DDSR;
1530 if (mswap & UART_MSR_DDSR) {
1531 msignals &= ~UART_MSR_DDSR;
1532 msignals |= UART_MSR_DDCD;
1534 if (mswap & UART_MSR_DCD) {
1535 msignals &= ~UART_MSR_DCD;
1536 msignals |= UART_MSR_DSR;
1538 if (mswap & UART_MSR_DSR) {
1539 msignals &= ~UART_MSR_DSR;
1540 msignals |= UART_MSR_DCD;
1544 /* Scrub off lower bits. They signify delta's, which I don't care about */
1547 if (msignals & UART_MSR_DCD)
1548 ch->ch_mistat |= UART_MSR_DCD;
1550 ch->ch_mistat &= ~UART_MSR_DCD;
1552 if (msignals & UART_MSR_DSR)
1553 ch->ch_mistat |= UART_MSR_DSR;
1555 ch->ch_mistat &= ~UART_MSR_DSR;
1557 if (msignals & UART_MSR_RI)
1558 ch->ch_mistat |= UART_MSR_RI;
1560 ch->ch_mistat &= ~UART_MSR_RI;
1562 if (msignals & UART_MSR_CTS)
1563 ch->ch_mistat |= UART_MSR_CTS;
1565 ch->ch_mistat &= ~UART_MSR_CTS;
1568 /* Make the UART raise any of the output signals we want up */
1569 static void neo_assert_modem_signals(struct channel_t *ch)
1573 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1576 out = ch->ch_mostat;
1578 if (ch->ch_flags & CH_LOOPBACK)
1579 out |= UART_MCR_LOOP;
1581 writeb(out, &ch->ch_neo_uart->mcr);
1582 neo_pci_posting_flush(ch->ch_bd);
1584 /* Give time for the UART to actually raise/drop the signals */
1588 static void neo_send_start_character(struct channel_t *ch)
1590 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1593 if (ch->ch_startc != _POSIX_VDISABLE) {
1595 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1596 neo_pci_posting_flush(ch->ch_bd);
1601 static void neo_send_stop_character(struct channel_t *ch)
1603 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1606 if (ch->ch_stopc != _POSIX_VDISABLE) {
1607 ch->ch_xoff_sends++;
1608 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1609 neo_pci_posting_flush(ch->ch_bd);
1617 static void neo_uart_init(struct channel_t *ch)
1619 writeb(0, &ch->ch_neo_uart->ier);
1620 writeb(0, &ch->ch_neo_uart->efr);
1621 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1623 /* Clear out UART and FIFO */
1624 readb(&ch->ch_neo_uart->txrx);
1625 writeb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1626 &ch->ch_neo_uart->isr_fcr);
1627 readb(&ch->ch_neo_uart->lsr);
1628 readb(&ch->ch_neo_uart->msr);
1630 ch->ch_flags |= CH_FIFO_ENABLED;
1632 /* Assert any signals we want up */
1633 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1634 neo_pci_posting_flush(ch->ch_bd);
1638 * Make the UART completely turn off.
1640 static void neo_uart_off(struct channel_t *ch)
1642 /* Turn off UART enhanced bits */
1643 writeb(0, &ch->ch_neo_uart->efr);
1645 /* Stop all interrupts from occurring. */
1646 writeb(0, &ch->ch_neo_uart->ier);
1647 neo_pci_posting_flush(ch->ch_bd);
1650 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1652 unsigned char left = 0;
1653 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1655 /* We must cache the LSR as some of the bits get reset once read... */
1656 ch->ch_cached_lsr |= lsr;
1658 /* Determine whether the Transmitter is empty or not */
1659 if (!(lsr & UART_LSR_TEMT)) {
1660 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1661 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1664 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1671 /* Channel lock MUST be held by the calling function! */
1672 static void neo_send_break(struct channel_t *ch, int msecs)
1675 * If we receive a time of 0, this means turn off the break.
1678 if (ch->ch_flags & CH_BREAK_SENDING) {
1679 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1681 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1682 neo_pci_posting_flush(ch->ch_bd);
1683 ch->ch_flags &= ~(CH_BREAK_SENDING);
1684 ch->ch_stop_sending_break = 0;
1690 * Set the time we should stop sending the break.
1691 * If we are already sending a break, toss away the existing
1692 * time to stop, and use this new value instead.
1694 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1696 /* Tell the UART to start sending the break */
1697 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1698 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1700 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1701 neo_pci_posting_flush(ch->ch_bd);
1702 ch->ch_flags |= (CH_BREAK_SENDING);
1707 * neo_send_immediate_char.
1709 * Sends a specific character as soon as possible to the UART,
1710 * jumping over any bytes that might be in the write queue.
1712 * The channel lock MUST be held by the calling function.
1714 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1716 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1719 writeb(c, &ch->ch_neo_uart->txrx);
1720 neo_pci_posting_flush(ch->ch_bd);
1723 static unsigned int neo_read_eeprom(unsigned char __iomem *base,
1724 unsigned int address)
1726 unsigned int enable;
1728 unsigned int databit;
1731 /* enable chip select */
1732 writeb(NEO_EECS, base + NEO_EEREG);
1734 enable = address | 0x180;
1736 for (bits = 9; bits--; ) {
1737 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1738 /* Set read address */
1739 writeb(databit | NEO_EECS, base + NEO_EEREG);
1740 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1745 for (bits = 17; bits--; ) {
1746 /* clock to EEPROM */
1747 writeb(NEO_EECS, base + NEO_EEREG);
1748 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1751 if (readb(base + NEO_EEREG) & NEO_EEDO)
1755 /* clock falling edge */
1756 writeb(NEO_EECS, base + NEO_EEREG);
1758 /* drop chip select */
1759 writeb(0x00, base + NEO_EEREG);
1764 static void neo_vpd(struct dgnc_board *brd)
1769 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1772 if (!brd->re_map_membase)
1775 /* Store the VPD into our buffer */
1776 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1777 a = neo_read_eeprom(brd->re_map_membase, i);
1778 brd->vpd[i * 2] = a & 0xff;
1779 brd->vpd[(i * 2) + 1] = (a >> 8) & 0xff;
1783 * brd->vpd has different name tags by below index.
1784 * 0x08 : long resource name tag
1785 * 0x10 : long resource name tage (PCI-66 files)
1786 * 0x7F : small resource end tag
1788 if (((brd->vpd[0x08] != 0x82) &&
1789 (brd->vpd[0x10] != 0x82)) ||
1790 (brd->vpd[0x7F] != 0x78)) {
1791 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1793 /* Search for the serial number */
1794 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1795 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1796 strncpy(brd->serial_num, &brd->vpd[i + 3], 9);