drivers/staging/dwc2/core.c

   1 /*
   2  * core.c - DesignWare HS OTG Controller common routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * The Core code provides basic services for accessing and managing the
  39  * DWC_otg hardware. These services are used by both the Host Controller
  40  * Driver and the Peripheral Controller Driver.
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 /**
  60  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
  61  * used in both device and host modes
  62  *
  63  * @hsotg: Programming view of the DWC_otg controller
  64  */
  65 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  66 {
  67         u32 intmsk;
  68
  69         /* Clear any pending OTG Interrupts */
  70         writel(0xffffffff, hsotg->regs + GOTGINT);
  71
  72         /* Clear any pending interrupts */
  73         writel(0xffffffff, hsotg->regs + GINTSTS);
  74
  75         /* Enable the interrupts in the GINTMSK */
  76         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  77
  78         if (hsotg->core_params->dma_enable <= 0)
  79                 intmsk |= GINTSTS_RXFLVL;
  80
  81         intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  82                   GINTSTS_SESSREQINT;
  83
  84         writel(intmsk, hsotg->regs + GINTMSK);
  85 }
  86
  87 /*
  88  * Initializes the FSLSPClkSel field of the HCFG register depending on the
  89  * PHY type
  90  */
  91 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
  92 {
  93         u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
  94         u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
  95         u32 hcfg, val;
  96
  97         if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
  98              fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
  99              hsotg->core_params->ulpi_fs_ls > 0) ||
 100             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 101                 /* Full speed PHY */
 102                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 103         } else {
 104                 /* High speed PHY running at full speed or high speed */
 105                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 106         }
 107
 108         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 109         hcfg = readl(hsotg->regs + HCFG);
 110         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 111         hcfg |= val;
 112         writel(hcfg, hsotg->regs + HCFG);
 113 }
 114
 115 /*
 116  * Do core a soft reset of the core.  Be careful with this because it
 117  * resets all the internal state machines of the core.
 118  */
 119 static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
 120 {
 121         u32 greset;
 122         int count = 0;
 123
 124         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 125
 126         /* Wait for AHB master IDLE state */
 127         do {
 128                 usleep_range(20000, 40000);
 129                 greset = readl(hsotg->regs + GRSTCTL);
 130                 if (++count > 50) {
 131                         dev_warn(hsotg->dev,
 132                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
 133                                  __func__, greset);
 134                         return;
 135                 }
 136         } while (!(greset & GRSTCTL_AHBIDLE));
 137
 138         /* Core Soft Reset */
 139         count = 0;
 140         greset |= GRSTCTL_CSFTRST;
 141         writel(greset, hsotg->regs + GRSTCTL);
 142         do {
 143                 usleep_range(20000, 40000);
 144                 greset = readl(hsotg->regs + GRSTCTL);
 145                 if (++count > 50) {
 146                         dev_warn(hsotg->dev,
 147                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
 148                                  __func__, greset);
 149                         break;
 150                 }
 151         } while (greset & GRSTCTL_CSFTRST);
 152
 153         /*
 154          * NOTE: This long sleep is _very_ important, otherwise the core will
 155          * not stay in host mode after a connector ID change!
 156          */
 157         usleep_range(150000, 200000);
 158 }
 159
 160 static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 161 {
 162         u32 usbcfg, i2cctl;
 163
 164         /*
 165          * core_init() is now called on every switch so only call the
 166          * following for the first time through
 167          */
 168         if (select_phy) {
 169                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 170                 usbcfg = readl(hsotg->regs + GUSBCFG);
 171                 usbcfg |= GUSBCFG_PHYSEL;
 172                 writel(usbcfg, hsotg->regs + GUSBCFG);
 173
 174                 /* Reset after a PHY select */
 175                 dwc2_core_reset(hsotg);
 176         }
 177
 178         /*
 179          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 180          * do this on HNP Dev/Host mode switches (done in dev_init and
 181          * host_init).
 182          */
 183         if (dwc2_is_host_mode(hsotg))
 184                 dwc2_init_fs_ls_pclk_sel(hsotg);
 185
 186         if (hsotg->core_params->i2c_enable > 0) {
 187                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 188
 189                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 190                 usbcfg = readl(hsotg->regs + GUSBCFG);
 191                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 192                 writel(usbcfg, hsotg->regs + GUSBCFG);
 193
 194                 /* Program GI2CCTL.I2CEn */
 195                 i2cctl = readl(hsotg->regs + GI2CCTL);
 196                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 197                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 198                 i2cctl &= ~GI2CCTL_I2CEN;
 199                 writel(i2cctl, hsotg->regs + GI2CCTL);
 200                 i2cctl |= GI2CCTL_I2CEN;
 201                 writel(i2cctl, hsotg->regs + GI2CCTL);
 202         }
 203 }
 204
 205 static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 206 {
 207         u32 usbcfg;
 208
 209         if (!select_phy)
 210                 return;
 211
 212         usbcfg = readl(hsotg->regs + GUSBCFG);
 213
 214         /*
 215          * HS PHY parameters. These parameters are preserved during soft reset
 216          * so only program the first time. Do a soft reset immediately after
 217          * setting phyif.
 218          */
 219         switch (hsotg->core_params->phy_type) {
 220         case DWC2_PHY_TYPE_PARAM_ULPI:
 221                 /* ULPI interface */
 222                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 223                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 224                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 225                 if (hsotg->core_params->phy_ulpi_ddr > 0)
 226                         usbcfg |= GUSBCFG_DDRSEL;
 227                 break;
 228         case DWC2_PHY_TYPE_PARAM_UTMI:
 229                 /* UTMI+ interface */
 230                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 231                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 232                 if (hsotg->core_params->phy_utmi_width == 16)
 233                         usbcfg |= GUSBCFG_PHYIF16;
 234                 break;
 235         default:
 236                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 237                 break;
 238         }
 239
 240         writel(usbcfg, hsotg->regs + GUSBCFG);
 241
 242         /* Reset after setting the PHY parameters */
 243         dwc2_core_reset(hsotg);
 244 }
 245
 246 static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 247 {
 248         u32 usbcfg, hs_phy_type, fs_phy_type;
 249
 250         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
 251             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 252                 /* If FS mode with FS PHY */
 253                 dwc2_fs_phy_init(hsotg, select_phy);
 254         } else {
 255                 /* High speed PHY */
 256                 dwc2_hs_phy_init(hsotg, select_phy);
 257         }
 258
 259         hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
 260         fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
 261
 262         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 263             fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 264             hsotg->core_params->ulpi_fs_ls > 0) {
 265                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 266                 usbcfg = readl(hsotg->regs + GUSBCFG);
 267                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 268                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 269                 writel(usbcfg, hsotg->regs + GUSBCFG);
 270         } else {
 271                 usbcfg = readl(hsotg->regs + GUSBCFG);
 272                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 273                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 274                 writel(usbcfg, hsotg->regs + GUSBCFG);
 275         }
 276 }
 277
 278 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 279 {
 280         u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
 281
 282         switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
 283         case GHWCFG2_EXT_DMA_ARCH:
 284                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 285                 return -EINVAL;
 286
 287         case GHWCFG2_INT_DMA_ARCH:
 288                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 289                 if (hsotg->core_params->ahbcfg != -1) {
 290                         ahbcfg &= GAHBCFG_CTRL_MASK;
 291                         ahbcfg |= hsotg->core_params->ahbcfg &
 292                                   ~GAHBCFG_CTRL_MASK;
 293                 }
 294                 break;
 295
 296         case GHWCFG2_SLAVE_ONLY_ARCH:
 297         default:
 298                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 299                 break;
 300         }
 301
 302         dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
 303                 hsotg->core_params->dma_enable,
 304                 hsotg->core_params->dma_desc_enable);
 305
 306         if (hsotg->core_params->dma_enable > 0) {
 307                 if (hsotg->core_params->dma_desc_enable > 0)
 308                         dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
 309                 else
 310                         dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
 311         } else {
 312                 dev_dbg(hsotg->dev, "Using Slave mode\n");
 313                 hsotg->core_params->dma_desc_enable = 0;
 314         }
 315
 316         if (hsotg->core_params->dma_enable > 0)
 317                 ahbcfg |= GAHBCFG_DMA_EN;
 318
 319         writel(ahbcfg, hsotg->regs + GAHBCFG);
 320
 321         return 0;
 322 }
 323
 324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 325 {
 326         u32 usbcfg;
 327
 328         usbcfg = readl(hsotg->regs + GUSBCFG);
 329         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 330
 331         switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
 332         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 333                 if (hsotg->core_params->otg_cap ==
 334                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 335                         usbcfg |= GUSBCFG_HNPCAP;
 336                 if (hsotg->core_params->otg_cap !=
 337                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 338                         usbcfg |= GUSBCFG_SRPCAP;
 339                 break;
 340
 341         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 342         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 343         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 344                 if (hsotg->core_params->otg_cap !=
 345                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 346                         usbcfg |= GUSBCFG_SRPCAP;
 347                 break;
 348
 349         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 350         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 351         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 352         default:
 353                 break;
 354         }
 355
 356         writel(usbcfg, hsotg->regs + GUSBCFG);
 357 }
 358
 359 /**
 360  * dwc2_core_init() - Initializes the DWC_otg controller registers and
 361  * prepares the core for device mode or host mode operation
 362  *
 363  * @hsotg:      Programming view of the DWC_otg controller
 364  * @select_phy: If true then also set the Phy type
 365  * @irq:        If >= 0, the irq to register
 366  */
 367 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
 368 {
 369         u32 usbcfg, otgctl;
 370         int retval;
 371
 372         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 373
 374         usbcfg = readl(hsotg->regs + GUSBCFG);
 375
 376         /* Set ULPI External VBUS bit if needed */
 377         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
 378         if (hsotg->core_params->phy_ulpi_ext_vbus ==
 379                                 DWC2_PHY_ULPI_EXTERNAL_VBUS)
 380                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
 381
 382         /* Set external TS Dline pulsing bit if needed */
 383         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
 384         if (hsotg->core_params->ts_dline > 0)
 385                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
 386
 387         writel(usbcfg, hsotg->regs + GUSBCFG);
 388
 389         /* Reset the Controller */
 390         dwc2_core_reset(hsotg);
 391
 392         dev_dbg(hsotg->dev, "num_dev_perio_in_ep=%d\n",
 393                 hsotg->hwcfg4 >> GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT &
 394                 GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK >>
 395                                 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT);
 396
 397         hsotg->total_fifo_size = hsotg->hwcfg3 >> GHWCFG3_DFIFO_DEPTH_SHIFT &
 398                         GHWCFG3_DFIFO_DEPTH_MASK >> GHWCFG3_DFIFO_DEPTH_SHIFT;
 399         hsotg->rx_fifo_size = readl(hsotg->regs + GRXFSIZ);
 400         hsotg->nperio_tx_fifo_size =
 401                         readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
 402
 403         dev_dbg(hsotg->dev, "Total FIFO SZ=%d\n", hsotg->total_fifo_size);
 404         dev_dbg(hsotg->dev, "RxFIFO SZ=%d\n", hsotg->rx_fifo_size);
 405         dev_dbg(hsotg->dev, "NP TxFIFO SZ=%d\n", hsotg->nperio_tx_fifo_size);
 406
 407         /*
 408          * This needs to happen in FS mode before any other programming occurs
 409          */
 410         dwc2_phy_init(hsotg, select_phy);
 411
 412         /* Program the GAHBCFG Register */
 413         retval = dwc2_gahbcfg_init(hsotg);
 414         if (retval)
 415                 return retval;
 416
 417         /* Program the GUSBCFG register */
 418         dwc2_gusbcfg_init(hsotg);
 419
 420         /* Program the GOTGCTL register */
 421         otgctl = readl(hsotg->regs + GOTGCTL);
 422         otgctl &= ~GOTGCTL_OTGVER;
 423         if (hsotg->core_params->otg_ver > 0)
 424                 otgctl |= GOTGCTL_OTGVER;
 425         writel(otgctl, hsotg->regs + GOTGCTL);
 426         dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
 427
 428         /* Clear the SRP success bit for FS-I2c */
 429         hsotg->srp_success = 0;
 430
 431         if (irq >= 0) {
 432                 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 433                         irq);
 434                 retval = devm_request_irq(hsotg->dev, irq,
 435                                           dwc2_handle_common_intr, IRQF_SHARED,
 436                                           dev_name(hsotg->dev), hsotg);
 437                 if (retval)
 438                         return retval;
 439         }
 440
 441         /* Enable common interrupts */
 442         dwc2_enable_common_interrupts(hsotg);
 443
 444         /*
 445          * Do device or host intialization based on mode during PCD and
 446          * HCD initialization
 447          */
 448         if (dwc2_is_host_mode(hsotg)) {
 449                 dev_dbg(hsotg->dev, "Host Mode\n");
 450                 hsotg->op_state = OTG_STATE_A_HOST;
 451         } else {
 452                 dev_dbg(hsotg->dev, "Device Mode\n");
 453                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 454         }
 455
 456         return 0;
 457 }
 458
 459 /**
 460  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 461  *
 462  * @hsotg: Programming view of DWC_otg controller
 463  */
 464 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 465 {
 466         u32 intmsk;
 467
 468         dev_dbg(hsotg->dev, "%s()\n", __func__);
 469
 470         /* Disable all interrupts */
 471         writel(0, hsotg->regs + GINTMSK);
 472         writel(0, hsotg->regs + HAINTMSK);
 473
 474         /* Clear any pending interrupts */
 475         writel(0xffffffff, hsotg->regs + GINTSTS);
 476
 477         /* Enable the common interrupts */
 478         dwc2_enable_common_interrupts(hsotg);
 479
 480         /* Enable host mode interrupts without disturbing common interrupts */
 481         intmsk = readl(hsotg->regs + GINTMSK);
 482         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 483         writel(intmsk, hsotg->regs + GINTMSK);
 484 }
 485
 486 /**
 487  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 488  *
 489  * @hsotg: Programming view of DWC_otg controller
 490  */
 491 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 492 {
 493         u32 intmsk = readl(hsotg->regs + GINTMSK);
 494
 495         /* Disable host mode interrupts without disturbing common interrupts */
 496         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 497                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
 498         writel(intmsk, hsotg->regs + GINTMSK);
 499 }
 500
 501 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 502 {
 503         struct dwc2_core_params *params = hsotg->core_params;
 504         u32 rxfsiz, nptxfsiz, ptxfsiz, hptxfsiz, dfifocfg;
 505
 506         if (!params->enable_dynamic_fifo)
 507                 return;
 508
 509         dev_dbg(hsotg->dev, "Total FIFO Size=%d\n", hsotg->total_fifo_size);
 510         dev_dbg(hsotg->dev, "Rx FIFO Size=%d\n", params->host_rx_fifo_size);
 511         dev_dbg(hsotg->dev, "NP Tx FIFO Size=%d\n",
 512                 params->host_nperio_tx_fifo_size);
 513         dev_dbg(hsotg->dev, "P Tx FIFO Size=%d\n",
 514                 params->host_perio_tx_fifo_size);
 515
 516         /* Rx FIFO */
 517         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n",
 518                 readl(hsotg->regs + GRXFSIZ));
 519         writel(params->host_rx_fifo_size, hsotg->regs + GRXFSIZ);
 520         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ));
 521
 522         /* Non-periodic Tx FIFO */
 523         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 524                 readl(hsotg->regs + GNPTXFSIZ));
 525         nptxfsiz = params->host_nperio_tx_fifo_size <<
 526                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 527         nptxfsiz |= params->host_rx_fifo_size <<
 528                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 529         writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 530         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 531                 readl(hsotg->regs + GNPTXFSIZ));
 532
 533         /* Periodic Tx FIFO */
 534         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 535                 readl(hsotg->regs + HPTXFSIZ));
 536         ptxfsiz = params->host_perio_tx_fifo_size <<
 537                   FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 538         ptxfsiz |= (params->host_rx_fifo_size +
 539                     params->host_nperio_tx_fifo_size) <<
 540                    FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 541         writel(ptxfsiz, hsotg->regs + HPTXFSIZ);
 542         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 543                 readl(hsotg->regs + HPTXFSIZ));
 544
 545         if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
 546             hsotg->snpsid <= DWC2_CORE_REV_2_94a) {
 547                 /*
 548                  * Global DFIFOCFG calculation for Host mode -
 549                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 550                  */
 551                 dfifocfg = readl(hsotg->regs + GDFIFOCFG);
 552                 rxfsiz = readl(hsotg->regs + GRXFSIZ) & 0x0000ffff;
 553                 nptxfsiz = readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
 554                 hptxfsiz = readl(hsotg->regs + HPTXFSIZ) >> 16 & 0xffff;
 555                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 556                 dfifocfg |= (rxfsiz + nptxfsiz + hptxfsiz) <<
 557                             GDFIFOCFG_EPINFOBASE_SHIFT &
 558                             GDFIFOCFG_EPINFOBASE_MASK;
 559                 writel(dfifocfg, hsotg->regs + GDFIFOCFG);
 560         }
 561 }
 562
 563 /**
 564  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
 565  * Host mode
 566  *
 567  * @hsotg: Programming view of DWC_otg controller
 568  *
 569  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
 570  * request queues. Host channels are reset to ensure that they are ready for
 571  * performing transfers.
 572  */
 573 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
 574 {
 575         u32 hcfg, hfir, otgctl;
 576
 577         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 578
 579         /* Restart the Phy Clock */
 580         writel(0, hsotg->regs + PCGCTL);
 581
 582         /* Initialize Host Configuration Register */
 583         dwc2_init_fs_ls_pclk_sel(hsotg);
 584         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
 585                 hcfg = readl(hsotg->regs + HCFG);
 586                 hcfg |= HCFG_FSLSSUPP;
 587                 writel(hcfg, hsotg->regs + HCFG);
 588         }
 589
 590         /*
 591          * This bit allows dynamic reloading of the HFIR register during
 592          * runtime. This bit needs to be programmed during inital configuration
 593          * and its value must not be changed during runtime.
 594          */
 595         if (hsotg->core_params->reload_ctl > 0) {
 596                 hfir = readl(hsotg->regs + HFIR);
 597                 hfir |= HFIR_RLDCTRL;
 598                 writel(hfir, hsotg->regs + HFIR);
 599         }
 600
 601         if (hsotg->core_params->dma_desc_enable > 0) {
 602                 u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
 603
 604                 if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
 605                     !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
 606                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
 607                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
 608                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
 609                         dev_err(hsotg->dev,
 610                                 "Hardware does not support descriptor DMA mode -\n");
 611                         dev_err(hsotg->dev,
 612                                 "falling back to buffer DMA mode.\n");
 613                         hsotg->core_params->dma_desc_enable = 0;
 614                 } else {
 615                         hcfg = readl(hsotg->regs + HCFG);
 616                         hcfg |= HCFG_DESCDMA;
 617                         writel(hcfg, hsotg->regs + HCFG);
 618                 }
 619         }
 620
 621         /* Configure data FIFO sizes */
 622         dwc2_config_fifos(hsotg);
 623
 624         /* TODO - check this */
 625         /* Clear Host Set HNP Enable in the OTG Control Register */
 626         otgctl = readl(hsotg->regs + GOTGCTL);
 627         otgctl &= ~GOTGCTL_HSTSETHNPEN;
 628         writel(otgctl, hsotg->regs + GOTGCTL);
 629
 630         /* Make sure the FIFOs are flushed */
 631         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
 632         dwc2_flush_rx_fifo(hsotg);
 633
 634         /* Clear Host Set HNP Enable in the OTG Control Register */
 635         otgctl = readl(hsotg->regs + GOTGCTL);
 636         otgctl &= ~GOTGCTL_HSTSETHNPEN;
 637         writel(otgctl, hsotg->regs + GOTGCTL);
 638
 639         if (hsotg->core_params->dma_desc_enable <= 0) {
 640                 int num_channels, i;
 641                 u32 hcchar;
 642
 643                 /* Flush out any leftover queued requests */
 644                 num_channels = hsotg->core_params->host_channels;
 645                 for (i = 0; i < num_channels; i++) {
 646                         hcchar = readl(hsotg->regs + HCCHAR(i));
 647                         hcchar &= ~HCCHAR_CHENA;
 648                         hcchar |= HCCHAR_CHDIS;
 649                         hcchar &= ~HCCHAR_EPDIR;
 650                         writel(hcchar, hsotg->regs + HCCHAR(i));
 651                 }
 652
 653                 /* Halt all channels to put them into a known state */
 654                 for (i = 0; i < num_channels; i++) {
 655                         int count = 0;
 656
 657                         hcchar = readl(hsotg->regs + HCCHAR(i));
 658                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
 659                         hcchar &= ~HCCHAR_EPDIR;
 660                         writel(hcchar, hsotg->regs + HCCHAR(i));
 661                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
 662                                 __func__, i);
 663                         do {
 664                                 hcchar = readl(hsotg->regs + HCCHAR(i));
 665                                 if (++count > 1000) {
 666                                         dev_err(hsotg->dev,
 667                                                 "Unable to clear enable on channel %d\n",
 668                                                 i);
 669                                         break;
 670                                 }
 671                                 udelay(1);
 672                         } while (hcchar & HCCHAR_CHENA);
 673                 }
 674         }
 675
 676         /* Turn on the vbus power */
 677         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
 678         if (hsotg->op_state == OTG_STATE_A_HOST) {
 679                 u32 hprt0 = dwc2_read_hprt0(hsotg);
 680
 681                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
 682                         !!(hprt0 & HPRT0_PWR));
 683                 if (!(hprt0 & HPRT0_PWR)) {
 684                         hprt0 |= HPRT0_PWR;
 685                         writel(hprt0, hsotg->regs + HPRT0);
 686                 }
 687         }
 688
 689         dwc2_enable_host_interrupts(hsotg);
 690 }
 691
 692 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
 693                                       struct dwc2_host_chan *chan)
 694 {
 695         u32 hcintmsk = HCINTMSK_CHHLTD;
 696
 697         switch (chan->ep_type) {
 698         case USB_ENDPOINT_XFER_CONTROL:
 699         case USB_ENDPOINT_XFER_BULK:
 700                 dev_vdbg(hsotg->dev, "control/bulk\n");
 701                 hcintmsk |= HCINTMSK_XFERCOMPL;
 702                 hcintmsk |= HCINTMSK_STALL;
 703                 hcintmsk |= HCINTMSK_XACTERR;
 704                 hcintmsk |= HCINTMSK_DATATGLERR;
 705                 if (chan->ep_is_in) {
 706                         hcintmsk |= HCINTMSK_BBLERR;
 707                 } else {
 708                         hcintmsk |= HCINTMSK_NAK;
 709                         hcintmsk |= HCINTMSK_NYET;
 710                         if (chan->do_ping)
 711                                 hcintmsk |= HCINTMSK_ACK;
 712                 }
 713
 714                 if (chan->do_split) {
 715                         hcintmsk |= HCINTMSK_NAK;
 716                         if (chan->complete_split)
 717                                 hcintmsk |= HCINTMSK_NYET;
 718                         else
 719                                 hcintmsk |= HCINTMSK_ACK;
 720                 }
 721
 722                 if (chan->error_state)
 723                         hcintmsk |= HCINTMSK_ACK;
 724                 break;
 725
 726         case USB_ENDPOINT_XFER_INT:
 727                 if (dbg_perio())
 728                         dev_vdbg(hsotg->dev, "intr\n");
 729                 hcintmsk |= HCINTMSK_XFERCOMPL;
 730                 hcintmsk |= HCINTMSK_NAK;
 731                 hcintmsk |= HCINTMSK_STALL;
 732                 hcintmsk |= HCINTMSK_XACTERR;
 733                 hcintmsk |= HCINTMSK_DATATGLERR;
 734                 hcintmsk |= HCINTMSK_FRMOVRUN;
 735
 736                 if (chan->ep_is_in)
 737                         hcintmsk |= HCINTMSK_BBLERR;
 738                 if (chan->error_state)
 739                         hcintmsk |= HCINTMSK_ACK;
 740                 if (chan->do_split) {
 741                         if (chan->complete_split)
 742                                 hcintmsk |= HCINTMSK_NYET;
 743                         else
 744                                 hcintmsk |= HCINTMSK_ACK;
 745                 }
 746                 break;
 747
 748         case USB_ENDPOINT_XFER_ISOC:
 749                 if (dbg_perio())
 750                         dev_vdbg(hsotg->dev, "isoc\n");
 751                 hcintmsk |= HCINTMSK_XFERCOMPL;
 752                 hcintmsk |= HCINTMSK_FRMOVRUN;
 753                 hcintmsk |= HCINTMSK_ACK;
 754
 755                 if (chan->ep_is_in) {
 756                         hcintmsk |= HCINTMSK_XACTERR;
 757                         hcintmsk |= HCINTMSK_BBLERR;
 758                 }
 759                 break;
 760         default:
 761                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
 762                 break;
 763         }
 764
 765         writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 766         if (dbg_hc(chan))
 767                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 768 }
 769
 770 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
 771                                     struct dwc2_host_chan *chan)
 772 {
 773         u32 hcintmsk = HCINTMSK_CHHLTD;
 774
 775         /*
 776          * For Descriptor DMA mode core halts the channel on AHB error.
 777          * Interrupt is not required.
 778          */
 779         if (hsotg->core_params->dma_desc_enable <= 0) {
 780                 if (dbg_hc(chan))
 781                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 782                 hcintmsk |= HCINTMSK_AHBERR;
 783         } else {
 784                 if (dbg_hc(chan))
 785                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
 786                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 787                         hcintmsk |= HCINTMSK_XFERCOMPL;
 788         }
 789
 790         if (chan->error_state && !chan->do_split &&
 791             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
 792                 if (dbg_hc(chan))
 793                         dev_vdbg(hsotg->dev, "setting ACK\n");
 794                 hcintmsk |= HCINTMSK_ACK;
 795                 if (chan->ep_is_in) {
 796                         hcintmsk |= HCINTMSK_DATATGLERR;
 797                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
 798                                 hcintmsk |= HCINTMSK_NAK;
 799                 }
 800         }
 801
 802         writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 803         if (dbg_hc(chan))
 804                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 805 }
 806
 807 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
 808                                 struct dwc2_host_chan *chan)
 809 {
 810         u32 intmsk;
 811
 812         if (hsotg->core_params->dma_enable > 0) {
 813                 if (dbg_hc(chan))
 814                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 815                 dwc2_hc_enable_dma_ints(hsotg, chan);
 816         } else {
 817                 if (dbg_hc(chan))
 818                         dev_vdbg(hsotg->dev, "DMA disabled\n");
 819                 dwc2_hc_enable_slave_ints(hsotg, chan);
 820         }
 821
 822         /* Enable the top level host channel interrupt */
 823         intmsk = readl(hsotg->regs + HAINTMSK);
 824         intmsk |= 1 << chan->hc_num;
 825         writel(intmsk, hsotg->regs + HAINTMSK);
 826         if (dbg_hc(chan))
 827                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 828
 829         /* Make sure host channel interrupts are enabled */
 830         intmsk = readl(hsotg->regs + GINTMSK);
 831         intmsk |= GINTSTS_HCHINT;
 832         writel(intmsk, hsotg->regs + GINTMSK);
 833         if (dbg_hc(chan))
 834                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 835 }
 836
 837 /**
 838  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
 839  * a specific endpoint
 840  *
 841  * @hsotg: Programming view of DWC_otg controller
 842  * @chan:  Information needed to initialize the host channel
 843  *
 844  * The HCCHARn register is set up with the characteristics specified in chan.
 845  * Host channel interrupts that may need to be serviced while this transfer is
 846  * in progress are enabled.
 847  */
 848 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 849 {
 850         u8 hc_num = chan->hc_num;
 851         u32 hcintmsk;
 852         u32 hcchar;
 853         u32 hcsplt = 0;
 854
 855         if (dbg_hc(chan))
 856                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 857
 858         /* Clear old interrupt conditions for this host channel */
 859         hcintmsk = 0xffffffff;
 860         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 861         writel(hcintmsk, hsotg->regs + HCINT(hc_num));
 862
 863         /* Enable channel interrupts required for this transfer */
 864         dwc2_hc_enable_ints(hsotg, chan);
 865
 866         /*
 867          * Program the HCCHARn register with the endpoint characteristics for
 868          * the current transfer
 869          */
 870         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
 871         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
 872         if (chan->ep_is_in)
 873                 hcchar |= HCCHAR_EPDIR;
 874         if (chan->speed == USB_SPEED_LOW)
 875                 hcchar |= HCCHAR_LSPDDEV;
 876         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 877         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 878         writel(hcchar, hsotg->regs + HCCHAR(hc_num));
 879         if (dbg_hc(chan)) {
 880                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 881                          hc_num, hcchar);
 882
 883                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, hc_num);
 884                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
 885                          hcchar >> HCCHAR_DEVADDR_SHIFT &
 886                          HCCHAR_DEVADDR_MASK >> HCCHAR_DEVADDR_SHIFT);
 887                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
 888                          hcchar >> HCCHAR_EPNUM_SHIFT &
 889                          HCCHAR_EPNUM_MASK >> HCCHAR_EPNUM_SHIFT);
 890                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
 891                          !!(hcchar & HCCHAR_EPDIR));
 892                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
 893                          !!(hcchar & HCCHAR_LSPDDEV));
 894                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
 895                          hcchar >> HCCHAR_EPTYPE_SHIFT &
 896                          HCCHAR_EPTYPE_MASK >> HCCHAR_EPTYPE_SHIFT);
 897                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
 898                          hcchar >> HCCHAR_MPS_SHIFT &
 899                          HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
 900                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
 901                          hcchar >> HCCHAR_MULTICNT_SHIFT &
 902                          HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
 903         }
 904
 905         /* Program the HCSPLT register for SPLITs */
 906         if (chan->do_split) {
 907                 if (dbg_hc(chan))
 908                         dev_vdbg(hsotg->dev,
 909                                  "Programming HC %d with split --> %s\n",
 910                                  hc_num,
 911                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
 912                 if (chan->complete_split)
 913                         hcsplt |= HCSPLT_COMPSPLT;
 914                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
 915                           HCSPLT_XACTPOS_MASK;
 916                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
 917                           HCSPLT_HUBADDR_MASK;
 918                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
 919                           HCSPLT_PRTADDR_MASK;
 920                 if (dbg_hc(chan)) {
 921                         dev_vdbg(hsotg->dev, "    comp split %d\n",
 922                                  chan->complete_split);
 923                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
 924                                  chan->xact_pos);
 925                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
 926                                  chan->hub_addr);
 927                         dev_vdbg(hsotg->dev, "    hub port %d\n",
 928                                  chan->hub_port);
 929                         dev_vdbg(hsotg->dev, "    is_in %d\n",
 930                                  chan->ep_is_in);
 931                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
 932                                  hcchar >> HCCHAR_MPS_SHIFT &
 933                                  HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
 934                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
 935                                  chan->xfer_len);
 936                 }
 937         }
 938
 939         writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
 940 }
 941
 942 /**
 943  * dwc2_hc_halt() - Attempts to halt a host channel
 944  *
 945  * @hsotg:       Controller register interface
 946  * @chan:        Host channel to halt
 947  * @halt_status: Reason for halting the channel
 948  *
 949  * This function should only be called in Slave mode or to abort a transfer in
 950  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
 951  * controller halts the channel when the transfer is complete or a condition
 952  * occurs that requires application intervention.
 953  *
 954  * In slave mode, checks for a free request queue entry, then sets the Channel
 955  * Enable and Channel Disable bits of the Host Channel Characteristics
 956  * register of the specified channel to intiate the halt. If there is no free
 957  * request queue entry, sets only the Channel Disable bit of the HCCHARn
 958  * register to flush requests for this channel. In the latter case, sets a
 959  * flag to indicate that the host channel needs to be halted when a request
 960  * queue slot is open.
 961  *
 962  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
 963  * HCCHARn register. The controller ensures there is space in the request
 964  * queue before submitting the halt request.
 965  *
 966  * Some time may elapse before the core flushes any posted requests for this
 967  * host channel and halts. The Channel Halted interrupt handler completes the
 968  * deactivation of the host channel.
 969  */
 970 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 971                   enum dwc2_halt_status halt_status)
 972 {
 973         u32 nptxsts, hptxsts, hcchar;
 974
 975         if (dbg_hc(chan))
 976                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 977         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
 978                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
 979
 980         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
 981             halt_status == DWC2_HC_XFER_AHB_ERR) {
 982                 /*
 983                  * Disable all channel interrupts except Ch Halted. The QTD
 984                  * and QH state associated with this transfer has been cleared
 985                  * (in the case of URB_DEQUEUE), so the channel needs to be
 986                  * shut down carefully to prevent crashes.
 987                  */
 988                 u32 hcintmsk = HCINTMSK_CHHLTD;
 989
 990                 dev_vdbg(hsotg->dev, "dequeue/error\n");
 991                 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
 992
 993                 /*
 994                  * Make sure no other interrupts besides halt are currently
 995                  * pending. Handling another interrupt could cause a crash due
 996                  * to the QTD and QH state.
 997                  */
 998                 writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
 999
1000                 /*
1001                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1002                  * even if the channel was already halted for some other
1003                  * reason
1004                  */
1005                 chan->halt_status = halt_status;
1006
1007                 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1008                 if (!(hcchar & HCCHAR_CHENA)) {
1009                         /*
1010                          * The channel is either already halted or it hasn't
1011                          * started yet. In DMA mode, the transfer may halt if
1012                          * it finishes normally or a condition occurs that
1013                          * requires driver intervention. Don't want to halt
1014                          * the channel again. In either Slave or DMA mode,
1015                          * it's possible that the transfer has been assigned
1016                          * to a channel, but not started yet when an URB is
1017                          * dequeued. Don't want to halt a channel that hasn't
1018                          * started yet.
1019                          */
1020                         return;
1021                 }
1022         }
1023         if (chan->halt_pending) {
1024                 /*
1025                  * A halt has already been issued for this channel. This might
1026                  * happen when a transfer is aborted by a higher level in
1027                  * the stack.
1028                  */
1029                 dev_vdbg(hsotg->dev,
1030                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1031                          __func__, chan->hc_num);
1032                 return;
1033         }
1034
1035         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1036
1037         /* No need to set the bit in DDMA for disabling the channel */
1038         /* TODO check it everywhere channel is disabled */
1039         if (hsotg->core_params->dma_desc_enable <= 0) {
1040                 if (dbg_hc(chan))
1041                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1042                 hcchar |= HCCHAR_CHENA;
1043         } else {
1044                 if (dbg_hc(chan))
1045                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1046         }
1047         hcchar |= HCCHAR_CHDIS;
1048
1049         if (hsotg->core_params->dma_enable <= 0) {
1050                 if (dbg_hc(chan))
1051                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1052                 hcchar |= HCCHAR_CHENA;
1053
1054                 /* Check for space in the request queue to issue the halt */
1055                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1056                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1057                         dev_vdbg(hsotg->dev, "control/bulk\n");
1058                         nptxsts = readl(hsotg->regs + GNPTXSTS);
1059                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1060                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1061                                 hcchar &= ~HCCHAR_CHENA;
1062                         }
1063                 } else {
1064                         if (dbg_perio())
1065                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1066                         hptxsts = readl(hsotg->regs + HPTXSTS);
1067                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1068                             hsotg->queuing_high_bandwidth) {
1069                                 if (dbg_perio())
1070                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1071                                 hcchar &= ~HCCHAR_CHENA;
1072                         }
1073                 }
1074         } else {
1075                 if (dbg_hc(chan))
1076                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1077         }
1078
1079         writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1080         chan->halt_status = halt_status;
1081
1082         if (hcchar & HCCHAR_CHENA) {
1083                 if (dbg_hc(chan))
1084                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1085                 chan->halt_pending = 1;
1086                 chan->halt_on_queue = 0;
1087         } else {
1088                 if (dbg_hc(chan))
1089                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1090                 chan->halt_on_queue = 1;
1091         }
1092
1093         if (dbg_hc(chan)) {
1094                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1095                          chan->hc_num);
1096                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1097                          hcchar);
1098                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1099                          chan->halt_pending);
1100                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1101                          chan->halt_on_queue);
1102                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1103                          chan->halt_status);
1104         }
1105 }
1106
1107 /**
1108  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1109  *
1110  * @hsotg: Programming view of DWC_otg controller
1111  * @chan:  Identifies the host channel to clean up
1112  *
1113  * This function is normally called after a transfer is done and the host
1114  * channel is being released
1115  */
1116 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1117 {
1118         u32 hcintmsk;
1119
1120         chan->xfer_started = 0;
1121
1122         /*
1123          * Clear channel interrupt enables and any unhandled channel interrupt
1124          * conditions
1125          */
1126         writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1127         hcintmsk = 0xffffffff;
1128         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1129         writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1130 }
1131
1132 /**
1133  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1134  * which frame a periodic transfer should occur
1135  *
1136  * @hsotg:  Programming view of DWC_otg controller
1137  * @chan:   Identifies the host channel to set up and its properties
1138  * @hcchar: Current value of the HCCHAR register for the specified host channel
1139  *
1140  * This function has no effect on non-periodic transfers
1141  */
1142 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1143                                        struct dwc2_host_chan *chan, u32 *hcchar)
1144 {
1145         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1146             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1147                 /* 1 if _next_ frame is odd, 0 if it's even */
1148                 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1149                         *hcchar |= HCCHAR_ODDFRM;
1150         }
1151 }
1152
1153 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1154 {
1155         /* Set up the initial PID for the transfer */
1156         if (chan->speed == USB_SPEED_HIGH) {
1157                 if (chan->ep_is_in) {
1158                         if (chan->multi_count == 1)
1159                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1160                         else if (chan->multi_count == 2)
1161                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1162                         else
1163                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1164                 } else {
1165                         if (chan->multi_count == 1)
1166                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1167                         else
1168                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1169                 }
1170         } else {
1171                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1172         }
1173 }
1174
1175 /**
1176  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1177  * the Host Channel
1178  *
1179  * @hsotg: Programming view of DWC_otg controller
1180  * @chan:  Information needed to initialize the host channel
1181  *
1182  * This function should only be called in Slave mode. For a channel associated
1183  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1184  * associated with a periodic EP, the periodic Tx FIFO is written.
1185  *
1186  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1187  * the number of bytes written to the Tx FIFO.
1188  */
1189 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1190                                  struct dwc2_host_chan *chan)
1191 {
1192         u32 i;
1193         u32 remaining_count;
1194         u32 byte_count;
1195         u32 dword_count;
1196         u32 __iomem *data_fifo;
1197         u32 *data_buf = (u32 *)chan->xfer_buf;
1198
1199         if (dbg_hc(chan))
1200                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1201
1202         data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1203
1204         remaining_count = chan->xfer_len - chan->xfer_count;
1205         if (remaining_count > chan->max_packet)
1206                 byte_count = chan->max_packet;
1207         else
1208                 byte_count = remaining_count;
1209
1210         dword_count = (byte_count + 3) / 4;
1211
1212         if (((unsigned long)data_buf & 0x3) == 0) {
1213                 /* xfer_buf is DWORD aligned */
1214                 for (i = 0; i < dword_count; i++, data_buf++)
1215                         writel(*data_buf, data_fifo);
1216         } else {
1217                 /* xfer_buf is not DWORD aligned */
1218                 for (i = 0; i < dword_count; i++, data_buf++) {
1219                         u32 data = data_buf[0] | data_buf[1] << 8 |
1220                                    data_buf[2] << 16 | data_buf[3] << 24;
1221                         writel(data, data_fifo);
1222                 }
1223         }
1224
1225         chan->xfer_count += byte_count;
1226         chan->xfer_buf += byte_count;
1227 }
1228
1229 /**
1230  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1231  * channel and starts the transfer
1232  *
1233  * @hsotg: Programming view of DWC_otg controller
1234  * @chan:  Information needed to initialize the host channel. The xfer_len value
1235  *         may be reduced to accommodate the max widths of the XferSize and
1236  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1237  *         changed to reflect the final xfer_len value.
1238  *
1239  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1240  * the caller must ensure that there is sufficient space in the request queue
1241  * and Tx Data FIFO.
1242  *
1243  * For an OUT transfer in Slave mode, it loads a data packet into the
1244  * appropriate FIFO. If necessary, additional data packets are loaded in the
1245  * Host ISR.
1246  *
1247  * For an IN transfer in Slave mode, a data packet is requested. The data
1248  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1249  * additional data packets are requested in the Host ISR.
1250  *
1251  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1252  * register along with a packet count of 1 and the channel is enabled. This
1253  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1254  * simply set to 0 since no data transfer occurs in this case.
1255  *
1256  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1257  * all the information required to perform the subsequent data transfer. In
1258  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1259  * controller performs the entire PING protocol, then starts the data
1260  * transfer.
1261  */
1262 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1263                             struct dwc2_host_chan *chan)
1264 {
1265         u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1266         u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1267         u32 hcchar;
1268         u32 hctsiz = 0;
1269         u16 num_packets;
1270
1271         if (dbg_hc(chan))
1272                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1273
1274         if (chan->do_ping) {
1275                 if (hsotg->core_params->dma_enable <= 0) {
1276                         if (dbg_hc(chan))
1277                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1278                         dwc2_hc_do_ping(hsotg, chan);
1279                         chan->xfer_started = 1;
1280                         return;
1281                 } else {
1282                         if (dbg_hc(chan))
1283                                 dev_vdbg(hsotg->dev, "ping, DMA\n");
1284                         hctsiz |= TSIZ_DOPNG;
1285                 }
1286         }
1287
1288         if (chan->do_split) {
1289                 if (dbg_hc(chan))
1290                         dev_vdbg(hsotg->dev, "split\n");
1291                 num_packets = 1;
1292
1293                 if (chan->complete_split && !chan->ep_is_in)
1294                         /*
1295                          * For CSPLIT OUT Transfer, set the size to 0 so the
1296                          * core doesn't expect any data written to the FIFO
1297                          */
1298                         chan->xfer_len = 0;
1299                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1300                         chan->xfer_len = chan->max_packet;
1301                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1302                         chan->xfer_len = 188;
1303
1304                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1305                           TSIZ_XFERSIZE_MASK;
1306         } else {
1307                 if (dbg_hc(chan))
1308                         dev_vdbg(hsotg->dev, "no split\n");
1309                 /*
1310                  * Ensure that the transfer length and packet count will fit
1311                  * in the widths allocated for them in the HCTSIZn register
1312                  */
1313                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1314                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1315                         /*
1316                          * Make sure the transfer size is no larger than one
1317                          * (micro)frame's worth of data. (A check was done
1318                          * when the periodic transfer was accepted to ensure
1319                          * that a (micro)frame's worth of data can be
1320                          * programmed into a channel.)
1321                          */
1322                         u32 max_periodic_len =
1323                                 chan->multi_count * chan->max_packet;
1324
1325                         if (chan->xfer_len > max_periodic_len)
1326                                 chan->xfer_len = max_periodic_len;
1327                 } else if (chan->xfer_len > max_hc_xfer_size) {
1328                         /*
1329                          * Make sure that xfer_len is a multiple of max packet
1330                          * size
1331                          */
1332                         chan->xfer_len =
1333                                 max_hc_xfer_size - chan->max_packet + 1;
1334                 }
1335
1336                 if (chan->xfer_len > 0) {
1337                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1338                                         chan->max_packet;
1339                         if (num_packets > max_hc_pkt_count) {
1340                                 num_packets = max_hc_pkt_count;
1341                                 chan->xfer_len = num_packets * chan->max_packet;
1342                         }
1343                 } else {
1344                         /* Need 1 packet for transfer length of 0 */
1345                         num_packets = 1;
1346                 }
1347
1348                 if (chan->ep_is_in)
1349                         /*
1350                          * Always program an integral # of max packets for IN
1351                          * transfers
1352                          */
1353                         chan->xfer_len = num_packets * chan->max_packet;
1354
1355                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1356                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1357                         /*
1358                          * Make sure that the multi_count field matches the
1359                          * actual transfer length
1360                          */
1361                         chan->multi_count = num_packets;
1362
1363                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1364                         dwc2_set_pid_isoc(chan);
1365
1366                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1367                           TSIZ_XFERSIZE_MASK;
1368         }
1369
1370         chan->start_pkt_count = num_packets;
1371         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1372         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1373                   TSIZ_SC_MC_PID_MASK;
1374         writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1375         if (dbg_hc(chan)) {
1376                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1377                          hctsiz, chan->hc_num);
1378
1379                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1380                          chan->hc_num);
1381                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1382                          hctsiz >> TSIZ_XFERSIZE_SHIFT &
1383                          TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
1384                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1385                          hctsiz >> TSIZ_PKTCNT_SHIFT &
1386                          TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
1387                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1388                          hctsiz >> TSIZ_SC_MC_PID_SHIFT &
1389                          TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);
1390         }
1391
1392         if (hsotg->core_params->dma_enable > 0) {
1393                 dma_addr_t dma_addr;
1394
1395                 if (chan->align_buf) {
1396                         if (dbg_hc(chan))
1397                                 dev_vdbg(hsotg->dev, "align_buf\n");
1398                         dma_addr = chan->align_buf;
1399                 } else {
1400                         dma_addr = chan->xfer_dma;
1401                 }
1402                 writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1403                 if (dbg_hc(chan))
1404                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1405                                  (unsigned long)dma_addr, chan->hc_num);
1406         }
1407
1408         /* Start the split */
1409         if (chan->do_split) {
1410                 u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
1411
1412                 hcsplt |= HCSPLT_SPLTENA;
1413                 writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1414         }
1415
1416         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1417         hcchar &= ~HCCHAR_MULTICNT_MASK;
1418         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1419                   HCCHAR_MULTICNT_MASK;
1420         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1421
1422         if (hcchar & HCCHAR_CHDIS)
1423                 dev_warn(hsotg->dev,
1424                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1425                          __func__, chan->hc_num, hcchar);
1426
1427         /* Set host channel enable after all other setup is complete */
1428         hcchar |= HCCHAR_CHENA;
1429         hcchar &= ~HCCHAR_CHDIS;
1430
1431         if (dbg_hc(chan))
1432                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1433                          hcchar >> HCCHAR_MULTICNT_SHIFT &
1434                          HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
1435
1436         writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1437         if (dbg_hc(chan))
1438                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1439                          chan->hc_num);
1440
1441         chan->xfer_started = 1;
1442         chan->requests++;
1443
1444         if (hsotg->core_params->dma_enable <= 0 &&
1445             !chan->ep_is_in && chan->xfer_len > 0)
1446                 /* Load OUT packet into the appropriate Tx FIFO */
1447                 dwc2_hc_write_packet(hsotg, chan);
1448 }
1449
1450 /**
1451  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1452  * host channel and starts the transfer in Descriptor DMA mode
1453  *
1454  * @hsotg: Programming view of DWC_otg controller
1455  * @chan:  Information needed to initialize the host channel
1456  *
1457  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1458  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1459  * with micro-frame bitmap.
1460  *
1461  * Initializes HCDMA register with descriptor list address and CTD value then
1462  * starts the transfer via enabling the channel.
1463  */
1464 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1465                                  struct dwc2_host_chan *chan)
1466 {
1467         u32 hcchar;
1468         u32 hc_dma;
1469         u32 hctsiz = 0;
1470
1471         if (chan->do_ping)
1472                 hctsiz |= TSIZ_DOPNG;
1473
1474         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1475                 dwc2_set_pid_isoc(chan);
1476
1477         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1478         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1479                   TSIZ_SC_MC_PID_MASK;
1480
1481         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1482         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1483
1484         /* Non-zero only for high-speed interrupt endpoints */
1485         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1486
1487         if (dbg_hc(chan)) {
1488                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1489                          chan->hc_num);
1490                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1491                          chan->data_pid_start);
1492                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1493         }
1494
1495         writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1496
1497         hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1498
1499         /* Always start from first descriptor */
1500         hc_dma &= ~HCDMA_CTD_MASK;
1501         writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1502         if (dbg_hc(chan))
1503                 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1504                          hc_dma, chan->hc_num);
1505
1506         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1507         hcchar &= ~HCCHAR_MULTICNT_MASK;
1508         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1509                   HCCHAR_MULTICNT_MASK;
1510
1511         if (hcchar & HCCHAR_CHDIS)
1512                 dev_warn(hsotg->dev,
1513                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1514                          __func__, chan->hc_num, hcchar);
1515
1516         /* Set host channel enable after all other setup is complete */
1517         hcchar |= HCCHAR_CHENA;
1518         hcchar &= ~HCCHAR_CHDIS;
1519
1520         if (dbg_hc(chan))
1521                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1522                          hcchar >> HCCHAR_MULTICNT_SHIFT &
1523                          HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
1524
1525         writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1526         if (dbg_hc(chan))
1527                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1528                          chan->hc_num);
1529
1530         chan->xfer_started = 1;
1531         chan->requests++;
1532 }
1533
1534 /**
1535  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1536  * a previous call to dwc2_hc_start_transfer()
1537  *
1538  * @hsotg: Programming view of DWC_otg controller
1539  * @chan:  Information needed to initialize the host channel
1540  *
1541  * The caller must ensure there is sufficient space in the request queue and Tx
1542  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1543  * the controller acts autonomously to complete transfers programmed to a host
1544  * channel.
1545  *
1546  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1547  * if there is any data remaining to be queued. For an IN transfer, another
1548  * data packet is always requested. For the SETUP phase of a control transfer,
1549  * this function does nothing.
1550  *
1551  * Return: 1 if a new request is queued, 0 if no more requests are required
1552  * for this transfer
1553  */
1554 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1555                               struct dwc2_host_chan *chan)
1556 {
1557         if (dbg_hc(chan))
1558                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1559                          chan->hc_num);
1560
1561         if (chan->do_split)
1562                 /* SPLITs always queue just once per channel */
1563                 return 0;
1564
1565         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1566                 /* SETUPs are queued only once since they can't be NAK'd */
1567                 return 0;
1568
1569         if (chan->ep_is_in) {
1570                 /*
1571                  * Always queue another request for other IN transfers. If
1572                  * back-to-back INs are issued and NAKs are received for both,
1573                  * the driver may still be processing the first NAK when the
1574                  * second NAK is received. When the interrupt handler clears
1575                  * the NAK interrupt for the first NAK, the second NAK will
1576                  * not be seen. So we can't depend on the NAK interrupt
1577                  * handler to requeue a NAK'd request. Instead, IN requests
1578                  * are issued each time this function is called. When the
1579                  * transfer completes, the extra requests for the channel will
1580                  * be flushed.
1581                  */
1582                 u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1583
1584                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1585                 hcchar |= HCCHAR_CHENA;
1586                 hcchar &= ~HCCHAR_CHDIS;
1587                 if (dbg_hc(chan))
1588                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
1589                                  hcchar);
1590                 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1591                 chan->requests++;
1592                 return 1;
1593         }
1594
1595         /* OUT transfers */
1596
1597         if (chan->xfer_count < chan->xfer_len) {
1598                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1599                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1600                         u32 hcchar = readl(hsotg->regs +
1601                                            HCCHAR(chan->hc_num));
1602
1603                         dwc2_hc_set_even_odd_frame(hsotg, chan,
1604                                                    &hcchar);
1605                 }
1606
1607                 /* Load OUT packet into the appropriate Tx FIFO */
1608                 dwc2_hc_write_packet(hsotg, chan);
1609                 chan->requests++;
1610                 return 1;
1611         }
1612
1613         return 0;
1614 }
1615
1616 /**
1617  * dwc2_hc_do_ping() - Starts a PING transfer
1618  *
1619  * @hsotg: Programming view of DWC_otg controller
1620  * @chan:  Information needed to initialize the host channel
1621  *
1622  * This function should only be called in Slave mode. The Do Ping bit is set in
1623  * the HCTSIZ register, then the channel is enabled.
1624  */
1625 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1626 {
1627         u32 hcchar;
1628         u32 hctsiz;
1629
1630         if (dbg_hc(chan))
1631                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1632                          chan->hc_num);
1633
1634
1635         hctsiz = TSIZ_DOPNG;
1636         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1637         writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1638
1639         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1640         hcchar |= HCCHAR_CHENA;
1641         hcchar &= ~HCCHAR_CHDIS;
1642         writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1643 }
1644
1645 /**
1646  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
1647  * the HFIR register according to PHY type and speed
1648  *
1649  * @hsotg: Programming view of DWC_otg controller
1650  *
1651  * NOTE: The caller can modify the value of the HFIR register only after the
1652  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
1653  * has been set
1654  */
1655 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
1656 {
1657         u32 usbcfg;
1658         u32 hwcfg2;
1659         u32 hprt0;
1660         int clock = 60; /* default value */
1661
1662         usbcfg = readl(hsotg->regs + GUSBCFG);
1663         hwcfg2 = readl(hsotg->regs + GHWCFG2);
1664         hprt0 = readl(hsotg->regs + HPRT0);
1665
1666         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
1667             !(usbcfg & GUSBCFG_PHYIF16))
1668                 clock = 60;
1669         if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1670             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
1671                 clock = 48;
1672         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1673             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1674                 clock = 30;
1675         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1676             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
1677                 clock = 60;
1678         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1679             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1680                 clock = 48;
1681         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
1682             (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1683             GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
1684                 clock = 48;
1685         if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1686             GHWCFG2_FS_PHY_TYPE_DEDICATED)
1687                 clock = 48;
1688
1689         if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)
1690                 /* High speed case */
1691                 return 125 * clock;
1692         else
1693                 /* FS/LS case */
1694                 return 1000 * clock;
1695 }
1696
1697 /**
1698  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
1699  * buffer
1700  *
1701  * @core_if: Programming view of DWC_otg controller
1702  * @dest:    Destination buffer for the packet
1703  * @bytes:   Number of bytes to copy to the destination
1704  */
1705 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
1706 {
1707         u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
1708         u32 *data_buf = (u32 *)dest;
1709         int word_count = (bytes + 3) / 4;
1710         int i;
1711
1712         /*
1713          * Todo: Account for the case where dest is not dword aligned. This
1714          * requires reading data from the FIFO into a u32 temp buffer, then
1715          * moving it into the data buffer.
1716          */
1717
1718         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
1719
1720         for (i = 0; i < word_count; i++, data_buf++)
1721                 *data_buf = readl(fifo);
1722 }
1723
1724 /**
1725  * dwc2_dump_host_registers() - Prints the host registers
1726  *
1727  * @hsotg: Programming view of DWC_otg controller
1728  *
1729  * NOTE: This function will be removed once the peripheral controller code
1730  * is integrated and the driver is stable
1731  */
1732 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
1733 {
1734 #ifdef DEBUG
1735         u32 __iomem *addr;
1736         int i;
1737
1738         dev_dbg(hsotg->dev, "Host Global Registers\n");
1739         addr = hsotg->regs + HCFG;
1740         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
1741                 (unsigned long)addr, readl(addr));
1742         addr = hsotg->regs + HFIR;
1743         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
1744                 (unsigned long)addr, readl(addr));
1745         addr = hsotg->regs + HFNUM;
1746         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
1747                 (unsigned long)addr, readl(addr));
1748         addr = hsotg->regs + HPTXSTS;
1749         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
1750                 (unsigned long)addr, readl(addr));
1751         addr = hsotg->regs + HAINT;
1752         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
1753                 (unsigned long)addr, readl(addr));
1754         addr = hsotg->regs + HAINTMSK;
1755         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
1756                 (unsigned long)addr, readl(addr));
1757         if (hsotg->core_params->dma_desc_enable > 0) {
1758                 addr = hsotg->regs + HFLBADDR;
1759                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
1760                         (unsigned long)addr, readl(addr));
1761         }
1762
1763         addr = hsotg->regs + HPRT0;
1764         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
1765                 (unsigned long)addr, readl(addr));
1766
1767         for (i = 0; i < hsotg->core_params->host_channels; i++) {
1768                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
1769                 addr = hsotg->regs + HCCHAR(i);
1770                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
1771                         (unsigned long)addr, readl(addr));
1772                 addr = hsotg->regs + HCSPLT(i);
1773                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
1774                         (unsigned long)addr, readl(addr));
1775                 addr = hsotg->regs + HCINT(i);
1776                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
1777                         (unsigned long)addr, readl(addr));
1778                 addr = hsotg->regs + HCINTMSK(i);
1779                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
1780                         (unsigned long)addr, readl(addr));
1781                 addr = hsotg->regs + HCTSIZ(i);
1782                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
1783                         (unsigned long)addr, readl(addr));
1784                 addr = hsotg->regs + HCDMA(i);
1785                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
1786                         (unsigned long)addr, readl(addr));
1787                 if (hsotg->core_params->dma_desc_enable > 0) {
1788                         addr = hsotg->regs + HCDMAB(i);
1789                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
1790                                 (unsigned long)addr, readl(addr));
1791                 }
1792         }
1793 #endif
1794 }
1795
1796 /**
1797  * dwc2_dump_global_registers() - Prints the core global registers
1798  *
1799  * @hsotg: Programming view of DWC_otg controller
1800  *
1801  * NOTE: This function will be removed once the peripheral controller code
1802  * is integrated and the driver is stable
1803  */
1804 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
1805 {
1806 #ifdef DEBUG
1807         u32 __iomem *addr;
1808
1809         dev_dbg(hsotg->dev, "Core Global Registers\n");
1810         addr = hsotg->regs + GOTGCTL;
1811         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
1812                 (unsigned long)addr, readl(addr));
1813         addr = hsotg->regs + GOTGINT;
1814         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
1815                 (unsigned long)addr, readl(addr));
1816         addr = hsotg->regs + GAHBCFG;
1817         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
1818                 (unsigned long)addr, readl(addr));
1819         addr = hsotg->regs + GUSBCFG;
1820         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
1821                 (unsigned long)addr, readl(addr));
1822         addr = hsotg->regs + GRSTCTL;
1823         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
1824                 (unsigned long)addr, readl(addr));
1825         addr = hsotg->regs + GINTSTS;
1826         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
1827                 (unsigned long)addr, readl(addr));
1828         addr = hsotg->regs + GINTMSK;
1829         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
1830                 (unsigned long)addr, readl(addr));
1831         addr = hsotg->regs + GRXSTSR;
1832         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
1833                 (unsigned long)addr, readl(addr));
1834         addr = hsotg->regs + GRXFSIZ;
1835         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
1836                 (unsigned long)addr, readl(addr));
1837         addr = hsotg->regs + GNPTXFSIZ;
1838         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
1839                 (unsigned long)addr, readl(addr));
1840         addr = hsotg->regs + GNPTXSTS;
1841         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
1842                 (unsigned long)addr, readl(addr));
1843         addr = hsotg->regs + GI2CCTL;
1844         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
1845                 (unsigned long)addr, readl(addr));
1846         addr = hsotg->regs + GPVNDCTL;
1847         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
1848                 (unsigned long)addr, readl(addr));
1849         addr = hsotg->regs + GGPIO;
1850         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
1851                 (unsigned long)addr, readl(addr));
1852         addr = hsotg->regs + GUID;
1853         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
1854                 (unsigned long)addr, readl(addr));
1855         addr = hsotg->regs + GSNPSID;
1856         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
1857                 (unsigned long)addr, readl(addr));
1858         addr = hsotg->regs + GHWCFG1;
1859         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
1860                 (unsigned long)addr, readl(addr));
1861         addr = hsotg->regs + GHWCFG2;
1862         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
1863                 (unsigned long)addr, readl(addr));
1864         addr = hsotg->regs + GHWCFG3;
1865         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
1866                 (unsigned long)addr, readl(addr));
1867         addr = hsotg->regs + GHWCFG4;
1868         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
1869                 (unsigned long)addr, readl(addr));
1870         addr = hsotg->regs + GLPMCFG;
1871         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
1872                 (unsigned long)addr, readl(addr));
1873         addr = hsotg->regs + GPWRDN;
1874         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
1875                 (unsigned long)addr, readl(addr));
1876         addr = hsotg->regs + GDFIFOCFG;
1877         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
1878                 (unsigned long)addr, readl(addr));
1879         addr = hsotg->regs + HPTXFSIZ;
1880         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
1881                 (unsigned long)addr, readl(addr));
1882
1883         addr = hsotg->regs + PCGCTL;
1884         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
1885                 (unsigned long)addr, readl(addr));
1886 #endif
1887 }
1888
1889 /**
1890  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
1891  *
1892  * @hsotg: Programming view of DWC_otg controller
1893  * @num:   Tx FIFO to flush
1894  */
1895 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
1896 {
1897         u32 greset;
1898         int count = 0;
1899
1900         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
1901
1902         greset = GRSTCTL_TXFFLSH;
1903         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
1904         writel(greset, hsotg->regs + GRSTCTL);
1905
1906         do {
1907                 greset = readl(hsotg->regs + GRSTCTL);
1908                 if (++count > 10000) {
1909                         dev_warn(hsotg->dev,
1910                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
1911                                  __func__, greset,
1912                                  readl(hsotg->regs + GNPTXSTS));
1913                         break;
1914                 }
1915                 udelay(1);
1916         } while (greset & GRSTCTL_TXFFLSH);
1917
1918         /* Wait for at least 3 PHY Clocks */
1919         udelay(1);
1920 }
1921
1922 /**
1923  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
1924  *
1925  * @hsotg: Programming view of DWC_otg controller
1926  */
1927 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
1928 {
1929         u32 greset;
1930         int count = 0;
1931
1932         dev_vdbg(hsotg->dev, "%s()\n", __func__);
1933
1934         greset = GRSTCTL_RXFFLSH;
1935         writel(greset, hsotg->regs + GRSTCTL);
1936
1937         do {
1938                 greset = readl(hsotg->regs + GRSTCTL);
1939                 if (++count > 10000) {
1940                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
1941                                  __func__, greset);
1942                         break;
1943                 }
1944                 udelay(1);
1945         } while (greset & GRSTCTL_RXFFLSH);
1946
1947         /* Wait for at least 3 PHY Clocks */
1948         udelay(1);
1949 }
1950
1951 #define DWC2_PARAM_TEST(a, b, c)        ((a) < (b) || (a) > (c))
1952
1953 /* Parameter access functions */
1954 int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
1955 {
1956         int valid = 1;
1957         int retval = 0;
1958         u32 op_mode;
1959
1960         op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
1961
1962         switch (val) {
1963         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
1964                 if (op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
1965                         valid = 0;
1966                 break;
1967         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
1968                 switch (op_mode) {
1969                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1970                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
1971                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
1972                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
1973                         break;
1974                 default:
1975                         valid = 0;
1976                         break;
1977                 }
1978                 break;
1979         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
1980                 /* always valid */
1981                 break;
1982         default:
1983                 valid = 0;
1984                 break;
1985         }
1986
1987         if (!valid) {
1988                 if (val >= 0)
1989                         dev_err(hsotg->dev,
1990                                 "%d invalid for otg_cap parameter. Check HW configuration.\n",
1991                                 val);
1992                 switch (op_mode) {
1993                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1994                         val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
1995                         break;
1996                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
1997                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
1998                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
1999                         val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2000                         break;
2001                 default:
2002                         val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2003                         break;
2004                 }
2005                 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2006                 retval = -EINVAL;
2007         }
2008
2009         hsotg->core_params->otg_cap = val;
2010         return retval;
2011 }
2012
2013 int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2014 {
2015         int valid = 1;
2016         int retval = 0;
2017
2018         if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==
2019             GHWCFG2_SLAVE_ONLY_ARCH)
2020                 valid = 0;
2021         if (val < 0)
2022                 valid = 0;
2023
2024         if (!valid) {
2025                 if (val >= 0)
2026                         dev_err(hsotg->dev,
2027                                 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2028                                 val);
2029                 val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=
2030                         GHWCFG2_SLAVE_ONLY_ARCH;
2031                 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2032                 retval = -EINVAL;
2033         }
2034
2035         hsotg->core_params->dma_enable = val;
2036         return retval;
2037 }
2038
2039 int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2040 {
2041         int valid = 1;
2042         int retval = 0;
2043
2044         if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2045                         !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA)))
2046                 valid = 0;
2047         if (val < 0)
2048                 valid = 0;
2049
2050         if (!valid) {
2051                 if (val >= 0)
2052                         dev_err(hsotg->dev,
2053                                 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2054                                 val);
2055                 val = (hsotg->core_params->dma_enable > 0 &&
2056                         (hsotg->hwcfg4 & GHWCFG4_DESC_DMA));
2057                 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2058                 retval = -EINVAL;
2059         }
2060
2061         hsotg->core_params->dma_desc_enable = val;
2062         return retval;
2063 }
2064
2065 int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2066                                                 int val)
2067 {
2068         int retval = 0;
2069
2070         if (DWC2_PARAM_TEST(val, 0, 1)) {
2071                 if (val >= 0) {
2072                         dev_err(hsotg->dev,
2073                                 "Wrong value for host_support_fs_low_power\n");
2074                         dev_err(hsotg->dev,
2075                                 "host_support_fs_low_power must be 0 or 1\n");
2076                 }
2077                 val = 0;
2078                 dev_dbg(hsotg->dev,
2079                         "Setting host_support_fs_low_power to %d\n", val);
2080                 retval = -EINVAL;
2081         }
2082
2083         hsotg->core_params->host_support_fs_ls_low_power = val;
2084         return retval;
2085 }
2086
2087 int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2088 {
2089         int valid = 1;
2090         int retval = 0;
2091
2092         if (val > 0 && !(hsotg->hwcfg2 & GHWCFG2_DYNAMIC_FIFO))
2093                 valid = 0;
2094         if (val < 0)
2095                 valid = 0;
2096
2097         if (!valid) {
2098                 if (val >= 0)
2099                         dev_err(hsotg->dev,
2100                                 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2101                                 val);
2102                 val = !!(hsotg->hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
2103                 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2104                 retval = -EINVAL;
2105         }
2106
2107         hsotg->core_params->enable_dynamic_fifo = val;
2108         return retval;
2109 }
2110
2111 int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2112 {
2113         int valid = 1;
2114         int retval = 0;
2115
2116         if (val < 16 || val > readl(hsotg->regs + GRXFSIZ))
2117                 valid = 0;
2118
2119         if (!valid) {
2120                 if (val >= 0)
2121                         dev_err(hsotg->dev,
2122                                 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2123                                 val);
2124                 val = readl(hsotg->regs + GRXFSIZ);
2125                 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2126                 retval = -EINVAL;
2127         }
2128
2129         hsotg->core_params->host_rx_fifo_size = val;
2130         return retval;
2131 }
2132
2133 int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2134 {
2135         int valid = 1;
2136         int retval = 0;
2137
2138         if (val < 16 || val > (readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff))
2139                 valid = 0;
2140
2141         if (!valid) {
2142                 if (val >= 0)
2143                         dev_err(hsotg->dev,
2144                                 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2145                                 val);
2146                 val = readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
2147                 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2148                         val);
2149                 retval = -EINVAL;
2150         }
2151
2152         hsotg->core_params->host_nperio_tx_fifo_size = val;
2153         return retval;
2154 }
2155
2156 int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2157 {
2158         int valid = 1;
2159         int retval = 0;
2160
2161         if (val < 16 || val > (hsotg->hptxfsiz >> 16))
2162                 valid = 0;
2163
2164         if (!valid) {
2165                 if (val >= 0)
2166                         dev_err(hsotg->dev,
2167                                 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2168                                 val);
2169                 val = hsotg->hptxfsiz >> 16;
2170                 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2171                         val);
2172                 retval = -EINVAL;
2173         }
2174
2175         hsotg->core_params->host_perio_tx_fifo_size = val;
2176         return retval;
2177 }
2178
2179 int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2180 {
2181         int valid = 1;
2182         int retval = 0;
2183         int width = hsotg->hwcfg3 >> GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT &
2184                     GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK >>
2185                                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
2186
2187         if (val < 2047 || val >= (1 << (width + 11)))
2188                 valid = 0;
2189
2190         if (!valid) {
2191                 if (val >= 0)
2192                         dev_err(hsotg->dev,
2193                                 "%d invalid for max_transfer_size. Check HW configuration.\n",
2194                                 val);
2195                 val = (1 << (width + 11)) - 1;
2196                 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2197                 retval = -EINVAL;
2198         }
2199
2200         hsotg->core_params->max_transfer_size = val;
2201         return retval;
2202 }
2203
2204 int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2205 {
2206         int valid = 1;
2207         int retval = 0;
2208         int width = hsotg->hwcfg3 >> GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT &
2209                     GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK >>
2210                                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
2211
2212         if (val < 15 || val > (1 << (width + 4)))
2213                 valid = 0;
2214
2215         if (!valid) {
2216                 if (val >= 0)
2217                         dev_err(hsotg->dev,
2218                                 "%d invalid for max_packet_count. Check HW configuration.\n",
2219                                 val);
2220                 val = (1 << (width + 4)) - 1;
2221                 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2222                 retval = -EINVAL;
2223         }
2224
2225         hsotg->core_params->max_packet_count = val;
2226         return retval;
2227 }
2228
2229 int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2230 {
2231         int valid = 1;
2232         int retval = 0;
2233         int num_chan = hsotg->hwcfg2 >> GHWCFG2_NUM_HOST_CHAN_SHIFT &
2234                 GHWCFG2_NUM_HOST_CHAN_MASK >> GHWCFG2_NUM_HOST_CHAN_SHIFT;
2235
2236         if (val < 1 || val > num_chan + 1)
2237                 valid = 0;
2238
2239         if (!valid) {
2240                 if (val >= 0)
2241                         dev_err(hsotg->dev,
2242                                 "%d invalid for host_channels. Check HW configuration.\n",
2243                                 val);
2244                 val = num_chan + 1;
2245                 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2246                 retval = -EINVAL;
2247         }
2248
2249         hsotg->core_params->host_channels = val;
2250         return retval;
2251 }
2252
2253 int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2254 {
2255 #ifndef NO_FS_PHY_HW_CHECKS
2256         int valid = 0;
2257         u32 hs_phy_type;
2258         u32 fs_phy_type;
2259 #endif
2260         int retval = 0;
2261
2262         if (DWC2_PARAM_TEST(val, DWC2_PHY_TYPE_PARAM_FS,
2263                             DWC2_PHY_TYPE_PARAM_ULPI)) {
2264                 if (val >= 0) {
2265                         dev_err(hsotg->dev, "Wrong value for phy_type\n");
2266                         dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2267                 }
2268
2269 #ifndef NO_FS_PHY_HW_CHECKS
2270                 valid = 0;
2271 #else
2272                 val = DWC2_PHY_TYPE_PARAM_FS;
2273                 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2274                 retval = -EINVAL;
2275 #endif
2276         }
2277
2278 #ifndef NO_FS_PHY_HW_CHECKS
2279         hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
2280         fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
2281
2282         if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2283             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2284              hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2285                 valid = 1;
2286         else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2287                  (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2288                   hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2289                 valid = 1;
2290         else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2291                  fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2292                 valid = 1;
2293
2294         if (!valid) {
2295                 if (val >= 0)
2296                         dev_err(hsotg->dev,
2297                                 "%d invalid for phy_type. Check HW configuration.\n",
2298                                 val);
2299                 val = DWC2_PHY_TYPE_PARAM_FS;
2300                 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2301                         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2302                             hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2303                                 val = DWC2_PHY_TYPE_PARAM_UTMI;
2304                         else
2305                                 val = DWC2_PHY_TYPE_PARAM_ULPI;
2306                 }
2307                 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2308                 retval = -EINVAL;
2309         }
2310 #endif
2311
2312         hsotg->core_params->phy_type = val;
2313         return retval;
2314 }
2315
2316 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2317 {
2318         return hsotg->core_params->phy_type;
2319 }
2320
2321 int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2322 {
2323         int valid = 1;
2324         int retval = 0;
2325
2326         if (DWC2_PARAM_TEST(val, 0, 1)) {
2327                 if (val >= 0) {
2328                         dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2329                         dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2330                 }
2331                 valid = 0;
2332         }
2333
2334         if (val == DWC2_SPEED_PARAM_HIGH &&
2335             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2336                 valid = 0;
2337
2338         if (!valid) {
2339                 if (val >= 0)
2340                         dev_err(hsotg->dev,
2341                                 "%d invalid for speed parameter. Check HW configuration.\n",
2342                                 val);
2343                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2344                                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2345                 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2346                 retval = -EINVAL;
2347         }
2348
2349         hsotg->core_params->speed = val;
2350         return retval;
2351 }
2352
2353 int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2354 {
2355         int valid = 1;
2356         int retval = 0;
2357
2358         if (DWC2_PARAM_TEST(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2359                             DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2360                 if (val >= 0) {
2361                         dev_err(hsotg->dev,
2362                                 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2363                         dev_err(hsotg->dev,
2364                                 "host_ls_low_power_phy_clk must be 0 or 1\n");
2365                 }
2366                 valid = 0;
2367         }
2368
2369         if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2370             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2371                 valid = 0;
2372
2373         if (!valid) {
2374                 if (val >= 0)
2375                         dev_err(hsotg->dev,
2376                                 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2377                                 val);
2378                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2379                         ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2380                         : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2381                 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2382                         val);
2383                 retval = -EINVAL;
2384         }
2385
2386         hsotg->core_params->host_ls_low_power_phy_clk = val;
2387         return retval;
2388 }
2389
2390 int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2391 {
2392         int retval = 0;
2393
2394         if (DWC2_PARAM_TEST(val, 0, 1)) {
2395                 if (val >= 0) {
2396                         dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2397                         dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2398                 }
2399                 val = 0;
2400                 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2401                 retval = -EINVAL;
2402         }
2403
2404         hsotg->core_params->phy_ulpi_ddr = val;
2405         return retval;
2406 }
2407
2408 int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2409 {
2410         int retval = 0;
2411
2412         if (DWC2_PARAM_TEST(val, 0, 1)) {
2413                 if (val >= 0) {
2414                         dev_err(hsotg->dev,
2415                                 "Wrong value for phy_ulpi_ext_vbus\n");
2416                         dev_err(hsotg->dev,
2417                                 "phy_ulpi_ext_vbus must be 0 or 1\n");
2418                 }
2419                 val = 0;
2420                 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2421                 retval = -EINVAL;
2422         }
2423
2424         hsotg->core_params->phy_ulpi_ext_vbus = val;
2425         return retval;
2426 }
2427
2428 int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2429 {
2430         int retval = 0;
2431
2432         if (DWC2_PARAM_TEST(val, 8, 8) && DWC2_PARAM_TEST(val, 16, 16)) {
2433                 if (val >= 0) {
2434                         dev_err(hsotg->dev, "Wrong value for phy_utmi_width\n");
2435                         dev_err(hsotg->dev, "phy_utmi_width must be 8 or 16\n");
2436                 }
2437                 val = 8;
2438                 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2439                 retval = -EINVAL;
2440         }
2441
2442         hsotg->core_params->phy_utmi_width = val;
2443         return retval;
2444 }
2445
2446 int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2447 {
2448         int retval = 0;
2449
2450         if (DWC2_PARAM_TEST(val, 0, 1)) {
2451                 if (val >= 0) {
2452                         dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2453                         dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2454                 }
2455                 val = 0;
2456                 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2457                 retval = -EINVAL;
2458         }
2459
2460         hsotg->core_params->ulpi_fs_ls = val;
2461         return retval;
2462 }
2463
2464 int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2465 {
2466         int retval = 0;
2467
2468         if (DWC2_PARAM_TEST(val, 0, 1)) {
2469                 if (val >= 0) {
2470                         dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2471                         dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2472                 }
2473                 val = 0;
2474                 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2475                 retval = -EINVAL;
2476         }
2477
2478         hsotg->core_params->ts_dline = val;
2479         return retval;
2480 }
2481
2482 int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2483 {
2484 #ifndef NO_FS_PHY_HW_CHECKS
2485         int valid = 1;
2486 #endif
2487         int retval = 0;
2488
2489         if (DWC2_PARAM_TEST(val, 0, 1)) {
2490                 if (val >= 0) {
2491                         dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2492                         dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2493                 }
2494
2495 #ifndef NO_FS_PHY_HW_CHECKS
2496                 valid = 0;
2497 #else
2498                 val = 0;
2499                 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2500                 retval = -EINVAL;
2501 #endif
2502         }
2503
2504 #ifndef NO_FS_PHY_HW_CHECKS
2505         if (val == 1 && !(hsotg->hwcfg3 & GHWCFG3_I2C))
2506                 valid = 0;
2507
2508         if (!valid) {
2509                 if (val >= 0)
2510                         dev_err(hsotg->dev,
2511                                 "%d invalid for i2c_enable. Check HW configuration.\n",
2512                                 val);
2513                 val = !!(hsotg->hwcfg3 & GHWCFG3_I2C);
2514                 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2515                 retval = -EINVAL;
2516         }
2517 #endif
2518
2519         hsotg->core_params->i2c_enable = val;
2520         return retval;
2521 }
2522
2523 int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2524 {
2525         int valid = 1;
2526         int retval = 0;
2527
2528         if (DWC2_PARAM_TEST(val, 0, 1)) {
2529                 if (val >= 0) {
2530                         dev_err(hsotg->dev,
2531                                 "Wrong value for en_multiple_tx_fifo,\n");
2532                         dev_err(hsotg->dev,
2533                                 "en_multiple_tx_fifo must be 0 or 1\n");
2534                 }
2535                 valid = 0;
2536         }
2537
2538         if (val == 1 && !(hsotg->hwcfg4 & GHWCFG4_DED_FIFO_EN))
2539                 valid = 0;
2540
2541         if (!valid) {
2542                 if (val >= 0)
2543                         dev_err(hsotg->dev,
2544                                 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2545                                 val);
2546                 val = !!(hsotg->hwcfg4 & GHWCFG4_DED_FIFO_EN);
2547                 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2548                 retval = -EINVAL;
2549         }
2550
2551         hsotg->core_params->en_multiple_tx_fifo = val;
2552         return retval;
2553 }
2554
2555 int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2556 {
2557         int valid = 1;
2558         int retval = 0;
2559
2560         if (DWC2_PARAM_TEST(val, 0, 1)) {
2561                 if (val >= 0) {
2562                         dev_err(hsotg->dev,
2563                                 "'%d' invalid for parameter reload_ctl\n", val);
2564                         dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2565                 }
2566                 valid = 0;
2567         }
2568
2569         if (val == 1 && hsotg->snpsid < DWC2_CORE_REV_2_92a)
2570                 valid = 0;
2571
2572         if (!valid) {
2573                 if (val >= 0)
2574                         dev_err(hsotg->dev,
2575                                 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2576                                 val);
2577                 val = hsotg->snpsid >= DWC2_CORE_REV_2_92a;
2578                 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2579                 retval = -EINVAL;
2580         }
2581
2582         hsotg->core_params->reload_ctl = val;
2583         return retval;
2584 }
2585
2586 int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2587 {
2588         if (val != -1)
2589                 hsotg->core_params->ahbcfg = val;
2590         else
2591                 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4;
2592         return 0;
2593 }
2594
2595 int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2596 {
2597         int retval = 0;
2598
2599         if (DWC2_PARAM_TEST(val, 0, 1)) {
2600                 if (val >= 0) {
2601                         dev_err(hsotg->dev,
2602                                 "'%d' invalid for parameter otg_ver\n", val);
2603                         dev_err(hsotg->dev,
2604                                 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2605                 }
2606                 val = 0;
2607                 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2608                 retval = -EINVAL;
2609         }
2610
2611         hsotg->core_params->otg_ver = val;
2612         return retval;
2613 }
2614
2615 /*
2616  * This function is called during module intialization to pass module parameters
2617  * for the DWC_otg core. It returns non-0 if any parameters are invalid.
2618  */
2619 int dwc2_set_parameters(struct dwc2_hsotg *hsotg,
2620                         const struct dwc2_core_params *params)
2621 {
2622         int retval = 0;
2623
2624         dev_dbg(hsotg->dev, "%s()\n", __func__);
2625
2626         retval |= dwc2_set_param_otg_cap(hsotg, params->otg_cap);
2627         retval |= dwc2_set_param_dma_enable(hsotg, params->dma_enable);
2628         retval |= dwc2_set_param_dma_desc_enable(hsotg,
2629                                                  params->dma_desc_enable);
2630         retval |= dwc2_set_param_host_support_fs_ls_low_power(hsotg,
2631                         params->host_support_fs_ls_low_power);
2632         retval |= dwc2_set_param_enable_dynamic_fifo(hsotg,
2633                         params->enable_dynamic_fifo);
2634         retval |= dwc2_set_param_host_rx_fifo_size(hsotg,
2635                         params->host_rx_fifo_size);
2636         retval |= dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
2637                         params->host_nperio_tx_fifo_size);
2638         retval |= dwc2_set_param_host_perio_tx_fifo_size(hsotg,
2639                         params->host_perio_tx_fifo_size);
2640         retval |= dwc2_set_param_max_transfer_size(hsotg,
2641                         params->max_transfer_size);
2642         retval |= dwc2_set_param_max_packet_count(hsotg,
2643                         params->max_packet_count);
2644         retval |= dwc2_set_param_host_channels(hsotg, params->host_channels);
2645         retval |= dwc2_set_param_phy_type(hsotg, params->phy_type);
2646         retval |= dwc2_set_param_speed(hsotg, params->speed);
2647         retval |= dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
2648                         params->host_ls_low_power_phy_clk);
2649         retval |= dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
2650         retval |= dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
2651                         params->phy_ulpi_ext_vbus);
2652         retval |= dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
2653         retval |= dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
2654         retval |= dwc2_set_param_ts_dline(hsotg, params->ts_dline);
2655         retval |= dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
2656         retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg,
2657                         params->en_multiple_tx_fifo);
2658         retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
2659         retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
2660         retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver);
2661
2662         return retval;
2663 }
2664
2665 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
2666 {
2667         return (u16)(hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103);
2668 }
2669
2670 int dwc2_check_core_status(struct dwc2_hsotg *hsotg)
2671 {
2672         if (readl(hsotg->regs + GSNPSID) == 0xffffffff)
2673                 return -1;
2674         else
2675                 return 0;
2676 }
2677
2678 /**
2679  * dwc2_enable_global_interrupts() - Enables the controller's Global
2680  * Interrupt in the AHB Config register
2681  *
2682  * @hsotg: Programming view of DWC_otg controller
2683  */
2684 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
2685 {
2686         u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2687
2688         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
2689         writel(ahbcfg, hsotg->regs + GAHBCFG);
2690 }
2691
2692 /**
2693  * dwc2_disable_global_interrupts() - Disables the controller's Global
2694  * Interrupt in the AHB Config register
2695  *
2696  * @hsotg: Programming view of DWC_otg controller
2697  */
2698 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
2699 {
2700         u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2701
2702         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2703         writel(ahbcfg, hsotg->regs + GAHBCFG);
2704 }
2705
2706 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
2707 MODULE_AUTHOR("Synopsys, Inc.");
2708 MODULE_LICENSE("Dual BSD/GPL");