2 * core.c - DesignWare HS OTG Controller common routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/moduleparam.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
60 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
61 * used in both device and host modes
63 * @hsotg: Programming view of the DWC_otg controller
65 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
69 /* Clear any pending OTG Interrupts */
70 writel(0xffffffff, hsotg->regs + GOTGINT);
72 /* Clear any pending interrupts */
73 writel(0xffffffff, hsotg->regs + GINTSTS);
75 /* Enable the interrupts in the GINTMSK */
76 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
78 if (hsotg->core_params->dma_enable <= 0)
79 intmsk |= GINTSTS_RXFLVL;
81 intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP |
84 writel(intmsk, hsotg->regs + GINTMSK);
88 * Initializes the FSLSPClkSel field of the HCFG register depending on the
91 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
93 u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
94 u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
97 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
98 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
99 hsotg->core_params->ulpi_fs_ls > 0) ||
100 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
102 val = HCFG_FSLSPCLKSEL_48_MHZ;
104 /* High speed PHY running at full speed or high speed */
105 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
108 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
109 hcfg = readl(hsotg->regs + HCFG);
110 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
112 writel(hcfg, hsotg->regs + HCFG);
116 * Do core a soft reset of the core. Be careful with this because it
117 * resets all the internal state machines of the core.
119 static void dwc2_core_reset(struct dwc2_hsotg *hsotg)
124 dev_vdbg(hsotg->dev, "%s()\n", __func__);
126 /* Wait for AHB master IDLE state */
128 usleep_range(20000, 40000);
129 greset = readl(hsotg->regs + GRSTCTL);
132 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
136 } while (!(greset & GRSTCTL_AHBIDLE));
138 /* Core Soft Reset */
140 greset |= GRSTCTL_CSFTRST;
141 writel(greset, hsotg->regs + GRSTCTL);
143 usleep_range(20000, 40000);
144 greset = readl(hsotg->regs + GRSTCTL);
147 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
151 } while (greset & GRSTCTL_CSFTRST);
154 * NOTE: This long sleep is _very_ important, otherwise the core will
155 * not stay in host mode after a connector ID change!
157 usleep_range(150000, 200000);
160 static void dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
165 * core_init() is now called on every switch so only call the
166 * following for the first time through
169 dev_dbg(hsotg->dev, "FS PHY selected\n");
170 usbcfg = readl(hsotg->regs + GUSBCFG);
171 usbcfg |= GUSBCFG_PHYSEL;
172 writel(usbcfg, hsotg->regs + GUSBCFG);
174 /* Reset after a PHY select */
175 dwc2_core_reset(hsotg);
179 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
180 * do this on HNP Dev/Host mode switches (done in dev_init and
183 if (dwc2_is_host_mode(hsotg))
184 dwc2_init_fs_ls_pclk_sel(hsotg);
186 if (hsotg->core_params->i2c_enable > 0) {
187 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
189 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
190 usbcfg = readl(hsotg->regs + GUSBCFG);
191 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
192 writel(usbcfg, hsotg->regs + GUSBCFG);
194 /* Program GI2CCTL.I2CEn */
195 i2cctl = readl(hsotg->regs + GI2CCTL);
196 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
197 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
198 i2cctl &= ~GI2CCTL_I2CEN;
199 writel(i2cctl, hsotg->regs + GI2CCTL);
200 i2cctl |= GI2CCTL_I2CEN;
201 writel(i2cctl, hsotg->regs + GI2CCTL);
205 static void dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
212 usbcfg = readl(hsotg->regs + GUSBCFG);
215 * HS PHY parameters. These parameters are preserved during soft reset
216 * so only program the first time. Do a soft reset immediately after
219 switch (hsotg->core_params->phy_type) {
220 case DWC2_PHY_TYPE_PARAM_ULPI:
222 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
223 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
224 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
225 if (hsotg->core_params->phy_ulpi_ddr > 0)
226 usbcfg |= GUSBCFG_DDRSEL;
228 case DWC2_PHY_TYPE_PARAM_UTMI:
229 /* UTMI+ interface */
230 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
231 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
232 if (hsotg->core_params->phy_utmi_width == 16)
233 usbcfg |= GUSBCFG_PHYIF16;
236 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
240 writel(usbcfg, hsotg->regs + GUSBCFG);
242 /* Reset after setting the PHY parameters */
243 dwc2_core_reset(hsotg);
246 static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
248 u32 usbcfg, hs_phy_type, fs_phy_type;
250 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
251 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
252 /* If FS mode with FS PHY */
253 dwc2_fs_phy_init(hsotg, select_phy);
256 dwc2_hs_phy_init(hsotg, select_phy);
259 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
260 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
262 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
263 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
264 hsotg->core_params->ulpi_fs_ls > 0) {
265 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
266 usbcfg = readl(hsotg->regs + GUSBCFG);
267 usbcfg |= GUSBCFG_ULPI_FS_LS;
268 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
269 writel(usbcfg, hsotg->regs + GUSBCFG);
271 usbcfg = readl(hsotg->regs + GUSBCFG);
272 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
273 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
274 writel(usbcfg, hsotg->regs + GUSBCFG);
278 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
282 switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
283 case GHWCFG2_EXT_DMA_ARCH:
284 dev_err(hsotg->dev, "External DMA Mode not supported\n");
287 case GHWCFG2_INT_DMA_ARCH:
288 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
290 * Old value was GAHBCFG_HBSTLEN_INCR - done for
291 * Host mode ISOC in issue fix - vahrama
293 ahbcfg |= GAHBCFG_HBSTLEN_INCR4;
296 case GHWCFG2_SLAVE_ONLY_ARCH:
298 dev_dbg(hsotg->dev, "Slave Only Mode\n");
302 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
303 hsotg->core_params->dma_enable,
304 hsotg->core_params->dma_desc_enable);
306 if (hsotg->core_params->dma_enable > 0) {
307 if (hsotg->core_params->dma_desc_enable > 0)
308 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
310 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
312 dev_dbg(hsotg->dev, "Using Slave mode\n");
313 hsotg->core_params->dma_desc_enable = 0;
316 if (hsotg->core_params->ahb_single > 0)
317 ahbcfg |= GAHBCFG_AHB_SINGLE;
319 if (hsotg->core_params->dma_enable > 0)
320 ahbcfg |= GAHBCFG_DMA_EN;
322 writel(ahbcfg, hsotg->regs + GAHBCFG);
327 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
331 usbcfg = readl(hsotg->regs + GUSBCFG);
332 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
334 switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
335 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
336 if (hsotg->core_params->otg_cap ==
337 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_HNPCAP;
339 if (hsotg->core_params->otg_cap !=
340 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
341 usbcfg |= GUSBCFG_SRPCAP;
344 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
345 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
346 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
347 if (hsotg->core_params->otg_cap !=
348 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
349 usbcfg |= GUSBCFG_SRPCAP;
352 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
353 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
354 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
359 writel(usbcfg, hsotg->regs + GUSBCFG);
363 * dwc2_core_init() - Initializes the DWC_otg controller registers and
364 * prepares the core for device mode or host mode operation
366 * @hsotg: Programming view of the DWC_otg controller
367 * @select_phy: If true then also set the Phy type
368 * @irq: If >= 0, the irq to register
370 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq)
375 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
377 usbcfg = readl(hsotg->regs + GUSBCFG);
379 /* Set ULPI External VBUS bit if needed */
380 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
381 if (hsotg->core_params->phy_ulpi_ext_vbus ==
382 DWC2_PHY_ULPI_EXTERNAL_VBUS)
383 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
385 /* Set external TS Dline pulsing bit if needed */
386 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
387 if (hsotg->core_params->ts_dline > 0)
388 usbcfg |= GUSBCFG_TERMSELDLPULSE;
390 writel(usbcfg, hsotg->regs + GUSBCFG);
392 /* Reset the Controller */
393 dwc2_core_reset(hsotg);
395 dev_dbg(hsotg->dev, "num_dev_perio_in_ep=%d\n",
396 hsotg->hwcfg4 >> GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT &
397 GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK >>
398 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT);
400 hsotg->total_fifo_size = hsotg->hwcfg3 >> GHWCFG3_DFIFO_DEPTH_SHIFT &
401 GHWCFG3_DFIFO_DEPTH_MASK >> GHWCFG3_DFIFO_DEPTH_SHIFT;
402 hsotg->rx_fifo_size = readl(hsotg->regs + GRXFSIZ);
403 hsotg->nperio_tx_fifo_size =
404 readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
406 dev_dbg(hsotg->dev, "Total FIFO SZ=%d\n", hsotg->total_fifo_size);
407 dev_dbg(hsotg->dev, "RxFIFO SZ=%d\n", hsotg->rx_fifo_size);
408 dev_dbg(hsotg->dev, "NP TxFIFO SZ=%d\n", hsotg->nperio_tx_fifo_size);
411 * This needs to happen in FS mode before any other programming occurs
413 dwc2_phy_init(hsotg, select_phy);
415 /* Program the GAHBCFG Register */
416 retval = dwc2_gahbcfg_init(hsotg);
420 /* Program the GUSBCFG register */
421 dwc2_gusbcfg_init(hsotg);
423 /* Program the GOTGCTL register */
424 otgctl = readl(hsotg->regs + GOTGCTL);
425 otgctl &= ~GOTGCTL_OTGVER;
426 if (hsotg->core_params->otg_ver > 0)
427 otgctl |= GOTGCTL_OTGVER;
428 writel(otgctl, hsotg->regs + GOTGCTL);
429 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
431 /* Clear the SRP success bit for FS-I2c */
432 hsotg->srp_success = 0;
435 dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
437 retval = devm_request_irq(hsotg->dev, irq,
438 dwc2_handle_common_intr, IRQF_SHARED,
439 dev_name(hsotg->dev), hsotg);
444 /* Enable common interrupts */
445 dwc2_enable_common_interrupts(hsotg);
448 * Do device or host intialization based on mode during PCD and
451 if (dwc2_is_host_mode(hsotg)) {
452 dev_dbg(hsotg->dev, "Host Mode\n");
453 hsotg->op_state = OTG_STATE_A_HOST;
455 dev_dbg(hsotg->dev, "Device Mode\n");
456 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
463 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
465 * @hsotg: Programming view of DWC_otg controller
467 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
471 dev_dbg(hsotg->dev, "%s()\n", __func__);
473 /* Disable all interrupts */
474 writel(0, hsotg->regs + GINTMSK);
475 writel(0, hsotg->regs + HAINTMSK);
477 /* Clear any pending interrupts */
478 writel(0xffffffff, hsotg->regs + GINTSTS);
480 /* Enable the common interrupts */
481 dwc2_enable_common_interrupts(hsotg);
483 /* Enable host mode interrupts without disturbing common interrupts */
484 intmsk = readl(hsotg->regs + GINTMSK);
485 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
486 writel(intmsk, hsotg->regs + GINTMSK);
490 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
492 * @hsotg: Programming view of DWC_otg controller
494 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
496 u32 intmsk = readl(hsotg->regs + GINTMSK);
498 /* Disable host mode interrupts without disturbing common interrupts */
499 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
500 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP);
501 writel(intmsk, hsotg->regs + GINTMSK);
504 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
506 struct dwc2_core_params *params = hsotg->core_params;
507 u32 rxfsiz, nptxfsiz, ptxfsiz, hptxfsiz, dfifocfg;
509 if (!params->enable_dynamic_fifo)
512 dev_dbg(hsotg->dev, "Total FIFO Size=%d\n", hsotg->total_fifo_size);
513 dev_dbg(hsotg->dev, "Rx FIFO Size=%d\n", params->host_rx_fifo_size);
514 dev_dbg(hsotg->dev, "NP Tx FIFO Size=%d\n",
515 params->host_nperio_tx_fifo_size);
516 dev_dbg(hsotg->dev, "P Tx FIFO Size=%d\n",
517 params->host_perio_tx_fifo_size);
520 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n",
521 readl(hsotg->regs + GRXFSIZ));
522 writel(params->host_rx_fifo_size, hsotg->regs + GRXFSIZ);
523 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ));
525 /* Non-periodic Tx FIFO */
526 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
527 readl(hsotg->regs + GNPTXFSIZ));
528 nptxfsiz = params->host_nperio_tx_fifo_size <<
529 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
530 nptxfsiz |= params->host_rx_fifo_size <<
531 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
532 writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
533 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
534 readl(hsotg->regs + GNPTXFSIZ));
536 /* Periodic Tx FIFO */
537 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
538 readl(hsotg->regs + HPTXFSIZ));
539 ptxfsiz = params->host_perio_tx_fifo_size <<
540 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
541 ptxfsiz |= (params->host_rx_fifo_size +
542 params->host_nperio_tx_fifo_size) <<
543 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
544 writel(ptxfsiz, hsotg->regs + HPTXFSIZ);
545 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
546 readl(hsotg->regs + HPTXFSIZ));
548 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
549 hsotg->snpsid <= DWC2_CORE_REV_2_94a) {
551 * Global DFIFOCFG calculation for Host mode -
552 * include RxFIFO, NPTXFIFO and HPTXFIFO
554 dfifocfg = readl(hsotg->regs + GDFIFOCFG);
555 rxfsiz = readl(hsotg->regs + GRXFSIZ) & 0x0000ffff;
556 nptxfsiz = readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
557 hptxfsiz = readl(hsotg->regs + HPTXFSIZ) >> 16 & 0xffff;
558 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
559 dfifocfg |= (rxfsiz + nptxfsiz + hptxfsiz) <<
560 GDFIFOCFG_EPINFOBASE_SHIFT &
561 GDFIFOCFG_EPINFOBASE_MASK;
562 writel(dfifocfg, hsotg->regs + GDFIFOCFG);
567 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
570 * @hsotg: Programming view of DWC_otg controller
572 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
573 * request queues. Host channels are reset to ensure that they are ready for
574 * performing transfers.
576 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
578 u32 hcfg, hfir, otgctl;
580 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
582 /* Restart the Phy Clock */
583 writel(0, hsotg->regs + PCGCTL);
585 /* Initialize Host Configuration Register */
586 dwc2_init_fs_ls_pclk_sel(hsotg);
587 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
588 hcfg = readl(hsotg->regs + HCFG);
589 hcfg |= HCFG_FSLSSUPP;
590 writel(hcfg, hsotg->regs + HCFG);
594 * This bit allows dynamic reloading of the HFIR register during
595 * runtime. This bit needs to be programmed during inital configuration
596 * and its value must not be changed during runtime.
598 if (hsotg->core_params->reload_ctl > 0) {
599 hfir = readl(hsotg->regs + HFIR);
600 hfir |= HFIR_RLDCTRL;
601 writel(hfir, hsotg->regs + HFIR);
604 if (hsotg->core_params->dma_desc_enable > 0) {
605 u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
607 if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
608 !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
609 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
610 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
611 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
613 "Hardware does not support descriptor DMA mode -\n");
615 "falling back to buffer DMA mode.\n");
616 hsotg->core_params->dma_desc_enable = 0;
618 hcfg = readl(hsotg->regs + HCFG);
619 hcfg |= HCFG_DESCDMA;
620 writel(hcfg, hsotg->regs + HCFG);
624 /* Configure data FIFO sizes */
625 dwc2_config_fifos(hsotg);
627 /* TODO - check this */
628 /* Clear Host Set HNP Enable in the OTG Control Register */
629 otgctl = readl(hsotg->regs + GOTGCTL);
630 otgctl &= ~GOTGCTL_HSTSETHNPEN;
631 writel(otgctl, hsotg->regs + GOTGCTL);
633 /* Make sure the FIFOs are flushed */
634 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
635 dwc2_flush_rx_fifo(hsotg);
637 /* Clear Host Set HNP Enable in the OTG Control Register */
638 otgctl = readl(hsotg->regs + GOTGCTL);
639 otgctl &= ~GOTGCTL_HSTSETHNPEN;
640 writel(otgctl, hsotg->regs + GOTGCTL);
642 if (hsotg->core_params->dma_desc_enable <= 0) {
646 /* Flush out any leftover queued requests */
647 num_channels = hsotg->core_params->host_channels;
648 for (i = 0; i < num_channels; i++) {
649 hcchar = readl(hsotg->regs + HCCHAR(i));
650 hcchar &= ~HCCHAR_CHENA;
651 hcchar |= HCCHAR_CHDIS;
652 hcchar &= ~HCCHAR_EPDIR;
653 writel(hcchar, hsotg->regs + HCCHAR(i));
656 /* Halt all channels to put them into a known state */
657 for (i = 0; i < num_channels; i++) {
660 hcchar = readl(hsotg->regs + HCCHAR(i));
661 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
662 hcchar &= ~HCCHAR_EPDIR;
663 writel(hcchar, hsotg->regs + HCCHAR(i));
664 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
667 hcchar = readl(hsotg->regs + HCCHAR(i));
668 if (++count > 1000) {
670 "Unable to clear enable on channel %d\n",
675 } while (hcchar & HCCHAR_CHENA);
679 /* Turn on the vbus power */
680 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
681 if (hsotg->op_state == OTG_STATE_A_HOST) {
682 u32 hprt0 = dwc2_read_hprt0(hsotg);
684 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
685 !!(hprt0 & HPRT0_PWR));
686 if (!(hprt0 & HPRT0_PWR)) {
688 writel(hprt0, hsotg->regs + HPRT0);
692 dwc2_enable_host_interrupts(hsotg);
695 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
696 struct dwc2_host_chan *chan)
698 u32 hcintmsk = HCINTMSK_CHHLTD;
700 switch (chan->ep_type) {
701 case USB_ENDPOINT_XFER_CONTROL:
702 case USB_ENDPOINT_XFER_BULK:
703 dev_vdbg(hsotg->dev, "control/bulk\n");
704 hcintmsk |= HCINTMSK_XFERCOMPL;
705 hcintmsk |= HCINTMSK_STALL;
706 hcintmsk |= HCINTMSK_XACTERR;
707 hcintmsk |= HCINTMSK_DATATGLERR;
708 if (chan->ep_is_in) {
709 hcintmsk |= HCINTMSK_BBLERR;
711 hcintmsk |= HCINTMSK_NAK;
712 hcintmsk |= HCINTMSK_NYET;
714 hcintmsk |= HCINTMSK_ACK;
717 if (chan->do_split) {
718 hcintmsk |= HCINTMSK_NAK;
719 if (chan->complete_split)
720 hcintmsk |= HCINTMSK_NYET;
722 hcintmsk |= HCINTMSK_ACK;
725 if (chan->error_state)
726 hcintmsk |= HCINTMSK_ACK;
729 case USB_ENDPOINT_XFER_INT:
731 dev_vdbg(hsotg->dev, "intr\n");
732 hcintmsk |= HCINTMSK_XFERCOMPL;
733 hcintmsk |= HCINTMSK_NAK;
734 hcintmsk |= HCINTMSK_STALL;
735 hcintmsk |= HCINTMSK_XACTERR;
736 hcintmsk |= HCINTMSK_DATATGLERR;
737 hcintmsk |= HCINTMSK_FRMOVRUN;
740 hcintmsk |= HCINTMSK_BBLERR;
741 if (chan->error_state)
742 hcintmsk |= HCINTMSK_ACK;
743 if (chan->do_split) {
744 if (chan->complete_split)
745 hcintmsk |= HCINTMSK_NYET;
747 hcintmsk |= HCINTMSK_ACK;
751 case USB_ENDPOINT_XFER_ISOC:
753 dev_vdbg(hsotg->dev, "isoc\n");
754 hcintmsk |= HCINTMSK_XFERCOMPL;
755 hcintmsk |= HCINTMSK_FRMOVRUN;
756 hcintmsk |= HCINTMSK_ACK;
758 if (chan->ep_is_in) {
759 hcintmsk |= HCINTMSK_XACTERR;
760 hcintmsk |= HCINTMSK_BBLERR;
764 dev_err(hsotg->dev, "## Unknown EP type ##\n");
768 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
770 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
773 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
774 struct dwc2_host_chan *chan)
776 u32 hcintmsk = HCINTMSK_CHHLTD;
779 * For Descriptor DMA mode core halts the channel on AHB error.
780 * Interrupt is not required.
782 if (hsotg->core_params->dma_desc_enable <= 0) {
784 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
785 hcintmsk |= HCINTMSK_AHBERR;
788 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
789 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
790 hcintmsk |= HCINTMSK_XFERCOMPL;
793 if (chan->error_state && !chan->do_split &&
794 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
796 dev_vdbg(hsotg->dev, "setting ACK\n");
797 hcintmsk |= HCINTMSK_ACK;
798 if (chan->ep_is_in) {
799 hcintmsk |= HCINTMSK_DATATGLERR;
800 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
801 hcintmsk |= HCINTMSK_NAK;
805 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
807 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
810 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
811 struct dwc2_host_chan *chan)
815 if (hsotg->core_params->dma_enable > 0) {
817 dev_vdbg(hsotg->dev, "DMA enabled\n");
818 dwc2_hc_enable_dma_ints(hsotg, chan);
821 dev_vdbg(hsotg->dev, "DMA disabled\n");
822 dwc2_hc_enable_slave_ints(hsotg, chan);
825 /* Enable the top level host channel interrupt */
826 intmsk = readl(hsotg->regs + HAINTMSK);
827 intmsk |= 1 << chan->hc_num;
828 writel(intmsk, hsotg->regs + HAINTMSK);
830 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
832 /* Make sure host channel interrupts are enabled */
833 intmsk = readl(hsotg->regs + GINTMSK);
834 intmsk |= GINTSTS_HCHINT;
835 writel(intmsk, hsotg->regs + GINTMSK);
837 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
841 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
842 * a specific endpoint
844 * @hsotg: Programming view of DWC_otg controller
845 * @chan: Information needed to initialize the host channel
847 * The HCCHARn register is set up with the characteristics specified in chan.
848 * Host channel interrupts that may need to be serviced while this transfer is
849 * in progress are enabled.
851 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
853 u8 hc_num = chan->hc_num;
859 dev_vdbg(hsotg->dev, "%s()\n", __func__);
861 /* Clear old interrupt conditions for this host channel */
862 hcintmsk = 0xffffffff;
863 hcintmsk &= ~HCINTMSK_RESERVED14_31;
864 writel(hcintmsk, hsotg->regs + HCINT(hc_num));
866 /* Enable channel interrupts required for this transfer */
867 dwc2_hc_enable_ints(hsotg, chan);
870 * Program the HCCHARn register with the endpoint characteristics for
871 * the current transfer
873 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
874 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
876 hcchar |= HCCHAR_EPDIR;
877 if (chan->speed == USB_SPEED_LOW)
878 hcchar |= HCCHAR_LSPDDEV;
879 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
880 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
881 writel(hcchar, hsotg->regs + HCCHAR(hc_num));
883 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
886 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, hc_num);
887 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
888 hcchar >> HCCHAR_DEVADDR_SHIFT &
889 HCCHAR_DEVADDR_MASK >> HCCHAR_DEVADDR_SHIFT);
890 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
891 hcchar >> HCCHAR_EPNUM_SHIFT &
892 HCCHAR_EPNUM_MASK >> HCCHAR_EPNUM_SHIFT);
893 dev_vdbg(hsotg->dev, " Is In: %d\n",
894 !!(hcchar & HCCHAR_EPDIR));
895 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
896 !!(hcchar & HCCHAR_LSPDDEV));
897 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
898 hcchar >> HCCHAR_EPTYPE_SHIFT &
899 HCCHAR_EPTYPE_MASK >> HCCHAR_EPTYPE_SHIFT);
900 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
901 hcchar >> HCCHAR_MPS_SHIFT &
902 HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
903 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
904 hcchar >> HCCHAR_MULTICNT_SHIFT &
905 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
908 /* Program the HCSPLT register for SPLITs */
909 if (chan->do_split) {
912 "Programming HC %d with split --> %s\n",
914 chan->complete_split ? "CSPLIT" : "SSPLIT");
915 if (chan->complete_split)
916 hcsplt |= HCSPLT_COMPSPLT;
917 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
919 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
921 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
924 dev_vdbg(hsotg->dev, " comp split %d\n",
925 chan->complete_split);
926 dev_vdbg(hsotg->dev, " xact pos %d\n",
928 dev_vdbg(hsotg->dev, " hub addr %d\n",
930 dev_vdbg(hsotg->dev, " hub port %d\n",
932 dev_vdbg(hsotg->dev, " is_in %d\n",
934 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
935 hcchar >> HCCHAR_MPS_SHIFT &
936 HCCHAR_MPS_MASK >> HCCHAR_MPS_SHIFT);
937 dev_vdbg(hsotg->dev, " xferlen %d\n",
942 writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
946 * dwc2_hc_halt() - Attempts to halt a host channel
948 * @hsotg: Controller register interface
949 * @chan: Host channel to halt
950 * @halt_status: Reason for halting the channel
952 * This function should only be called in Slave mode or to abort a transfer in
953 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
954 * controller halts the channel when the transfer is complete or a condition
955 * occurs that requires application intervention.
957 * In slave mode, checks for a free request queue entry, then sets the Channel
958 * Enable and Channel Disable bits of the Host Channel Characteristics
959 * register of the specified channel to intiate the halt. If there is no free
960 * request queue entry, sets only the Channel Disable bit of the HCCHARn
961 * register to flush requests for this channel. In the latter case, sets a
962 * flag to indicate that the host channel needs to be halted when a request
963 * queue slot is open.
965 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
966 * HCCHARn register. The controller ensures there is space in the request
967 * queue before submitting the halt request.
969 * Some time may elapse before the core flushes any posted requests for this
970 * host channel and halts. The Channel Halted interrupt handler completes the
971 * deactivation of the host channel.
973 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
974 enum dwc2_halt_status halt_status)
976 u32 nptxsts, hptxsts, hcchar;
979 dev_vdbg(hsotg->dev, "%s()\n", __func__);
980 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
981 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
983 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
984 halt_status == DWC2_HC_XFER_AHB_ERR) {
986 * Disable all channel interrupts except Ch Halted. The QTD
987 * and QH state associated with this transfer has been cleared
988 * (in the case of URB_DEQUEUE), so the channel needs to be
989 * shut down carefully to prevent crashes.
991 u32 hcintmsk = HCINTMSK_CHHLTD;
993 dev_vdbg(hsotg->dev, "dequeue/error\n");
994 writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
997 * Make sure no other interrupts besides halt are currently
998 * pending. Handling another interrupt could cause a crash due
999 * to the QTD and QH state.
1001 writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1004 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1005 * even if the channel was already halted for some other
1008 chan->halt_status = halt_status;
1010 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1011 if (!(hcchar & HCCHAR_CHENA)) {
1013 * The channel is either already halted or it hasn't
1014 * started yet. In DMA mode, the transfer may halt if
1015 * it finishes normally or a condition occurs that
1016 * requires driver intervention. Don't want to halt
1017 * the channel again. In either Slave or DMA mode,
1018 * it's possible that the transfer has been assigned
1019 * to a channel, but not started yet when an URB is
1020 * dequeued. Don't want to halt a channel that hasn't
1026 if (chan->halt_pending) {
1028 * A halt has already been issued for this channel. This might
1029 * happen when a transfer is aborted by a higher level in
1032 dev_vdbg(hsotg->dev,
1033 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1034 __func__, chan->hc_num);
1038 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1040 /* No need to set the bit in DDMA for disabling the channel */
1041 /* TODO check it everywhere channel is disabled */
1042 if (hsotg->core_params->dma_desc_enable <= 0) {
1044 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1045 hcchar |= HCCHAR_CHENA;
1048 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1050 hcchar |= HCCHAR_CHDIS;
1052 if (hsotg->core_params->dma_enable <= 0) {
1054 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1055 hcchar |= HCCHAR_CHENA;
1057 /* Check for space in the request queue to issue the halt */
1058 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1059 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1060 dev_vdbg(hsotg->dev, "control/bulk\n");
1061 nptxsts = readl(hsotg->regs + GNPTXSTS);
1062 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1063 dev_vdbg(hsotg->dev, "Disabling channel\n");
1064 hcchar &= ~HCCHAR_CHENA;
1068 dev_vdbg(hsotg->dev, "isoc/intr\n");
1069 hptxsts = readl(hsotg->regs + HPTXSTS);
1070 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1071 hsotg->queuing_high_bandwidth) {
1073 dev_vdbg(hsotg->dev, "Disabling channel\n");
1074 hcchar &= ~HCCHAR_CHENA;
1079 dev_vdbg(hsotg->dev, "DMA enabled\n");
1082 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1083 chan->halt_status = halt_status;
1085 if (hcchar & HCCHAR_CHENA) {
1087 dev_vdbg(hsotg->dev, "Channel enabled\n");
1088 chan->halt_pending = 1;
1089 chan->halt_on_queue = 0;
1092 dev_vdbg(hsotg->dev, "Channel disabled\n");
1093 chan->halt_on_queue = 1;
1097 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1099 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1101 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1102 chan->halt_pending);
1103 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1104 chan->halt_on_queue);
1105 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1111 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1113 * @hsotg: Programming view of DWC_otg controller
1114 * @chan: Identifies the host channel to clean up
1116 * This function is normally called after a transfer is done and the host
1117 * channel is being released
1119 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1123 chan->xfer_started = 0;
1126 * Clear channel interrupt enables and any unhandled channel interrupt
1129 writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1130 hcintmsk = 0xffffffff;
1131 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1132 writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1136 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1137 * which frame a periodic transfer should occur
1139 * @hsotg: Programming view of DWC_otg controller
1140 * @chan: Identifies the host channel to set up and its properties
1141 * @hcchar: Current value of the HCCHAR register for the specified host channel
1143 * This function has no effect on non-periodic transfers
1145 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1146 struct dwc2_host_chan *chan, u32 *hcchar)
1148 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1149 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1150 /* 1 if _next_ frame is odd, 0 if it's even */
1151 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1152 *hcchar |= HCCHAR_ODDFRM;
1156 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1158 /* Set up the initial PID for the transfer */
1159 if (chan->speed == USB_SPEED_HIGH) {
1160 if (chan->ep_is_in) {
1161 if (chan->multi_count == 1)
1162 chan->data_pid_start = DWC2_HC_PID_DATA0;
1163 else if (chan->multi_count == 2)
1164 chan->data_pid_start = DWC2_HC_PID_DATA1;
1166 chan->data_pid_start = DWC2_HC_PID_DATA2;
1168 if (chan->multi_count == 1)
1169 chan->data_pid_start = DWC2_HC_PID_DATA0;
1171 chan->data_pid_start = DWC2_HC_PID_MDATA;
1174 chan->data_pid_start = DWC2_HC_PID_DATA0;
1179 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1182 * @hsotg: Programming view of DWC_otg controller
1183 * @chan: Information needed to initialize the host channel
1185 * This function should only be called in Slave mode. For a channel associated
1186 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1187 * associated with a periodic EP, the periodic Tx FIFO is written.
1189 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1190 * the number of bytes written to the Tx FIFO.
1192 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1193 struct dwc2_host_chan *chan)
1196 u32 remaining_count;
1199 u32 __iomem *data_fifo;
1200 u32 *data_buf = (u32 *)chan->xfer_buf;
1203 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1205 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1207 remaining_count = chan->xfer_len - chan->xfer_count;
1208 if (remaining_count > chan->max_packet)
1209 byte_count = chan->max_packet;
1211 byte_count = remaining_count;
1213 dword_count = (byte_count + 3) / 4;
1215 if (((unsigned long)data_buf & 0x3) == 0) {
1216 /* xfer_buf is DWORD aligned */
1217 for (i = 0; i < dword_count; i++, data_buf++)
1218 writel(*data_buf, data_fifo);
1220 /* xfer_buf is not DWORD aligned */
1221 for (i = 0; i < dword_count; i++, data_buf++) {
1222 u32 data = data_buf[0] | data_buf[1] << 8 |
1223 data_buf[2] << 16 | data_buf[3] << 24;
1224 writel(data, data_fifo);
1228 chan->xfer_count += byte_count;
1229 chan->xfer_buf += byte_count;
1233 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1234 * channel and starts the transfer
1236 * @hsotg: Programming view of DWC_otg controller
1237 * @chan: Information needed to initialize the host channel. The xfer_len value
1238 * may be reduced to accommodate the max widths of the XferSize and
1239 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1240 * changed to reflect the final xfer_len value.
1242 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1243 * the caller must ensure that there is sufficient space in the request queue
1246 * For an OUT transfer in Slave mode, it loads a data packet into the
1247 * appropriate FIFO. If necessary, additional data packets are loaded in the
1250 * For an IN transfer in Slave mode, a data packet is requested. The data
1251 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1252 * additional data packets are requested in the Host ISR.
1254 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1255 * register along with a packet count of 1 and the channel is enabled. This
1256 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1257 * simply set to 0 since no data transfer occurs in this case.
1259 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1260 * all the information required to perform the subsequent data transfer. In
1261 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1262 * controller performs the entire PING protocol, then starts the data
1265 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1266 struct dwc2_host_chan *chan)
1268 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1269 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1275 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1277 if (chan->do_ping) {
1278 if (hsotg->core_params->dma_enable <= 0) {
1280 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1281 dwc2_hc_do_ping(hsotg, chan);
1282 chan->xfer_started = 1;
1286 dev_vdbg(hsotg->dev, "ping, DMA\n");
1287 hctsiz |= TSIZ_DOPNG;
1291 if (chan->do_split) {
1293 dev_vdbg(hsotg->dev, "split\n");
1296 if (chan->complete_split && !chan->ep_is_in)
1298 * For CSPLIT OUT Transfer, set the size to 0 so the
1299 * core doesn't expect any data written to the FIFO
1302 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1303 chan->xfer_len = chan->max_packet;
1304 else if (!chan->ep_is_in && chan->xfer_len > 188)
1305 chan->xfer_len = 188;
1307 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1311 dev_vdbg(hsotg->dev, "no split\n");
1313 * Ensure that the transfer length and packet count will fit
1314 * in the widths allocated for them in the HCTSIZn register
1316 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1317 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1319 * Make sure the transfer size is no larger than one
1320 * (micro)frame's worth of data. (A check was done
1321 * when the periodic transfer was accepted to ensure
1322 * that a (micro)frame's worth of data can be
1323 * programmed into a channel.)
1325 u32 max_periodic_len =
1326 chan->multi_count * chan->max_packet;
1328 if (chan->xfer_len > max_periodic_len)
1329 chan->xfer_len = max_periodic_len;
1330 } else if (chan->xfer_len > max_hc_xfer_size) {
1332 * Make sure that xfer_len is a multiple of max packet
1336 max_hc_xfer_size - chan->max_packet + 1;
1339 if (chan->xfer_len > 0) {
1340 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1342 if (num_packets > max_hc_pkt_count) {
1343 num_packets = max_hc_pkt_count;
1344 chan->xfer_len = num_packets * chan->max_packet;
1347 /* Need 1 packet for transfer length of 0 */
1353 * Always program an integral # of max packets for IN
1356 chan->xfer_len = num_packets * chan->max_packet;
1358 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1359 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1361 * Make sure that the multi_count field matches the
1362 * actual transfer length
1364 chan->multi_count = num_packets;
1366 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1367 dwc2_set_pid_isoc(chan);
1369 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1373 chan->start_pkt_count = num_packets;
1374 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1375 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1376 TSIZ_SC_MC_PID_MASK;
1377 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1379 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1380 hctsiz, chan->hc_num);
1382 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1384 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1385 hctsiz >> TSIZ_XFERSIZE_SHIFT &
1386 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
1387 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1388 hctsiz >> TSIZ_PKTCNT_SHIFT &
1389 TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
1390 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1391 hctsiz >> TSIZ_SC_MC_PID_SHIFT &
1392 TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);
1395 if (hsotg->core_params->dma_enable > 0) {
1396 dma_addr_t dma_addr;
1398 if (chan->align_buf) {
1400 dev_vdbg(hsotg->dev, "align_buf\n");
1401 dma_addr = chan->align_buf;
1403 dma_addr = chan->xfer_dma;
1405 writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1407 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1408 (unsigned long)dma_addr, chan->hc_num);
1411 /* Start the split */
1412 if (chan->do_split) {
1413 u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
1415 hcsplt |= HCSPLT_SPLTENA;
1416 writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1419 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1420 hcchar &= ~HCCHAR_MULTICNT_MASK;
1421 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1422 HCCHAR_MULTICNT_MASK;
1423 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1425 if (hcchar & HCCHAR_CHDIS)
1426 dev_warn(hsotg->dev,
1427 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1428 __func__, chan->hc_num, hcchar);
1430 /* Set host channel enable after all other setup is complete */
1431 hcchar |= HCCHAR_CHENA;
1432 hcchar &= ~HCCHAR_CHDIS;
1435 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1436 hcchar >> HCCHAR_MULTICNT_SHIFT &
1437 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
1439 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1441 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1444 chan->xfer_started = 1;
1447 if (hsotg->core_params->dma_enable <= 0 &&
1448 !chan->ep_is_in && chan->xfer_len > 0)
1449 /* Load OUT packet into the appropriate Tx FIFO */
1450 dwc2_hc_write_packet(hsotg, chan);
1454 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1455 * host channel and starts the transfer in Descriptor DMA mode
1457 * @hsotg: Programming view of DWC_otg controller
1458 * @chan: Information needed to initialize the host channel
1460 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1461 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1462 * with micro-frame bitmap.
1464 * Initializes HCDMA register with descriptor list address and CTD value then
1465 * starts the transfer via enabling the channel.
1467 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1468 struct dwc2_host_chan *chan)
1475 hctsiz |= TSIZ_DOPNG;
1477 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1478 dwc2_set_pid_isoc(chan);
1480 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1481 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1482 TSIZ_SC_MC_PID_MASK;
1484 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1485 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1487 /* Non-zero only for high-speed interrupt endpoints */
1488 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1491 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1493 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1494 chan->data_pid_start);
1495 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1498 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1500 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1502 /* Always start from first descriptor */
1503 hc_dma &= ~HCDMA_CTD_MASK;
1504 writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1506 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1507 hc_dma, chan->hc_num);
1509 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1510 hcchar &= ~HCCHAR_MULTICNT_MASK;
1511 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1512 HCCHAR_MULTICNT_MASK;
1514 if (hcchar & HCCHAR_CHDIS)
1515 dev_warn(hsotg->dev,
1516 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1517 __func__, chan->hc_num, hcchar);
1519 /* Set host channel enable after all other setup is complete */
1520 hcchar |= HCCHAR_CHENA;
1521 hcchar &= ~HCCHAR_CHDIS;
1524 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1525 hcchar >> HCCHAR_MULTICNT_SHIFT &
1526 HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
1528 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1530 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1533 chan->xfer_started = 1;
1538 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1539 * a previous call to dwc2_hc_start_transfer()
1541 * @hsotg: Programming view of DWC_otg controller
1542 * @chan: Information needed to initialize the host channel
1544 * The caller must ensure there is sufficient space in the request queue and Tx
1545 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1546 * the controller acts autonomously to complete transfers programmed to a host
1549 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1550 * if there is any data remaining to be queued. For an IN transfer, another
1551 * data packet is always requested. For the SETUP phase of a control transfer,
1552 * this function does nothing.
1554 * Return: 1 if a new request is queued, 0 if no more requests are required
1557 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1558 struct dwc2_host_chan *chan)
1561 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1565 /* SPLITs always queue just once per channel */
1568 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1569 /* SETUPs are queued only once since they can't be NAK'd */
1572 if (chan->ep_is_in) {
1574 * Always queue another request for other IN transfers. If
1575 * back-to-back INs are issued and NAKs are received for both,
1576 * the driver may still be processing the first NAK when the
1577 * second NAK is received. When the interrupt handler clears
1578 * the NAK interrupt for the first NAK, the second NAK will
1579 * not be seen. So we can't depend on the NAK interrupt
1580 * handler to requeue a NAK'd request. Instead, IN requests
1581 * are issued each time this function is called. When the
1582 * transfer completes, the extra requests for the channel will
1585 u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1587 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1588 hcchar |= HCCHAR_CHENA;
1589 hcchar &= ~HCCHAR_CHDIS;
1591 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1593 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1600 if (chan->xfer_count < chan->xfer_len) {
1601 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1602 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1603 u32 hcchar = readl(hsotg->regs +
1604 HCCHAR(chan->hc_num));
1606 dwc2_hc_set_even_odd_frame(hsotg, chan,
1610 /* Load OUT packet into the appropriate Tx FIFO */
1611 dwc2_hc_write_packet(hsotg, chan);
1620 * dwc2_hc_do_ping() - Starts a PING transfer
1622 * @hsotg: Programming view of DWC_otg controller
1623 * @chan: Information needed to initialize the host channel
1625 * This function should only be called in Slave mode. The Do Ping bit is set in
1626 * the HCTSIZ register, then the channel is enabled.
1628 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1634 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1638 hctsiz = TSIZ_DOPNG;
1639 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1640 writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1642 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
1643 hcchar |= HCCHAR_CHENA;
1644 hcchar &= ~HCCHAR_CHDIS;
1645 writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1649 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
1650 * the HFIR register according to PHY type and speed
1652 * @hsotg: Programming view of DWC_otg controller
1654 * NOTE: The caller can modify the value of the HFIR register only after the
1655 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
1658 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
1663 int clock = 60; /* default value */
1665 usbcfg = readl(hsotg->regs + GUSBCFG);
1666 hwcfg2 = readl(hsotg->regs + GHWCFG2);
1667 hprt0 = readl(hsotg->regs + HPRT0);
1669 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
1670 !(usbcfg & GUSBCFG_PHYIF16))
1672 if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1673 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
1675 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1676 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1678 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1679 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
1681 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
1682 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
1684 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
1685 (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1686 GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
1688 if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
1689 GHWCFG2_FS_PHY_TYPE_DEDICATED)
1692 if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)
1693 /* High speed case */
1697 return 1000 * clock;
1701 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
1704 * @core_if: Programming view of DWC_otg controller
1705 * @dest: Destination buffer for the packet
1706 * @bytes: Number of bytes to copy to the destination
1708 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
1710 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
1711 u32 *data_buf = (u32 *)dest;
1712 int word_count = (bytes + 3) / 4;
1716 * Todo: Account for the case where dest is not dword aligned. This
1717 * requires reading data from the FIFO into a u32 temp buffer, then
1718 * moving it into the data buffer.
1721 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
1723 for (i = 0; i < word_count; i++, data_buf++)
1724 *data_buf = readl(fifo);
1728 * dwc2_dump_host_registers() - Prints the host registers
1730 * @hsotg: Programming view of DWC_otg controller
1732 * NOTE: This function will be removed once the peripheral controller code
1733 * is integrated and the driver is stable
1735 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
1741 dev_dbg(hsotg->dev, "Host Global Registers\n");
1742 addr = hsotg->regs + HCFG;
1743 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
1744 (unsigned long)addr, readl(addr));
1745 addr = hsotg->regs + HFIR;
1746 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
1747 (unsigned long)addr, readl(addr));
1748 addr = hsotg->regs + HFNUM;
1749 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
1750 (unsigned long)addr, readl(addr));
1751 addr = hsotg->regs + HPTXSTS;
1752 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
1753 (unsigned long)addr, readl(addr));
1754 addr = hsotg->regs + HAINT;
1755 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
1756 (unsigned long)addr, readl(addr));
1757 addr = hsotg->regs + HAINTMSK;
1758 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
1759 (unsigned long)addr, readl(addr));
1760 if (hsotg->core_params->dma_desc_enable > 0) {
1761 addr = hsotg->regs + HFLBADDR;
1762 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
1763 (unsigned long)addr, readl(addr));
1766 addr = hsotg->regs + HPRT0;
1767 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
1768 (unsigned long)addr, readl(addr));
1770 for (i = 0; i < hsotg->core_params->host_channels; i++) {
1771 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
1772 addr = hsotg->regs + HCCHAR(i);
1773 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
1774 (unsigned long)addr, readl(addr));
1775 addr = hsotg->regs + HCSPLT(i);
1776 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
1777 (unsigned long)addr, readl(addr));
1778 addr = hsotg->regs + HCINT(i);
1779 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
1780 (unsigned long)addr, readl(addr));
1781 addr = hsotg->regs + HCINTMSK(i);
1782 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
1783 (unsigned long)addr, readl(addr));
1784 addr = hsotg->regs + HCTSIZ(i);
1785 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
1786 (unsigned long)addr, readl(addr));
1787 addr = hsotg->regs + HCDMA(i);
1788 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
1789 (unsigned long)addr, readl(addr));
1790 if (hsotg->core_params->dma_desc_enable > 0) {
1791 addr = hsotg->regs + HCDMAB(i);
1792 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
1793 (unsigned long)addr, readl(addr));
1800 * dwc2_dump_global_registers() - Prints the core global registers
1802 * @hsotg: Programming view of DWC_otg controller
1804 * NOTE: This function will be removed once the peripheral controller code
1805 * is integrated and the driver is stable
1807 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
1812 dev_dbg(hsotg->dev, "Core Global Registers\n");
1813 addr = hsotg->regs + GOTGCTL;
1814 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
1815 (unsigned long)addr, readl(addr));
1816 addr = hsotg->regs + GOTGINT;
1817 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
1818 (unsigned long)addr, readl(addr));
1819 addr = hsotg->regs + GAHBCFG;
1820 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
1821 (unsigned long)addr, readl(addr));
1822 addr = hsotg->regs + GUSBCFG;
1823 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
1824 (unsigned long)addr, readl(addr));
1825 addr = hsotg->regs + GRSTCTL;
1826 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
1827 (unsigned long)addr, readl(addr));
1828 addr = hsotg->regs + GINTSTS;
1829 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
1830 (unsigned long)addr, readl(addr));
1831 addr = hsotg->regs + GINTMSK;
1832 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
1833 (unsigned long)addr, readl(addr));
1834 addr = hsotg->regs + GRXSTSR;
1835 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
1836 (unsigned long)addr, readl(addr));
1837 addr = hsotg->regs + GRXFSIZ;
1838 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
1839 (unsigned long)addr, readl(addr));
1840 addr = hsotg->regs + GNPTXFSIZ;
1841 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
1842 (unsigned long)addr, readl(addr));
1843 addr = hsotg->regs + GNPTXSTS;
1844 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
1845 (unsigned long)addr, readl(addr));
1846 addr = hsotg->regs + GI2CCTL;
1847 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
1848 (unsigned long)addr, readl(addr));
1849 addr = hsotg->regs + GPVNDCTL;
1850 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
1851 (unsigned long)addr, readl(addr));
1852 addr = hsotg->regs + GGPIO;
1853 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
1854 (unsigned long)addr, readl(addr));
1855 addr = hsotg->regs + GUID;
1856 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
1857 (unsigned long)addr, readl(addr));
1858 addr = hsotg->regs + GSNPSID;
1859 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
1860 (unsigned long)addr, readl(addr));
1861 addr = hsotg->regs + GHWCFG1;
1862 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
1863 (unsigned long)addr, readl(addr));
1864 addr = hsotg->regs + GHWCFG2;
1865 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
1866 (unsigned long)addr, readl(addr));
1867 addr = hsotg->regs + GHWCFG3;
1868 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
1869 (unsigned long)addr, readl(addr));
1870 addr = hsotg->regs + GHWCFG4;
1871 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
1872 (unsigned long)addr, readl(addr));
1873 addr = hsotg->regs + GLPMCFG;
1874 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
1875 (unsigned long)addr, readl(addr));
1876 addr = hsotg->regs + GPWRDN;
1877 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
1878 (unsigned long)addr, readl(addr));
1879 addr = hsotg->regs + GDFIFOCFG;
1880 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
1881 (unsigned long)addr, readl(addr));
1882 addr = hsotg->regs + HPTXFSIZ;
1883 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
1884 (unsigned long)addr, readl(addr));
1886 addr = hsotg->regs + PCGCTL;
1887 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
1888 (unsigned long)addr, readl(addr));
1893 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
1895 * @hsotg: Programming view of DWC_otg controller
1896 * @num: Tx FIFO to flush
1898 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
1903 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
1905 greset = GRSTCTL_TXFFLSH;
1906 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
1907 writel(greset, hsotg->regs + GRSTCTL);
1910 greset = readl(hsotg->regs + GRSTCTL);
1911 if (++count > 10000) {
1912 dev_warn(hsotg->dev,
1913 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
1915 readl(hsotg->regs + GNPTXSTS));
1919 } while (greset & GRSTCTL_TXFFLSH);
1921 /* Wait for at least 3 PHY Clocks */
1926 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
1928 * @hsotg: Programming view of DWC_otg controller
1930 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
1935 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1937 greset = GRSTCTL_RXFFLSH;
1938 writel(greset, hsotg->regs + GRSTCTL);
1941 greset = readl(hsotg->regs + GRSTCTL);
1942 if (++count > 10000) {
1943 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
1948 } while (greset & GRSTCTL_RXFFLSH);
1950 /* Wait for at least 3 PHY Clocks */
1954 #define DWC2_PARAM_TEST(a, b, c) ((a) < (b) || (a) > (c))
1956 /* Parameter access functions */
1957 int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
1963 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
1966 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
1967 if (op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
1970 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
1972 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1973 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
1974 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
1975 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
1982 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
1993 "%d invalid for otg_cap parameter. Check HW configuration.\n",
1996 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
1997 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
1999 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2000 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2001 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2002 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2005 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2008 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2012 hsotg->core_params->otg_cap = val;
2016 int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2021 if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==
2022 GHWCFG2_SLAVE_ONLY_ARCH)
2030 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2032 val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=
2033 GHWCFG2_SLAVE_ONLY_ARCH;
2034 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2038 hsotg->core_params->dma_enable = val;
2042 int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2047 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2048 !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA)))
2056 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2058 val = (hsotg->core_params->dma_enable > 0 &&
2059 (hsotg->hwcfg4 & GHWCFG4_DESC_DMA));
2060 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2064 hsotg->core_params->dma_desc_enable = val;
2068 int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2073 if (DWC2_PARAM_TEST(val, 0, 1)) {
2076 "Wrong value for host_support_fs_low_power\n");
2078 "host_support_fs_low_power must be 0 or 1\n");
2082 "Setting host_support_fs_low_power to %d\n", val);
2086 hsotg->core_params->host_support_fs_ls_low_power = val;
2090 int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2095 if (val > 0 && !(hsotg->hwcfg2 & GHWCFG2_DYNAMIC_FIFO))
2103 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2105 val = !!(hsotg->hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
2106 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2110 hsotg->core_params->enable_dynamic_fifo = val;
2114 int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2119 if (val < 16 || val > readl(hsotg->regs + GRXFSIZ))
2125 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2127 val = readl(hsotg->regs + GRXFSIZ);
2128 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2132 hsotg->core_params->host_rx_fifo_size = val;
2136 int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2141 if (val < 16 || val > (readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff))
2147 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2149 val = readl(hsotg->regs + GNPTXFSIZ) >> 16 & 0xffff;
2150 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2155 hsotg->core_params->host_nperio_tx_fifo_size = val;
2159 int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2164 if (val < 16 || val > (hsotg->hptxfsiz >> 16))
2170 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2172 val = hsotg->hptxfsiz >> 16;
2173 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2178 hsotg->core_params->host_perio_tx_fifo_size = val;
2182 int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2186 int width = hsotg->hwcfg3 >> GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT &
2187 GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK >>
2188 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
2190 if (val < 2047 || val >= (1 << (width + 11)))
2196 "%d invalid for max_transfer_size. Check HW configuration.\n",
2198 val = (1 << (width + 11)) - 1;
2199 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2203 hsotg->core_params->max_transfer_size = val;
2207 int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2211 int width = hsotg->hwcfg3 >> GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT &
2212 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK >>
2213 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
2215 if (val < 15 || val > (1 << (width + 4)))
2221 "%d invalid for max_packet_count. Check HW configuration.\n",
2223 val = (1 << (width + 4)) - 1;
2224 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2228 hsotg->core_params->max_packet_count = val;
2232 int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2236 int num_chan = hsotg->hwcfg2 >> GHWCFG2_NUM_HOST_CHAN_SHIFT &
2237 GHWCFG2_NUM_HOST_CHAN_MASK >> GHWCFG2_NUM_HOST_CHAN_SHIFT;
2239 if (val < 1 || val > num_chan + 1)
2245 "%d invalid for host_channels. Check HW configuration.\n",
2248 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2252 hsotg->core_params->host_channels = val;
2256 int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2258 #ifndef NO_FS_PHY_HW_CHECKS
2265 if (DWC2_PARAM_TEST(val, DWC2_PHY_TYPE_PARAM_FS,
2266 DWC2_PHY_TYPE_PARAM_ULPI)) {
2268 dev_err(hsotg->dev, "Wrong value for phy_type\n");
2269 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2272 #ifndef NO_FS_PHY_HW_CHECKS
2275 val = DWC2_PHY_TYPE_PARAM_FS;
2276 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2281 #ifndef NO_FS_PHY_HW_CHECKS
2282 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
2283 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
2285 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2286 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2287 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2289 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2290 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2291 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2293 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2294 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2300 "%d invalid for phy_type. Check HW configuration.\n",
2302 val = DWC2_PHY_TYPE_PARAM_FS;
2303 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2304 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2305 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2306 val = DWC2_PHY_TYPE_PARAM_UTMI;
2308 val = DWC2_PHY_TYPE_PARAM_ULPI;
2310 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2315 hsotg->core_params->phy_type = val;
2319 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2321 return hsotg->core_params->phy_type;
2324 int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2329 if (DWC2_PARAM_TEST(val, 0, 1)) {
2331 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2332 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2337 if (val == DWC2_SPEED_PARAM_HIGH &&
2338 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2344 "%d invalid for speed parameter. Check HW configuration.\n",
2346 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2347 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2348 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2352 hsotg->core_params->speed = val;
2356 int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2361 if (DWC2_PARAM_TEST(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2362 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2365 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2367 "host_ls_low_power_phy_clk must be 0 or 1\n");
2372 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2373 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2379 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2381 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2382 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2383 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2384 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2389 hsotg->core_params->host_ls_low_power_phy_clk = val;
2393 int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2397 if (DWC2_PARAM_TEST(val, 0, 1)) {
2399 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2400 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2403 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2407 hsotg->core_params->phy_ulpi_ddr = val;
2411 int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2415 if (DWC2_PARAM_TEST(val, 0, 1)) {
2418 "Wrong value for phy_ulpi_ext_vbus\n");
2420 "phy_ulpi_ext_vbus must be 0 or 1\n");
2423 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2427 hsotg->core_params->phy_ulpi_ext_vbus = val;
2431 int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2435 if (DWC2_PARAM_TEST(val, 8, 8) && DWC2_PARAM_TEST(val, 16, 16)) {
2437 dev_err(hsotg->dev, "Wrong value for phy_utmi_width\n");
2438 dev_err(hsotg->dev, "phy_utmi_width must be 8 or 16\n");
2441 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2445 hsotg->core_params->phy_utmi_width = val;
2449 int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2453 if (DWC2_PARAM_TEST(val, 0, 1)) {
2455 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2456 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2459 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2463 hsotg->core_params->ulpi_fs_ls = val;
2467 int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2471 if (DWC2_PARAM_TEST(val, 0, 1)) {
2473 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2474 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2477 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2481 hsotg->core_params->ts_dline = val;
2485 int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2487 #ifndef NO_FS_PHY_HW_CHECKS
2492 if (DWC2_PARAM_TEST(val, 0, 1)) {
2494 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2495 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2498 #ifndef NO_FS_PHY_HW_CHECKS
2502 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2507 #ifndef NO_FS_PHY_HW_CHECKS
2508 if (val == 1 && !(hsotg->hwcfg3 & GHWCFG3_I2C))
2514 "%d invalid for i2c_enable. Check HW configuration.\n",
2516 val = !!(hsotg->hwcfg3 & GHWCFG3_I2C);
2517 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2522 hsotg->core_params->i2c_enable = val;
2526 int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2531 if (DWC2_PARAM_TEST(val, 0, 1)) {
2534 "Wrong value for en_multiple_tx_fifo,\n");
2536 "en_multiple_tx_fifo must be 0 or 1\n");
2541 if (val == 1 && !(hsotg->hwcfg4 & GHWCFG4_DED_FIFO_EN))
2547 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2549 val = !!(hsotg->hwcfg4 & GHWCFG4_DED_FIFO_EN);
2550 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2554 hsotg->core_params->en_multiple_tx_fifo = val;
2558 int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2563 if (DWC2_PARAM_TEST(val, 0, 1)) {
2566 "'%d' invalid for parameter reload_ctl\n", val);
2567 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2572 if (val == 1 && hsotg->snpsid < DWC2_CORE_REV_2_92a)
2578 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2580 val = hsotg->snpsid >= DWC2_CORE_REV_2_92a;
2581 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2585 hsotg->core_params->reload_ctl = val;
2589 int dwc2_set_param_ahb_single(struct dwc2_hsotg *hsotg, int val)
2594 if (DWC2_PARAM_TEST(val, 0, 1)) {
2597 "'%d' invalid for parameter ahb_single\n", val);
2598 dev_err(hsotg->dev, "ahb_single must be 0 or 1\n");
2603 if (val > 0 && hsotg->snpsid < DWC2_CORE_REV_2_94a)
2609 "%d invalid for parameter ahb_single. Check HW configuration.\n",
2612 dev_dbg(hsotg->dev, "Setting ahb_single to %d\n", val);
2616 hsotg->core_params->ahb_single = val;
2620 int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2624 if (DWC2_PARAM_TEST(val, 0, 1)) {
2627 "'%d' invalid for parameter otg_ver\n", val);
2629 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2632 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2636 hsotg->core_params->otg_ver = val;
2641 * This function is called during module intialization to pass module parameters
2642 * for the DWC_otg core. It returns non-0 if any parameters are invalid.
2644 int dwc2_set_parameters(struct dwc2_hsotg *hsotg,
2645 const struct dwc2_core_params *params)
2649 dev_dbg(hsotg->dev, "%s()\n", __func__);
2651 retval |= dwc2_set_param_otg_cap(hsotg, params->otg_cap);
2652 retval |= dwc2_set_param_dma_enable(hsotg, params->dma_enable);
2653 retval |= dwc2_set_param_dma_desc_enable(hsotg,
2654 params->dma_desc_enable);
2655 retval |= dwc2_set_param_host_support_fs_ls_low_power(hsotg,
2656 params->host_support_fs_ls_low_power);
2657 retval |= dwc2_set_param_enable_dynamic_fifo(hsotg,
2658 params->enable_dynamic_fifo);
2659 retval |= dwc2_set_param_host_rx_fifo_size(hsotg,
2660 params->host_rx_fifo_size);
2661 retval |= dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
2662 params->host_nperio_tx_fifo_size);
2663 retval |= dwc2_set_param_host_perio_tx_fifo_size(hsotg,
2664 params->host_perio_tx_fifo_size);
2665 retval |= dwc2_set_param_max_transfer_size(hsotg,
2666 params->max_transfer_size);
2667 retval |= dwc2_set_param_max_packet_count(hsotg,
2668 params->max_packet_count);
2669 retval |= dwc2_set_param_host_channels(hsotg, params->host_channels);
2670 retval |= dwc2_set_param_phy_type(hsotg, params->phy_type);
2671 retval |= dwc2_set_param_speed(hsotg, params->speed);
2672 retval |= dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
2673 params->host_ls_low_power_phy_clk);
2674 retval |= dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
2675 retval |= dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
2676 params->phy_ulpi_ext_vbus);
2677 retval |= dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
2678 retval |= dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
2679 retval |= dwc2_set_param_ts_dline(hsotg, params->ts_dline);
2680 retval |= dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
2681 retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg,
2682 params->en_multiple_tx_fifo);
2683 retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
2684 retval |= dwc2_set_param_ahb_single(hsotg, params->ahb_single);
2685 retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver);
2690 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
2692 return (u16)(hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103);
2695 int dwc2_check_core_status(struct dwc2_hsotg *hsotg)
2697 if (readl(hsotg->regs + GSNPSID) == 0xffffffff)
2704 * dwc2_enable_global_interrupts() - Enables the controller's Global
2705 * Interrupt in the AHB Config register
2707 * @hsotg: Programming view of DWC_otg controller
2709 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
2711 u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2713 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
2714 writel(ahbcfg, hsotg->regs + GAHBCFG);
2718 * dwc2_disable_global_interrupts() - Disables the controller's Global
2719 * Interrupt in the AHB Config register
2721 * @hsotg: Programming view of DWC_otg controller
2723 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
2725 u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
2727 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2728 writel(ahbcfg, hsotg->regs + GAHBCFG);
2731 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
2732 MODULE_AUTHOR("Synopsys, Inc.");
2733 MODULE_LICENSE("Dual BSD/GPL");