drivers/staging/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260 }
 261
 262 /**
 263  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 264  *
 265  * @hsotg: Pointer to struct dwc2_hsotg
 266  *
 267  * Must be called with interrupt disabled and spinlock held
 268  */
 269 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 270 {
 271         u32 intr;
 272
 273         /* Set status flags for the hub driver */
 274         hsotg->flags.b.port_connect_status_change = 1;
 275         hsotg->flags.b.port_connect_status = 0;
 276
 277         /*
 278          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 279          * interrupt mask and status bits and disabling subsequent host
 280          * channel interrupts.
 281          */
 282         intr = readl(hsotg->regs + GINTMSK);
 283         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 284         writel(intr, hsotg->regs + GINTMSK);
 285         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 286         writel(intr, hsotg->regs + GINTSTS);
 287
 288         /*
 289          * Turn off the vbus power only if the core has transitioned to device
 290          * mode. If still in host mode, need to keep power on to detect a
 291          * reconnection.
 292          */
 293         if (dwc2_is_device_mode(hsotg)) {
 294                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 295                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 296                         writel(0, hsotg->regs + HPRT0);
 297                 }
 298
 299                 dwc2_disable_host_interrupts(hsotg);
 300         }
 301
 302         /* Respond with an error status to all URBs in the schedule */
 303         dwc2_kill_all_urbs(hsotg);
 304
 305         if (dwc2_is_host_mode(hsotg))
 306                 /* Clean up any host channels that were in use */
 307                 dwc2_hcd_cleanup_channels(hsotg);
 308
 309         dwc2_host_disconnect(hsotg);
 310 }
 311
 312 /**
 313  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 314  *
 315  * @hsotg: Pointer to struct dwc2_hsotg
 316  */
 317 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 318 {
 319         if (hsotg->lx_state == DWC2_L2)
 320                 hsotg->flags.b.port_suspend_change = 1;
 321         else
 322                 hsotg->flags.b.port_l1_change = 1;
 323 }
 324
 325 /**
 326  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 327  *
 328  * @hsotg: Pointer to struct dwc2_hsotg
 329  *
 330  * Must be called with interrupt disabled and spinlock held
 331  */
 332 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 333 {
 334         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 335
 336         /*
 337          * The root hub should be disconnected before this function is called.
 338          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 339          * and the QH lists (via ..._hcd_endpoint_disable).
 340          */
 341
 342         /* Turn off all host-specific interrupts */
 343         dwc2_disable_host_interrupts(hsotg);
 344
 345         /* Turn off the vbus power */
 346         dev_dbg(hsotg->dev, "PortPower off\n");
 347         writel(0, hsotg->regs + HPRT0);
 348 }
 349
 350 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 351                                 struct dwc2_hcd_urb *urb, void **ep_handle,
 352                                 gfp_t mem_flags)
 353 {
 354         struct dwc2_qtd *qtd;
 355         unsigned long flags;
 356         u32 intr_mask;
 357         int retval;
 358
 359         if (!hsotg->flags.b.port_connect_status) {
 360                 /* No longer connected */
 361                 dev_err(hsotg->dev, "Not connected\n");
 362                 return -ENODEV;
 363         }
 364
 365         qtd = kzalloc(sizeof(*qtd), mem_flags);
 366         if (!qtd)
 367                 return -ENOMEM;
 368
 369         dwc2_hcd_qtd_init(qtd, urb);
 370         retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
 371                                   mem_flags);
 372         if (retval < 0) {
 373                 dev_err(hsotg->dev,
 374                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 375                         retval);
 376                 kfree(qtd);
 377                 return retval;
 378         }
 379
 380         intr_mask = readl(hsotg->regs + GINTMSK);
 381         if (!(intr_mask & GINTSTS_SOF) && retval == 0) {
 382                 enum dwc2_transaction_type tr_type;
 383
 384                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 385                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 386                         /*
 387                          * Do not schedule SG transactions until qtd has
 388                          * URB_GIVEBACK_ASAP set
 389                          */
 390                         return 0;
 391
 392                 spin_lock_irqsave(&hsotg->lock, flags);
 393                 tr_type = dwc2_hcd_select_transactions(hsotg);
 394                 if (tr_type != DWC2_TRANSACTION_NONE)
 395                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 396                 spin_unlock_irqrestore(&hsotg->lock, flags);
 397         }
 398
 399         return retval;
 400 }
 401
 402 /* Must be called with interrupt disabled and spinlock held */
 403 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 404                                 struct dwc2_hcd_urb *urb)
 405 {
 406         struct dwc2_qh *qh;
 407         struct dwc2_qtd *urb_qtd;
 408
 409         urb_qtd = urb->qtd;
 410         if (!urb_qtd) {
 411                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 412                 return -EINVAL;
 413         }
 414
 415         qh = urb_qtd->qh;
 416         if (!qh) {
 417                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 418                 return -EINVAL;
 419         }
 420
 421         urb->priv = NULL;
 422
 423         if (urb_qtd->in_process && qh->channel) {
 424                 dwc2_dump_channel_info(hsotg, qh->channel);
 425
 426                 /* The QTD is in process (it has been assigned to a channel) */
 427                 if (hsotg->flags.b.port_connect_status)
 428                         /*
 429                          * If still connected (i.e. in host mode), halt the
 430                          * channel so it can be used for other transfers. If
 431                          * no longer connected, the host registers can't be
 432                          * written to halt the channel since the core is in
 433                          * device mode.
 434                          */
 435                         dwc2_hc_halt(hsotg, qh->channel,
 436                                      DWC2_HC_XFER_URB_DEQUEUE);
 437         }
 438
 439         /*
 440          * Free the QTD and clean up the associated QH. Leave the QH in the
 441          * schedule if it has any remaining QTDs.
 442          */
 443         if (hsotg->core_params->dma_desc_enable <= 0) {
 444                 u8 in_process = urb_qtd->in_process;
 445
 446                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 447                 if (in_process) {
 448                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 449                         qh->channel = NULL;
 450                 } else if (list_empty(&qh->qtd_list)) {
 451                         dwc2_hcd_qh_unlink(hsotg, qh);
 452                 }
 453         } else {
 454                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 455         }
 456
 457         return 0;
 458 }
 459
 460 /* Must NOT be called with interrupt disabled or spinlock held */
 461 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 462                                      struct usb_host_endpoint *ep, int retry)
 463 {
 464         struct dwc2_qtd *qtd, *qtd_tmp;
 465         struct dwc2_qh *qh;
 466         unsigned long flags;
 467         int rc;
 468
 469         spin_lock_irqsave(&hsotg->lock, flags);
 470
 471         qh = ep->hcpriv;
 472         if (!qh) {
 473                 rc = -EINVAL;
 474                 goto err;
 475         }
 476
 477         while (!list_empty(&qh->qtd_list) && retry--) {
 478                 if (retry == 0) {
 479                         dev_err(hsotg->dev,
 480                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 481                         rc = -EBUSY;
 482                         goto err;
 483                 }
 484
 485                 spin_unlock_irqrestore(&hsotg->lock, flags);
 486                 usleep_range(20000, 40000);
 487                 spin_lock_irqsave(&hsotg->lock, flags);
 488                 qh = ep->hcpriv;
 489                 if (!qh) {
 490                         rc = -EINVAL;
 491                         goto err;
 492                 }
 493         }
 494
 495         dwc2_hcd_qh_unlink(hsotg, qh);
 496
 497         /* Free each QTD in the QH's QTD list */
 498         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 499                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 500
 501         ep->hcpriv = NULL;
 502         spin_unlock_irqrestore(&hsotg->lock, flags);
 503         dwc2_hcd_qh_free(hsotg, qh);
 504
 505         return 0;
 506
 507 err:
 508         ep->hcpriv = NULL;
 509         spin_unlock_irqrestore(&hsotg->lock, flags);
 510
 511         return rc;
 512 }
 513
 514 /* Must be called with interrupt disabled and spinlock held */
 515 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 516                                    struct usb_host_endpoint *ep)
 517 {
 518         struct dwc2_qh *qh = ep->hcpriv;
 519
 520         if (!qh)
 521                 return -EINVAL;
 522
 523         qh->data_toggle = DWC2_HC_PID_DATA0;
 524
 525         return 0;
 526 }
 527
 528 /*
 529  * Initializes dynamic portions of the DWC_otg HCD state
 530  *
 531  * Must be called with interrupt disabled and spinlock held
 532  */
 533 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 534 {
 535         struct dwc2_host_chan *chan, *chan_tmp;
 536         int num_channels;
 537         int i;
 538
 539         hsotg->flags.d32 = 0;
 540
 541         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 542         hsotg->non_periodic_channels = 0;
 543         hsotg->periodic_channels = 0;
 544
 545         /*
 546          * Put all channels in the free channel list and clean up channel
 547          * states
 548          */
 549         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 550                                  hc_list_entry)
 551                 list_del_init(&chan->hc_list_entry);
 552
 553         num_channels = hsotg->core_params->host_channels;
 554         for (i = 0; i < num_channels; i++) {
 555                 chan = hsotg->hc_ptr_array[i];
 556                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 557                 dwc2_hc_cleanup(hsotg, chan);
 558         }
 559
 560         /* Initialize the DWC core for host mode operation */
 561         dwc2_core_host_init(hsotg);
 562 }
 563
 564 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 565                                struct dwc2_host_chan *chan,
 566                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 567 {
 568         int hub_addr, hub_port;
 569
 570         chan->do_split = 1;
 571         chan->xact_pos = qtd->isoc_split_pos;
 572         chan->complete_split = qtd->complete_split;
 573         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 574         chan->hub_addr = (u8)hub_addr;
 575         chan->hub_port = (u8)hub_port;
 576 }
 577
 578 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 579                                struct dwc2_host_chan *chan,
 580                                struct dwc2_qtd *qtd, void *bufptr)
 581 {
 582         struct dwc2_hcd_urb *urb = qtd->urb;
 583         struct dwc2_hcd_iso_packet_desc *frame_desc;
 584
 585         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 586         case USB_ENDPOINT_XFER_CONTROL:
 587                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 588
 589                 switch (qtd->control_phase) {
 590                 case DWC2_CONTROL_SETUP:
 591                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 592                         chan->do_ping = 0;
 593                         chan->ep_is_in = 0;
 594                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 595                         if (hsotg->core_params->dma_enable > 0)
 596                                 chan->xfer_dma = urb->setup_dma;
 597                         else
 598                                 chan->xfer_buf = urb->setup_packet;
 599                         chan->xfer_len = 8;
 600                         bufptr = NULL;
 601                         break;
 602
 603                 case DWC2_CONTROL_DATA:
 604                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 605                         chan->data_pid_start = qtd->data_toggle;
 606                         break;
 607
 608                 case DWC2_CONTROL_STATUS:
 609                         /*
 610                          * Direction is opposite of data direction or IN if no
 611                          * data
 612                          */
 613                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 614                         if (urb->length == 0)
 615                                 chan->ep_is_in = 1;
 616                         else
 617                                 chan->ep_is_in =
 618                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 619                         if (chan->ep_is_in)
 620                                 chan->do_ping = 0;
 621                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 622                         chan->xfer_len = 0;
 623                         if (hsotg->core_params->dma_enable > 0)
 624                                 chan->xfer_dma = hsotg->status_buf_dma;
 625                         else
 626                                 chan->xfer_buf = hsotg->status_buf;
 627                         bufptr = NULL;
 628                         break;
 629                 }
 630                 break;
 631
 632         case USB_ENDPOINT_XFER_BULK:
 633                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 634                 break;
 635
 636         case USB_ENDPOINT_XFER_INT:
 637                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 638                 break;
 639
 640         case USB_ENDPOINT_XFER_ISOC:
 641                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 642                 if (hsotg->core_params->dma_desc_enable > 0)
 643                         break;
 644
 645                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 646                 frame_desc->status = 0;
 647
 648                 if (hsotg->core_params->dma_enable > 0) {
 649                         chan->xfer_dma = urb->dma;
 650                         chan->xfer_dma += frame_desc->offset +
 651                                         qtd->isoc_split_offset;
 652                 } else {
 653                         chan->xfer_buf = urb->buf;
 654                         chan->xfer_buf += frame_desc->offset +
 655                                         qtd->isoc_split_offset;
 656                 }
 657
 658                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 659
 660                 /* For non-dword aligned buffers */
 661                 if (hsotg->core_params->dma_enable > 0 &&
 662                     (chan->xfer_dma & 0x3))
 663                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 664                                         qtd->isoc_split_offset;
 665                 else
 666                         bufptr = NULL;
 667
 668                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 669                         if (chan->xfer_len <= 188)
 670                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 671                         else
 672                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 673                 }
 674                 break;
 675         }
 676
 677         return bufptr;
 678 }
 679
 680 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 681                                    struct dwc2_host_chan *chan, void *bufptr)
 682 {
 683         u32 buf_size;
 684
 685         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 686                 buf_size = hsotg->core_params->max_transfer_size;
 687         else
 688                 buf_size = 4096;
 689
 690         if (!qh->dw_align_buf) {
 691                 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
 692                                                       &qh->dw_align_buf_dma,
 693                                                       GFP_ATOMIC);
 694                 if (!qh->dw_align_buf)
 695                         return -ENOMEM;
 696         }
 697
 698         if (!chan->ep_is_in && chan->xfer_len) {
 699                 dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size,
 700                                         DMA_TO_DEVICE);
 701                 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len);
 702                 dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size,
 703                                            DMA_TO_DEVICE);
 704         }
 705
 706         chan->align_buf = qh->dw_align_buf_dma;
 707         return 0;
 708 }
 709
 710 /**
 711  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 712  * channel and initializes the host channel to perform the transactions. The
 713  * host channel is removed from the free list.
 714  *
 715  * @hsotg: The HCD state structure
 716  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 717  *         to a free host channel
 718  */
 719 static void dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg,
 720                                     struct dwc2_qh *qh)
 721 {
 722         struct dwc2_host_chan *chan;
 723         struct dwc2_hcd_urb *urb;
 724         struct dwc2_qtd *qtd;
 725         void *bufptr = NULL;
 726
 727         if (dbg_qh(qh))
 728                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 729
 730         if (list_empty(&qh->qtd_list)) {
 731                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 732                 return;
 733         }
 734
 735         if (list_empty(&hsotg->free_hc_list)) {
 736                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 737                 return;
 738         }
 739
 740         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 741                                 hc_list_entry);
 742
 743         /* Remove the host channel from the free list */
 744         list_del_init(&chan->hc_list_entry);
 745
 746         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 747         urb = qtd->urb;
 748         qh->channel = chan;
 749         qtd->in_process = 1;
 750
 751         /*
 752          * Use usb_pipedevice to determine device address. This address is
 753          * 0 before the SET_ADDRESS command and the correct address afterward.
 754          */
 755         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 756         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 757         chan->speed = qh->dev_speed;
 758         chan->max_packet = dwc2_max_packet(qh->maxp);
 759
 760         chan->xfer_started = 0;
 761         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 762         chan->error_state = (qtd->error_count > 0);
 763         chan->halt_on_queue = 0;
 764         chan->halt_pending = 0;
 765         chan->requests = 0;
 766
 767         /*
 768          * The following values may be modified in the transfer type section
 769          * below. The xfer_len value may be reduced when the transfer is
 770          * started to accommodate the max widths of the XferSize and PktCnt
 771          * fields in the HCTSIZn register.
 772          */
 773
 774         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 775         if (chan->ep_is_in)
 776                 chan->do_ping = 0;
 777         else
 778                 chan->do_ping = qh->ping_state;
 779
 780         chan->data_pid_start = qh->data_toggle;
 781         chan->multi_count = 1;
 782
 783         if (hsotg->core_params->dma_enable > 0) {
 784                 chan->xfer_dma = urb->dma + urb->actual_length;
 785
 786                 /* For non-dword aligned case */
 787                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 788                     (chan->xfer_dma & 0x3))
 789                         bufptr = (u8 *)urb->buf + urb->actual_length;
 790         } else {
 791                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 792         }
 793
 794         chan->xfer_len = urb->length - urb->actual_length;
 795         chan->xfer_count = 0;
 796
 797         /* Set the split attributes if required */
 798         if (qh->do_split)
 799                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 800         else
 801                 chan->do_split = 0;
 802
 803         /* Set the transfer attributes */
 804         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 805
 806         /* Non DWORD-aligned buffer case */
 807         if (bufptr) {
 808                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 809                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) {
 810                         dev_err(hsotg->dev,
 811                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 812                                 __func__);
 813                         /* Add channel back to free list */
 814                         chan->align_buf = 0;
 815                         chan->multi_count = 0;
 816                         list_add_tail(&chan->hc_list_entry,
 817                                       &hsotg->free_hc_list);
 818                         qtd->in_process = 0;
 819                         qh->channel = NULL;
 820                         return;
 821                 }
 822         } else {
 823                 chan->align_buf = 0;
 824         }
 825
 826         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 827             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 828                 /*
 829                  * This value may be modified when the transfer is started
 830                  * to reflect the actual transfer length
 831                  */
 832                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 833
 834         if (hsotg->core_params->dma_desc_enable > 0)
 835                 chan->desc_list_addr = qh->desc_list_dma;
 836
 837         dwc2_hc_init(hsotg, chan);
 838         chan->qh = qh;
 839 }
 840
 841 /**
 842  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 843  * schedule and assigns them to available host channels. Called from the HCD
 844  * interrupt handler functions.
 845  *
 846  * @hsotg: The HCD state structure
 847  *
 848  * Return: The types of new transactions that were assigned to host channels
 849  */
 850 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 851                 struct dwc2_hsotg *hsotg)
 852 {
 853         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 854         struct list_head *qh_ptr;
 855         struct dwc2_qh *qh;
 856         int num_channels;
 857
 858 #ifdef DWC2_DEBUG_SOF
 859         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 860 #endif
 861
 862         /* Process entries in the periodic ready list */
 863         qh_ptr = hsotg->periodic_sched_ready.next;
 864         while (qh_ptr != &hsotg->periodic_sched_ready) {
 865                 if (list_empty(&hsotg->free_hc_list))
 866                         break;
 867                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 868                 dwc2_assign_and_init_hc(hsotg, qh);
 869
 870                 /*
 871                  * Move the QH from the periodic ready schedule to the
 872                  * periodic assigned schedule
 873                  */
 874                 qh_ptr = qh_ptr->next;
 875                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 876                 ret_val = DWC2_TRANSACTION_PERIODIC;
 877         }
 878
 879         /*
 880          * Process entries in the inactive portion of the non-periodic
 881          * schedule. Some free host channels may not be used if they are
 882          * reserved for periodic transfers.
 883          */
 884         num_channels = hsotg->core_params->host_channels;
 885         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 886         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 887                 if (hsotg->non_periodic_channels >= num_channels -
 888                                                 hsotg->periodic_channels)
 889                         break;
 890                 if (list_empty(&hsotg->free_hc_list))
 891                         break;
 892                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 893                 dwc2_assign_and_init_hc(hsotg, qh);
 894
 895                 /*
 896                  * Move the QH from the non-periodic inactive schedule to the
 897                  * non-periodic active schedule
 898                  */
 899                 qh_ptr = qh_ptr->next;
 900                 list_move(&qh->qh_list_entry,
 901                           &hsotg->non_periodic_sched_active);
 902
 903                 if (ret_val == DWC2_TRANSACTION_NONE)
 904                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 905                 else
 906                         ret_val = DWC2_TRANSACTION_ALL;
 907
 908                 hsotg->non_periodic_channels++;
 909         }
 910
 911         return ret_val;
 912 }
 913
 914 /**
 915  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 916  * a host channel associated with either a periodic or non-periodic transfer
 917  *
 918  * @hsotg: The HCD state structure
 919  * @chan:  Host channel descriptor associated with either a periodic or
 920  *         non-periodic transfer
 921  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 922  *                     for periodic transfers or the non-periodic Tx FIFO
 923  *                     for non-periodic transfers
 924  *
 925  * Return: 1 if a request is queued and more requests may be needed to
 926  * complete the transfer, 0 if no more requests are required for this
 927  * transfer, -1 if there is insufficient space in the Tx FIFO
 928  *
 929  * This function assumes that there is space available in the appropriate
 930  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 931  * it checks whether space is available in the appropriate Tx FIFO.
 932  *
 933  * Must be called with interrupt disabled and spinlock held
 934  */
 935 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
 936                                   struct dwc2_host_chan *chan,
 937                                   u16 fifo_dwords_avail)
 938 {
 939         int retval = 0;
 940
 941         if (hsotg->core_params->dma_enable > 0) {
 942                 if (hsotg->core_params->dma_desc_enable > 0) {
 943                         if (!chan->xfer_started ||
 944                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
 945                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
 946                                 chan->qh->ping_state = 0;
 947                         }
 948                 } else if (!chan->xfer_started) {
 949                         dwc2_hc_start_transfer(hsotg, chan);
 950                         chan->qh->ping_state = 0;
 951                 }
 952         } else if (chan->halt_pending) {
 953                 /* Don't queue a request if the channel has been halted */
 954         } else if (chan->halt_on_queue) {
 955                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
 956         } else if (chan->do_ping) {
 957                 if (!chan->xfer_started)
 958                         dwc2_hc_start_transfer(hsotg, chan);
 959         } else if (!chan->ep_is_in ||
 960                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
 961                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
 962                         if (!chan->xfer_started) {
 963                                 dwc2_hc_start_transfer(hsotg, chan);
 964                                 retval = 1;
 965                         } else {
 966                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
 967                         }
 968                 } else {
 969                         retval = -1;
 970                 }
 971         } else {
 972                 if (!chan->xfer_started) {
 973                         dwc2_hc_start_transfer(hsotg, chan);
 974                         retval = 1;
 975                 } else {
 976                         retval = dwc2_hc_continue_transfer(hsotg, chan);
 977                 }
 978         }
 979
 980         return retval;
 981 }
 982
 983 /*
 984  * Processes periodic channels for the next frame and queues transactions for
 985  * these channels to the DWC_otg controller. After queueing transactions, the
 986  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
 987  * to queue as Periodic Tx FIFO or request queue space becomes available.
 988  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
 989  *
 990  * Must be called with interrupt disabled and spinlock held
 991  */
 992 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
 993 {
 994         struct list_head *qh_ptr;
 995         struct dwc2_qh *qh;
 996         u32 tx_status;
 997         u32 fspcavail;
 998         u32 gintmsk;
 999         int status;
1000         int no_queue_space = 0;
1001         int no_fifo_space = 0;
1002         u32 qspcavail;
1003
1004         if (dbg_perio())
1005                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1006
1007         tx_status = readl(hsotg->regs + HPTXSTS);
1008         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1009                     TXSTS_QSPCAVAIL_SHIFT;
1010         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1011                     TXSTS_FSPCAVAIL_SHIFT;
1012
1013         if (dbg_perio()) {
1014                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1015                          qspcavail);
1016                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1017                          fspcavail);
1018         }
1019
1020         qh_ptr = hsotg->periodic_sched_assigned.next;
1021         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1022                 tx_status = readl(hsotg->regs + HPTXSTS);
1023                 if ((tx_status & TXSTS_QSPCAVAIL_MASK) == 0) {
1024                         no_queue_space = 1;
1025                         break;
1026                 }
1027
1028                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1029                 if (!qh->channel) {
1030                         qh_ptr = qh_ptr->next;
1031                         continue;
1032                 }
1033
1034                 /* Make sure EP's TT buffer is clean before queueing qtds */
1035                 if (qh->tt_buffer_dirty) {
1036                         qh_ptr = qh_ptr->next;
1037                         continue;
1038                 }
1039
1040                 /*
1041                  * Set a flag if we're queuing high-bandwidth in slave mode.
1042                  * The flag prevents any halts to get into the request queue in
1043                  * the middle of multiple high-bandwidth packets getting queued.
1044                  */
1045                 if (hsotg->core_params->dma_enable <= 0 &&
1046                                 qh->channel->multi_count > 1)
1047                         hsotg->queuing_high_bandwidth = 1;
1048
1049                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1050                             TXSTS_FSPCAVAIL_SHIFT;
1051                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1052                 if (status < 0) {
1053                         no_fifo_space = 1;
1054                         break;
1055                 }
1056
1057                 /*
1058                  * In Slave mode, stay on the current transfer until there is
1059                  * nothing more to do or the high-bandwidth request count is
1060                  * reached. In DMA mode, only need to queue one request. The
1061                  * controller automatically handles multiple packets for
1062                  * high-bandwidth transfers.
1063                  */
1064                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1065                     qh->channel->requests == qh->channel->multi_count) {
1066                         qh_ptr = qh_ptr->next;
1067                         /*
1068                          * Move the QH from the periodic assigned schedule to
1069                          * the periodic queued schedule
1070                          */
1071                         list_move(&qh->qh_list_entry,
1072                                   &hsotg->periodic_sched_queued);
1073
1074                         /* done queuing high bandwidth */
1075                         hsotg->queuing_high_bandwidth = 0;
1076                 }
1077         }
1078
1079         if (hsotg->core_params->dma_enable <= 0) {
1080                 tx_status = readl(hsotg->regs + HPTXSTS);
1081                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1082                             TXSTS_QSPCAVAIL_SHIFT;
1083                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1084                             TXSTS_FSPCAVAIL_SHIFT;
1085                 if (dbg_perio()) {
1086                         dev_vdbg(hsotg->dev,
1087                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1088                                  qspcavail);
1089                         dev_vdbg(hsotg->dev,
1090                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1091                                  fspcavail);
1092                 }
1093
1094                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1095                     no_queue_space || no_fifo_space) {
1096                         /*
1097                          * May need to queue more transactions as the request
1098                          * queue or Tx FIFO empties. Enable the periodic Tx
1099                          * FIFO empty interrupt. (Always use the half-empty
1100                          * level to ensure that new requests are loaded as
1101                          * soon as possible.)
1102                          */
1103                         gintmsk = readl(hsotg->regs + GINTMSK);
1104                         gintmsk |= GINTSTS_PTXFEMP;
1105                         writel(gintmsk, hsotg->regs + GINTMSK);
1106                 } else {
1107                         /*
1108                          * Disable the Tx FIFO empty interrupt since there are
1109                          * no more transactions that need to be queued right
1110                          * now. This function is called from interrupt
1111                          * handlers to queue more transactions as transfer
1112                          * states change.
1113                          */
1114                         gintmsk = readl(hsotg->regs + GINTMSK);
1115                         gintmsk &= ~GINTSTS_PTXFEMP;
1116                         writel(gintmsk, hsotg->regs + GINTMSK);
1117                 }
1118         }
1119 }
1120
1121 /*
1122  * Processes active non-periodic channels and queues transactions for these
1123  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1124  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1125  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1126  * FIFO Empty interrupt is disabled.
1127  *
1128  * Must be called with interrupt disabled and spinlock held
1129  */
1130 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1131 {
1132         struct list_head *orig_qh_ptr;
1133         struct dwc2_qh *qh;
1134         u32 tx_status;
1135         u32 qspcavail;
1136         u32 fspcavail;
1137         u32 gintmsk;
1138         int status;
1139         int no_queue_space = 0;
1140         int no_fifo_space = 0;
1141         int more_to_do = 0;
1142
1143         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1144
1145         tx_status = readl(hsotg->regs + GNPTXSTS);
1146         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1147                     TXSTS_QSPCAVAIL_SHIFT;
1148         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1149                     TXSTS_FSPCAVAIL_SHIFT;
1150         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1151                  qspcavail);
1152         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1153                  fspcavail);
1154
1155         /*
1156          * Keep track of the starting point. Skip over the start-of-list
1157          * entry.
1158          */
1159         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1160                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1161         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1162
1163         /*
1164          * Process once through the active list or until no more space is
1165          * available in the request queue or the Tx FIFO
1166          */
1167         do {
1168                 tx_status = readl(hsotg->regs + GNPTXSTS);
1169                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1170                             TXSTS_QSPCAVAIL_SHIFT;
1171                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1172                         no_queue_space = 1;
1173                         break;
1174                 }
1175
1176                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1177                                 qh_list_entry);
1178                 if (!qh->channel)
1179                         goto next;
1180
1181                 /* Make sure EP's TT buffer is clean before queueing qtds */
1182                 if (qh->tt_buffer_dirty)
1183                         goto next;
1184
1185                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1186                             TXSTS_FSPCAVAIL_SHIFT;
1187                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1188
1189                 if (status > 0) {
1190                         more_to_do = 1;
1191                 } else if (status < 0) {
1192                         no_fifo_space = 1;
1193                         break;
1194                 }
1195 next:
1196                 /* Advance to next QH, skipping start-of-list entry */
1197                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1198                 if (hsotg->non_periodic_qh_ptr ==
1199                                 &hsotg->non_periodic_sched_active)
1200                         hsotg->non_periodic_qh_ptr =
1201                                         hsotg->non_periodic_qh_ptr->next;
1202         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1203
1204         if (hsotg->core_params->dma_enable <= 0) {
1205                 tx_status = readl(hsotg->regs + GNPTXSTS);
1206                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1207                             TXSTS_QSPCAVAIL_SHIFT;
1208                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1209                             TXSTS_FSPCAVAIL_SHIFT;
1210                 dev_vdbg(hsotg->dev,
1211                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1212                          qspcavail);
1213                 dev_vdbg(hsotg->dev,
1214                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1215                          fspcavail);
1216
1217                 if (more_to_do || no_queue_space || no_fifo_space) {
1218                         /*
1219                          * May need to queue more transactions as the request
1220                          * queue or Tx FIFO empties. Enable the non-periodic
1221                          * Tx FIFO empty interrupt. (Always use the half-empty
1222                          * level to ensure that new requests are loaded as
1223                          * soon as possible.)
1224                          */
1225                         gintmsk = readl(hsotg->regs + GINTMSK);
1226                         gintmsk |= GINTSTS_NPTXFEMP;
1227                         writel(gintmsk, hsotg->regs + GINTMSK);
1228                 } else {
1229                         /*
1230                          * Disable the Tx FIFO empty interrupt since there are
1231                          * no more transactions that need to be queued right
1232                          * now. This function is called from interrupt
1233                          * handlers to queue more transactions as transfer
1234                          * states change.
1235                          */
1236                         gintmsk = readl(hsotg->regs + GINTMSK);
1237                         gintmsk &= ~GINTSTS_NPTXFEMP;
1238                         writel(gintmsk, hsotg->regs + GINTMSK);
1239                 }
1240         }
1241 }
1242
1243 /**
1244  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1245  * and queues transactions for these channels to the DWC_otg controller. Called
1246  * from the HCD interrupt handler functions.
1247  *
1248  * @hsotg:   The HCD state structure
1249  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1250  *           or both)
1251  *
1252  * Must be called with interrupt disabled and spinlock held
1253  */
1254 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1255                                  enum dwc2_transaction_type tr_type)
1256 {
1257 #ifdef DWC2_DEBUG_SOF
1258         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1259 #endif
1260         /* Process host channels associated with periodic transfers */
1261         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1262              tr_type == DWC2_TRANSACTION_ALL) &&
1263             !list_empty(&hsotg->periodic_sched_assigned))
1264                 dwc2_process_periodic_channels(hsotg);
1265
1266         /* Process host channels associated with non-periodic transfers */
1267         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1268             tr_type == DWC2_TRANSACTION_ALL) {
1269                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1270                         dwc2_process_non_periodic_channels(hsotg);
1271                 } else {
1272                         /*
1273                          * Ensure NP Tx FIFO empty interrupt is disabled when
1274                          * there are no non-periodic transfers to process
1275                          */
1276                         u32 gintmsk = readl(hsotg->regs + GINTMSK);
1277
1278                         gintmsk &= ~GINTSTS_NPTXFEMP;
1279                         writel(gintmsk, hsotg->regs + GINTMSK);
1280                 }
1281         }
1282 }
1283
1284 static void dwc2_conn_id_status_change(struct work_struct *work)
1285 {
1286         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1287                                                 wf_otg);
1288         u32 count = 0;
1289         u32 gotgctl;
1290
1291         dev_dbg(hsotg->dev, "%s()\n", __func__);
1292
1293         gotgctl = readl(hsotg->regs + GOTGCTL);
1294         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1295         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1296                 !!(gotgctl & GOTGCTL_CONID_B));
1297
1298         /* B-Device connector (Device Mode) */
1299         if (gotgctl & GOTGCTL_CONID_B) {
1300                 /* Wait for switch to device mode */
1301                 dev_dbg(hsotg->dev, "connId B\n");
1302                 while (!dwc2_is_device_mode(hsotg)) {
1303                         dev_info(hsotg->dev,
1304                                  "Waiting for Peripheral Mode, Mode=%s\n",
1305                                  dwc2_is_host_mode(hsotg) ? "Host" :
1306                                  "Peripheral");
1307                         usleep_range(20000, 40000);
1308                         if (++count > 250)
1309                                 break;
1310                 }
1311                 if (count > 250)
1312                         dev_err(hsotg->dev,
1313                                 "Connection id status change timed out\n");
1314                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1315                 dwc2_core_init(hsotg, false, -1);
1316                 dwc2_enable_global_interrupts(hsotg);
1317         } else {
1318                 /* A-Device connector (Host Mode) */
1319                 dev_dbg(hsotg->dev, "connId A\n");
1320                 while (!dwc2_is_host_mode(hsotg)) {
1321                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1322                                  dwc2_is_host_mode(hsotg) ?
1323                                  "Host" : "Peripheral");
1324                         usleep_range(20000, 40000);
1325                         if (++count > 250)
1326                                 break;
1327                 }
1328                 if (count > 250)
1329                         dev_err(hsotg->dev,
1330                                 "Connection id status change timed out\n");
1331                 hsotg->op_state = OTG_STATE_A_HOST;
1332
1333                 /* Initialize the Core for Host mode */
1334                 dwc2_core_init(hsotg, false, -1);
1335                 dwc2_enable_global_interrupts(hsotg);
1336                 dwc2_hcd_start(hsotg);
1337         }
1338 }
1339
1340 static void dwc2_wakeup_detected(unsigned long data)
1341 {
1342         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1343         u32 hprt0;
1344
1345         dev_dbg(hsotg->dev, "%s()\n", __func__);
1346
1347         /*
1348          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1349          * so that OPT tests pass with all PHYs.)
1350          */
1351         hprt0 = dwc2_read_hprt0(hsotg);
1352         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1353         hprt0 &= ~HPRT0_RES;
1354         writel(hprt0, hsotg->regs + HPRT0);
1355         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1356                 readl(hsotg->regs + HPRT0));
1357
1358         dwc2_hcd_rem_wakeup(hsotg);
1359
1360         /* Change to L0 state */
1361         hsotg->lx_state = DWC2_L0;
1362 }
1363
1364 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1365 {
1366         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1367
1368         return hcd->self.b_hnp_enable;
1369 }
1370
1371 /* Must NOT be called with interrupt disabled or spinlock held */
1372 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1373 {
1374         unsigned long flags;
1375         u32 hprt0;
1376         u32 pcgctl;
1377         u32 gotgctl;
1378
1379         dev_dbg(hsotg->dev, "%s()\n", __func__);
1380
1381         spin_lock_irqsave(&hsotg->lock, flags);
1382
1383         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1384                 gotgctl = readl(hsotg->regs + GOTGCTL);
1385                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1386                 writel(gotgctl, hsotg->regs + GOTGCTL);
1387                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1388         }
1389
1390         hprt0 = dwc2_read_hprt0(hsotg);
1391         hprt0 |= HPRT0_SUSP;
1392         writel(hprt0, hsotg->regs + HPRT0);
1393
1394         /* Update lx_state */
1395         hsotg->lx_state = DWC2_L2;
1396
1397         /* Suspend the Phy Clock */
1398         pcgctl = readl(hsotg->regs + PCGCTL);
1399         pcgctl |= PCGCTL_STOPPCLK;
1400         writel(pcgctl, hsotg->regs + PCGCTL);
1401         udelay(10);
1402
1403         /* For HNP the bus must be suspended for at least 200ms */
1404         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1405                 pcgctl = readl(hsotg->regs + PCGCTL);
1406                 pcgctl &= ~PCGCTL_STOPPCLK;
1407                 writel(pcgctl, hsotg->regs + PCGCTL);
1408
1409                 spin_unlock_irqrestore(&hsotg->lock, flags);
1410
1411                 usleep_range(200000, 250000);
1412         } else {
1413                 spin_unlock_irqrestore(&hsotg->lock, flags);
1414         }
1415 }
1416
1417 /* Handles hub class-specific requests */
1418 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1419                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1420 {
1421         struct usb_hub_descriptor *hub_desc;
1422         int retval = 0;
1423         u32 hprt0;
1424         u32 port_status;
1425         u32 speed;
1426         u32 pcgctl;
1427
1428         switch (typereq) {
1429         case ClearHubFeature:
1430                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1431
1432                 switch (wvalue) {
1433                 case C_HUB_LOCAL_POWER:
1434                 case C_HUB_OVER_CURRENT:
1435                         /* Nothing required here */
1436                         break;
1437
1438                 default:
1439                         retval = -EINVAL;
1440                         dev_err(hsotg->dev,
1441                                 "ClearHubFeature request %1xh unknown\n",
1442                                 wvalue);
1443                 }
1444                 break;
1445
1446         case ClearPortFeature:
1447                 if (wvalue != USB_PORT_FEAT_L1)
1448                         if (!windex || windex > 1)
1449                                 goto error;
1450                 switch (wvalue) {
1451                 case USB_PORT_FEAT_ENABLE:
1452                         dev_dbg(hsotg->dev,
1453                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1454                         hprt0 = dwc2_read_hprt0(hsotg);
1455                         hprt0 |= HPRT0_ENA;
1456                         writel(hprt0, hsotg->regs + HPRT0);
1457                         break;
1458
1459                 case USB_PORT_FEAT_SUSPEND:
1460                         dev_dbg(hsotg->dev,
1461                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1462                         writel(0, hsotg->regs + PCGCTL);
1463                         usleep_range(20000, 40000);
1464
1465                         hprt0 = dwc2_read_hprt0(hsotg);
1466                         hprt0 |= HPRT0_RES;
1467                         writel(hprt0, hsotg->regs + HPRT0);
1468                         hprt0 &= ~HPRT0_SUSP;
1469                         usleep_range(100000, 150000);
1470
1471                         hprt0 &= ~HPRT0_RES;
1472                         writel(hprt0, hsotg->regs + HPRT0);
1473                         break;
1474
1475                 case USB_PORT_FEAT_POWER:
1476                         dev_dbg(hsotg->dev,
1477                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1478                         hprt0 = dwc2_read_hprt0(hsotg);
1479                         hprt0 &= ~HPRT0_PWR;
1480                         writel(hprt0, hsotg->regs + HPRT0);
1481                         break;
1482
1483                 case USB_PORT_FEAT_INDICATOR:
1484                         dev_dbg(hsotg->dev,
1485                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1486                         /* Port indicator not supported */
1487                         break;
1488
1489                 case USB_PORT_FEAT_C_CONNECTION:
1490                         /*
1491                          * Clears driver's internal Connect Status Change flag
1492                          */
1493                         dev_dbg(hsotg->dev,
1494                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1495                         hsotg->flags.b.port_connect_status_change = 0;
1496                         break;
1497
1498                 case USB_PORT_FEAT_C_RESET:
1499                         /* Clears driver's internal Port Reset Change flag */
1500                         dev_dbg(hsotg->dev,
1501                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1502                         hsotg->flags.b.port_reset_change = 0;
1503                         break;
1504
1505                 case USB_PORT_FEAT_C_ENABLE:
1506                         /*
1507                          * Clears the driver's internal Port Enable/Disable
1508                          * Change flag
1509                          */
1510                         dev_dbg(hsotg->dev,
1511                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1512                         hsotg->flags.b.port_enable_change = 0;
1513                         break;
1514
1515                 case USB_PORT_FEAT_C_SUSPEND:
1516                         /*
1517                          * Clears the driver's internal Port Suspend Change
1518                          * flag, which is set when resume signaling on the host
1519                          * port is complete
1520                          */
1521                         dev_dbg(hsotg->dev,
1522                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1523                         hsotg->flags.b.port_suspend_change = 0;
1524                         break;
1525
1526                 case USB_PORT_FEAT_C_PORT_L1:
1527                         dev_dbg(hsotg->dev,
1528                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1529                         hsotg->flags.b.port_l1_change = 0;
1530                         break;
1531
1532                 case USB_PORT_FEAT_C_OVER_CURRENT:
1533                         dev_dbg(hsotg->dev,
1534                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1535                         hsotg->flags.b.port_over_current_change = 0;
1536                         break;
1537
1538                 default:
1539                         retval = -EINVAL;
1540                         dev_err(hsotg->dev,
1541                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1542                                 wvalue);
1543                 }
1544                 break;
1545
1546         case GetHubDescriptor:
1547                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1548                 hub_desc = (struct usb_hub_descriptor *)buf;
1549                 hub_desc->bDescLength = 9;
1550                 hub_desc->bDescriptorType = 0x29;
1551                 hub_desc->bNbrPorts = 1;
1552                 hub_desc->wHubCharacteristics = cpu_to_le16(0x08);
1553                 hub_desc->bPwrOn2PwrGood = 1;
1554                 hub_desc->bHubContrCurrent = 0;
1555                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1556                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1557                 break;
1558
1559         case GetHubStatus:
1560                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1561                 memset(buf, 0, 4);
1562                 break;
1563
1564         case GetPortStatus:
1565                 dev_vdbg(hsotg->dev,
1566                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1567                          hsotg->flags.d32);
1568                 if (!windex || windex > 1)
1569                         goto error;
1570
1571                 port_status = 0;
1572                 if (hsotg->flags.b.port_connect_status_change)
1573                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1574                 if (hsotg->flags.b.port_enable_change)
1575                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1576                 if (hsotg->flags.b.port_suspend_change)
1577                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1578                 if (hsotg->flags.b.port_l1_change)
1579                         port_status |= USB_PORT_STAT_C_L1 << 16;
1580                 if (hsotg->flags.b.port_reset_change)
1581                         port_status |= USB_PORT_STAT_C_RESET << 16;
1582                 if (hsotg->flags.b.port_over_current_change) {
1583                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1584                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1585                 }
1586
1587                 if (!hsotg->flags.b.port_connect_status) {
1588                         /*
1589                          * The port is disconnected, which means the core is
1590                          * either in device mode or it soon will be. Just
1591                          * return 0's for the remainder of the port status
1592                          * since the port register can't be read if the core
1593                          * is in device mode.
1594                          */
1595                         *(__le32 *)buf = cpu_to_le32(port_status);
1596                         break;
1597                 }
1598
1599                 hprt0 = readl(hsotg->regs + HPRT0);
1600                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1601
1602                 if (hprt0 & HPRT0_CONNSTS)
1603                         port_status |= USB_PORT_STAT_CONNECTION;
1604                 if (hprt0 & HPRT0_ENA)
1605                         port_status |= USB_PORT_STAT_ENABLE;
1606                 if (hprt0 & HPRT0_SUSP)
1607                         port_status |= USB_PORT_STAT_SUSPEND;
1608                 if (hprt0 & HPRT0_OVRCURRACT)
1609                         port_status |= USB_PORT_STAT_OVERCURRENT;
1610                 if (hprt0 & HPRT0_RST)
1611                         port_status |= USB_PORT_STAT_RESET;
1612                 if (hprt0 & HPRT0_PWR)
1613                         port_status |= USB_PORT_STAT_POWER;
1614
1615                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1616                 if (speed == HPRT0_SPD_HIGH_SPEED)
1617                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1618                 else if (speed == HPRT0_SPD_LOW_SPEED)
1619                         port_status |= USB_PORT_STAT_LOW_SPEED;
1620
1621                 if (hprt0 & HPRT0_TSTCTL_MASK)
1622                         port_status |= USB_PORT_STAT_TEST;
1623                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1624
1625                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1626                 *(__le32 *)buf = cpu_to_le32(port_status);
1627                 break;
1628
1629         case SetHubFeature:
1630                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1631                 /* No HUB features supported */
1632                 break;
1633
1634         case SetPortFeature:
1635                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1636                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1637                         goto error;
1638
1639                 if (!hsotg->flags.b.port_connect_status) {
1640                         /*
1641                          * The port is disconnected, which means the core is
1642                          * either in device mode or it soon will be. Just
1643                          * return without doing anything since the port
1644                          * register can't be written if the core is in device
1645                          * mode.
1646                          */
1647                         break;
1648                 }
1649
1650                 switch (wvalue) {
1651                 case USB_PORT_FEAT_SUSPEND:
1652                         dev_dbg(hsotg->dev,
1653                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1654                         if (windex != hsotg->otg_port)
1655                                 goto error;
1656                         dwc2_port_suspend(hsotg, windex);
1657                         break;
1658
1659                 case USB_PORT_FEAT_POWER:
1660                         dev_dbg(hsotg->dev,
1661                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1662                         hprt0 = dwc2_read_hprt0(hsotg);
1663                         hprt0 |= HPRT0_PWR;
1664                         writel(hprt0, hsotg->regs + HPRT0);
1665                         break;
1666
1667                 case USB_PORT_FEAT_RESET:
1668                         hprt0 = dwc2_read_hprt0(hsotg);
1669                         dev_dbg(hsotg->dev,
1670                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1671                         pcgctl = readl(hsotg->regs + PCGCTL);
1672                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1673                         writel(pcgctl, hsotg->regs + PCGCTL);
1674                         /* ??? Original driver does this */
1675                         writel(0, hsotg->regs + PCGCTL);
1676
1677                         hprt0 = dwc2_read_hprt0(hsotg);
1678                         /* Clear suspend bit if resetting from suspend state */
1679                         hprt0 &= ~HPRT0_SUSP;
1680
1681                         /*
1682                          * When B-Host the Port reset bit is set in the Start
1683                          * HCD Callback function, so that the reset is started
1684                          * within 1ms of the HNP success interrupt
1685                          */
1686                         if (!dwc2_hcd_is_b_host(hsotg)) {
1687                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1688                                 dev_dbg(hsotg->dev,
1689                                         "In host mode, hprt0=%08x\n", hprt0);
1690                                 writel(hprt0, hsotg->regs + HPRT0);
1691                         }
1692
1693                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1694                         usleep_range(50000, 70000);
1695                         hprt0 &= ~HPRT0_RST;
1696                         writel(hprt0, hsotg->regs + HPRT0);
1697                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1698                         break;
1699
1700                 case USB_PORT_FEAT_INDICATOR:
1701                         dev_dbg(hsotg->dev,
1702                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1703                         /* Not supported */
1704                         break;
1705
1706                 default:
1707                         retval = -EINVAL;
1708                         dev_err(hsotg->dev,
1709                                 "SetPortFeature %1xh unknown or unsupported\n",
1710                                 wvalue);
1711                         break;
1712                 }
1713                 break;
1714
1715         default:
1716 error:
1717                 retval = -EINVAL;
1718                 dev_dbg(hsotg->dev,
1719                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1720                         typereq, windex, wvalue);
1721                 break;
1722         }
1723
1724         return retval;
1725 }
1726
1727 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1728 {
1729         int retval;
1730
1731         if (port != 1)
1732                 return -EINVAL;
1733
1734         retval = (hsotg->flags.b.port_connect_status_change ||
1735                   hsotg->flags.b.port_reset_change ||
1736                   hsotg->flags.b.port_enable_change ||
1737                   hsotg->flags.b.port_suspend_change ||
1738                   hsotg->flags.b.port_over_current_change);
1739
1740         if (retval) {
1741                 dev_dbg(hsotg->dev,
1742                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1743                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1744                         hsotg->flags.b.port_connect_status_change);
1745                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1746                         hsotg->flags.b.port_reset_change);
1747                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1748                         hsotg->flags.b.port_enable_change);
1749                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1750                         hsotg->flags.b.port_suspend_change);
1751                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1752                         hsotg->flags.b.port_over_current_change);
1753         }
1754
1755         return retval;
1756 }
1757
1758 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1759 {
1760         u32 hfnum = readl(hsotg->regs + HFNUM);
1761
1762 #ifdef DWC2_DEBUG_SOF
1763         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1764                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1765 #endif
1766         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1767 }
1768
1769 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1770 {
1771         return (hsotg->op_state == OTG_STATE_B_HOST);
1772 }
1773
1774 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1775                                                int iso_desc_count,
1776                                                gfp_t mem_flags)
1777 {
1778         struct dwc2_hcd_urb *urb;
1779         u32 size = sizeof(*urb) + iso_desc_count *
1780                    sizeof(struct dwc2_hcd_iso_packet_desc);
1781
1782         urb = kzalloc(size, mem_flags);
1783         if (urb)
1784                 urb->packet_count = iso_desc_count;
1785         return urb;
1786 }
1787
1788 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1789                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1790                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1791 {
1792         if (dbg_perio() ||
1793             ep_type == USB_ENDPOINT_XFER_BULK ||
1794             ep_type == USB_ENDPOINT_XFER_CONTROL)
1795                 dev_vdbg(hsotg->dev,
1796                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1797                          dev_addr, ep_num, ep_dir, ep_type, mps);
1798         urb->pipe_info.dev_addr = dev_addr;
1799         urb->pipe_info.ep_num = ep_num;
1800         urb->pipe_info.pipe_type = ep_type;
1801         urb->pipe_info.pipe_dir = ep_dir;
1802         urb->pipe_info.mps = mps;
1803 }
1804
1805 /*
1806  * NOTE: This function will be removed once the peripheral controller code
1807  * is integrated and the driver is stable
1808  */
1809 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1810 {
1811 #ifdef DEBUG
1812         struct dwc2_host_chan *chan;
1813         struct dwc2_hcd_urb *urb;
1814         struct dwc2_qtd *qtd;
1815         int num_channels;
1816         u32 np_tx_status;
1817         u32 p_tx_status;
1818         int i;
1819
1820         num_channels = hsotg->core_params->host_channels;
1821         dev_dbg(hsotg->dev, "\n");
1822         dev_dbg(hsotg->dev,
1823                 "************************************************************\n");
1824         dev_dbg(hsotg->dev, "HCD State:\n");
1825         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1826
1827         for (i = 0; i < num_channels; i++) {
1828                 chan = hsotg->hc_ptr_array[i];
1829                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1830                 dev_dbg(hsotg->dev,
1831                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1832                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1833                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1834                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1835                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1836                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1837                         chan->data_pid_start);
1838                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1839                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1840                         chan->xfer_started);
1841                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1842                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1843                         (unsigned long)chan->xfer_dma);
1844                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1845                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1846                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1847                         chan->halt_on_queue);
1848                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1849                         chan->halt_pending);
1850                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1851                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1852                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1853                         chan->complete_split);
1854                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1855                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1856                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1857                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1858                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1859
1860                 if (chan->xfer_started) {
1861                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1862
1863                         hfnum = readl(hsotg->regs + HFNUM);
1864                         hcchar = readl(hsotg->regs + HCCHAR(i));
1865                         hctsiz = readl(hsotg->regs + HCTSIZ(i));
1866                         hcint = readl(hsotg->regs + HCINT(i));
1867                         hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1868                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1869                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1870                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1871                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1872                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1873                 }
1874
1875                 if (!(chan->xfer_started && chan->qh))
1876                         continue;
1877
1878                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1879                         if (!qtd->in_process)
1880                                 break;
1881                         urb = qtd->urb;
1882                         dev_dbg(hsotg->dev, "    URB Info:\n");
1883                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
1884                                 qtd, urb);
1885                         if (urb) {
1886                                 dev_dbg(hsotg->dev,
1887                                         "      Dev: %d, EP: %d %s\n",
1888                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
1889                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
1890                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1891                                         "IN" : "OUT");
1892                                 dev_dbg(hsotg->dev,
1893                                         "      Max packet size: %d\n",
1894                                         dwc2_hcd_get_mps(&urb->pipe_info));
1895                                 dev_dbg(hsotg->dev,
1896                                         "      transfer_buffer: %p\n",
1897                                         urb->buf);
1898                                 dev_dbg(hsotg->dev,
1899                                         "      transfer_dma: %08lx\n",
1900                                         (unsigned long)urb->dma);
1901                                 dev_dbg(hsotg->dev,
1902                                         "      transfer_buffer_length: %d\n",
1903                                         urb->length);
1904                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
1905                                         urb->actual_length);
1906                         }
1907                 }
1908         }
1909
1910         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
1911                 hsotg->non_periodic_channels);
1912         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
1913                 hsotg->periodic_channels);
1914         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
1915         np_tx_status = readl(hsotg->regs + GNPTXSTS);
1916         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
1917                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1918         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
1919                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1920         p_tx_status = readl(hsotg->regs + HPTXSTS);
1921         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
1922                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1923         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
1924                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1925         dwc2_hcd_dump_frrem(hsotg);
1926         dwc2_dump_global_registers(hsotg);
1927         dwc2_dump_host_registers(hsotg);
1928         dev_dbg(hsotg->dev,
1929                 "************************************************************\n");
1930         dev_dbg(hsotg->dev, "\n");
1931 #endif
1932 }
1933
1934 /*
1935  * NOTE: This function will be removed once the peripheral controller code
1936  * is integrated and the driver is stable
1937  */
1938 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
1939 {
1940 #ifdef DWC2_DUMP_FRREM
1941         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
1942         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1943                 hsotg->frrem_samples, hsotg->frrem_accum,
1944                 hsotg->frrem_samples > 0 ?
1945                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
1946         dev_dbg(hsotg->dev, "\n");
1947         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
1948         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1949                 hsotg->hfnum_7_samples,
1950                 hsotg->hfnum_7_frrem_accum,
1951                 hsotg->hfnum_7_samples > 0 ?
1952                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
1953         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
1954         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1955                 hsotg->hfnum_0_samples,
1956                 hsotg->hfnum_0_frrem_accum,
1957                 hsotg->hfnum_0_samples > 0 ?
1958                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
1959         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
1960         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1961                 hsotg->hfnum_other_samples,
1962                 hsotg->hfnum_other_frrem_accum,
1963                 hsotg->hfnum_other_samples > 0 ?
1964                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
1965                 0);
1966         dev_dbg(hsotg->dev, "\n");
1967         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
1968         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1969                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
1970                 hsotg->hfnum_7_samples_a > 0 ?
1971                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
1972         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
1973         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1974                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
1975                 hsotg->hfnum_0_samples_a > 0 ?
1976                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
1977         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
1978         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1979                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
1980                 hsotg->hfnum_other_samples_a > 0 ?
1981                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
1982                 : 0);
1983         dev_dbg(hsotg->dev, "\n");
1984         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
1985         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1986                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
1987                 hsotg->hfnum_7_samples_b > 0 ?
1988                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
1989         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
1990         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1991                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
1992                 (hsotg->hfnum_0_samples_b > 0) ?
1993                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
1994         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
1995         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
1996                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
1997                 (hsotg->hfnum_other_samples_b > 0) ?
1998                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
1999                 : 0);
2000 #endif
2001 }
2002
2003 struct wrapper_priv_data {
2004         struct dwc2_hsotg *hsotg;
2005 };
2006
2007 /* Gets the dwc2_hsotg from a usb_hcd */
2008 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2009 {
2010         struct wrapper_priv_data *p;
2011
2012         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2013         return p->hsotg;
2014 }
2015
2016 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2017
2018 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2019 {
2020         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2021
2022         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2023         _dwc2_hcd_start(hcd);
2024 }
2025
2026 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2027 {
2028         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2029
2030         hcd->self.is_b_host = 0;
2031 }
2032
2033 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2034                         int *hub_port)
2035 {
2036         struct urb *urb = context;
2037
2038         if (urb->dev->tt)
2039                 *hub_addr = urb->dev->tt->hub->devnum;
2040         else
2041                 *hub_addr = 0;
2042         *hub_port = urb->dev->ttport;
2043 }
2044
2045 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2046 {
2047         struct urb *urb = context;
2048
2049         return urb->dev->speed;
2050 }
2051
2052 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2053                                         struct urb *urb)
2054 {
2055         struct usb_bus *bus = hcd_to_bus(hcd);
2056
2057         if (urb->interval)
2058                 bus->bandwidth_allocated += bw / urb->interval;
2059         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2060                 bus->bandwidth_isoc_reqs++;
2061         else
2062                 bus->bandwidth_int_reqs++;
2063 }
2064
2065 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2066                                     struct urb *urb)
2067 {
2068         struct usb_bus *bus = hcd_to_bus(hcd);
2069
2070         if (urb->interval)
2071                 bus->bandwidth_allocated -= bw / urb->interval;
2072         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2073                 bus->bandwidth_isoc_reqs--;
2074         else
2075                 bus->bandwidth_int_reqs--;
2076 }
2077
2078 /*
2079  * Sets the final status of an URB and returns it to the upper layer. Any
2080  * required cleanup of the URB is performed.
2081  *
2082  * Must be called with interrupt disabled and spinlock held
2083  */
2084 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2085                         int status)
2086 {
2087         struct urb *urb;
2088         int i;
2089
2090         if (!qtd) {
2091                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2092                 return;
2093         }
2094
2095         if (!qtd->urb) {
2096                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2097                 return;
2098         }
2099
2100         urb = qtd->urb->priv;
2101         if (!urb) {
2102                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2103                 return;
2104         }
2105
2106         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2107
2108         if (dbg_urb(urb))
2109                 dev_vdbg(hsotg->dev,
2110                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2111                          __func__, urb, usb_pipedevice(urb->pipe),
2112                          usb_pipeendpoint(urb->pipe),
2113                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2114                          urb->actual_length);
2115
2116         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2117                 for (i = 0; i < urb->number_of_packets; i++)
2118                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2119                                  i, urb->iso_frame_desc[i].status);
2120         }
2121
2122         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2123                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2124                 for (i = 0; i < urb->number_of_packets; ++i) {
2125                         urb->iso_frame_desc[i].actual_length =
2126                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2127                                                 qtd->urb, i);
2128                         urb->iso_frame_desc[i].status =
2129                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2130                 }
2131         }
2132
2133         urb->status = status;
2134         if (!status) {
2135                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2136                     urb->actual_length < urb->transfer_buffer_length)
2137                         urb->status = -EREMOTEIO;
2138         }
2139
2140         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2141             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2142                 struct usb_host_endpoint *ep = urb->ep;
2143
2144                 if (ep)
2145                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2146                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2147                                         urb);
2148         }
2149
2150         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2151         urb->hcpriv = NULL;
2152         kfree(qtd->urb);
2153         qtd->urb = NULL;
2154
2155         spin_unlock(&hsotg->lock);
2156         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2157         spin_lock(&hsotg->lock);
2158 }
2159
2160 /*
2161  * Work queue function for starting the HCD when A-Cable is connected
2162  */
2163 static void dwc2_hcd_start_func(struct work_struct *work)
2164 {
2165         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2166                                                 start_work.work);
2167
2168         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2169         dwc2_host_start(hsotg);
2170 }
2171
2172 /*
2173  * Reset work queue function
2174  */
2175 static void dwc2_hcd_reset_func(struct work_struct *work)
2176 {
2177         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2178                                                 reset_work.work);
2179         u32 hprt0;
2180
2181         dev_dbg(hsotg->dev, "USB RESET function called\n");
2182         hprt0 = dwc2_read_hprt0(hsotg);
2183         hprt0 &= ~HPRT0_RST;
2184         writel(hprt0, hsotg->regs + HPRT0);
2185         hsotg->flags.b.port_reset_change = 1;
2186 }
2187
2188 /*
2189  * =========================================================================
2190  *  Linux HC Driver Functions
2191  * =========================================================================
2192  */
2193
2194 /*
2195  * Initializes the DWC_otg controller and its root hub and prepares it for host
2196  * mode operation. Activates the root port. Returns 0 on success and a negative
2197  * error code on failure.
2198  */
2199 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2200 {
2201         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2202         struct usb_bus *bus = hcd_to_bus(hcd);
2203         unsigned long flags;
2204
2205         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2206
2207         spin_lock_irqsave(&hsotg->lock, flags);
2208
2209         hcd->state = HC_STATE_RUNNING;
2210
2211         if (dwc2_is_device_mode(hsotg)) {
2212                 spin_unlock_irqrestore(&hsotg->lock, flags);
2213                 return 0;       /* why 0 ?? */
2214         }
2215
2216         dwc2_hcd_reinit(hsotg);
2217
2218         /* Initialize and connect root hub if one is not already attached */
2219         if (bus->root_hub) {
2220                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2221                 /* Inform the HUB driver to resume */
2222                 usb_hcd_resume_root_hub(hcd);
2223         }
2224
2225         spin_unlock_irqrestore(&hsotg->lock, flags);
2226         return 0;
2227 }
2228
2229 /*
2230  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2231  * stopped.
2232  */
2233 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2234 {
2235         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2236         unsigned long flags;
2237
2238         spin_lock_irqsave(&hsotg->lock, flags);
2239         dwc2_hcd_stop(hsotg);
2240         spin_unlock_irqrestore(&hsotg->lock, flags);
2241
2242         usleep_range(1000, 3000);
2243 }
2244
2245 /* Returns the current frame number */
2246 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2247 {
2248         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2249
2250         return dwc2_hcd_get_frame_number(hsotg);
2251 }
2252
2253 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2254                                char *fn_name)
2255 {
2256 #ifdef VERBOSE_DEBUG
2257         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2258         char *pipetype;
2259         char *speed;
2260
2261         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2262         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2263                  usb_pipedevice(urb->pipe));
2264         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2265                  usb_pipeendpoint(urb->pipe),
2266                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2267
2268         switch (usb_pipetype(urb->pipe)) {
2269         case PIPE_CONTROL:
2270                 pipetype = "CONTROL";
2271                 break;
2272         case PIPE_BULK:
2273                 pipetype = "BULK";
2274                 break;
2275         case PIPE_INTERRUPT:
2276                 pipetype = "INTERRUPT";
2277                 break;
2278         case PIPE_ISOCHRONOUS:
2279                 pipetype = "ISOCHRONOUS";
2280                 break;
2281         default:
2282                 pipetype = "UNKNOWN";
2283                 break;
2284         }
2285
2286         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2287                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2288                  "IN" : "OUT");
2289
2290         switch (urb->dev->speed) {
2291         case USB_SPEED_HIGH:
2292                 speed = "HIGH";
2293                 break;
2294         case USB_SPEED_FULL:
2295                 speed = "FULL";
2296                 break;
2297         case USB_SPEED_LOW:
2298                 speed = "LOW";
2299                 break;
2300         default:
2301                 speed = "UNKNOWN";
2302                 break;
2303         }
2304
2305         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2306         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2307                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2308         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2309                  urb->transfer_buffer_length);
2310         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2311                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2312         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2313                  urb->setup_packet, (unsigned long)urb->setup_dma);
2314         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2315
2316         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2317                 int i;
2318
2319                 for (i = 0; i < urb->number_of_packets; i++) {
2320                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2321                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2322                                  urb->iso_frame_desc[i].offset,
2323                                  urb->iso_frame_desc[i].length);
2324                 }
2325         }
2326 #endif
2327 }
2328
2329 /*
2330  * Starts processing a USB transfer request specified by a USB Request Block
2331  * (URB). mem_flags indicates the type of memory allocation to use while
2332  * processing this URB.
2333  */
2334 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2335                                  gfp_t mem_flags)
2336 {
2337         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2338         struct usb_host_endpoint *ep = urb->ep;
2339         struct dwc2_hcd_urb *dwc2_urb;
2340         int i;
2341         int retval;
2342         int alloc_bandwidth = 0;
2343         u8 ep_type = 0;
2344         u32 tflags = 0;
2345         void *buf;
2346         unsigned long flags;
2347
2348         if (dbg_urb(urb)) {
2349                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2350                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2351         }
2352
2353         if (ep == NULL)
2354                 return -EINVAL;
2355
2356         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2357             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2358                 spin_lock_irqsave(&hsotg->lock, flags);
2359                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2360                         alloc_bandwidth = 1;
2361                 spin_unlock_irqrestore(&hsotg->lock, flags);
2362         }
2363
2364         switch (usb_pipetype(urb->pipe)) {
2365         case PIPE_CONTROL:
2366                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2367                 break;
2368         case PIPE_ISOCHRONOUS:
2369                 ep_type = USB_ENDPOINT_XFER_ISOC;
2370                 break;
2371         case PIPE_BULK:
2372                 ep_type = USB_ENDPOINT_XFER_BULK;
2373                 break;
2374         case PIPE_INTERRUPT:
2375                 ep_type = USB_ENDPOINT_XFER_INT;
2376                 break;
2377         default:
2378                 dev_warn(hsotg->dev, "Wrong ep type\n");
2379         }
2380
2381         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2382                                       mem_flags);
2383         if (!dwc2_urb)
2384                 return -ENOMEM;
2385
2386         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2387                                   usb_pipeendpoint(urb->pipe), ep_type,
2388                                   usb_pipein(urb->pipe),
2389                                   usb_maxpacket(urb->dev, urb->pipe,
2390                                                 !(usb_pipein(urb->pipe))));
2391
2392         buf = urb->transfer_buffer;
2393
2394         if (hcd->self.uses_dma) {
2395                 if (!buf && (urb->transfer_dma & 3)) {
2396                         dev_err(hsotg->dev,
2397                                 "%s: unaligned transfer with no transfer_buffer",
2398                                 __func__);
2399                         retval = -EINVAL;
2400                         goto fail1;
2401                 }
2402         }
2403
2404         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2405                 tflags |= URB_GIVEBACK_ASAP;
2406         if (urb->transfer_flags & URB_ZERO_PACKET)
2407                 tflags |= URB_SEND_ZERO_PACKET;
2408
2409         dwc2_urb->priv = urb;
2410         dwc2_urb->buf = buf;
2411         dwc2_urb->dma = urb->transfer_dma;
2412         dwc2_urb->length = urb->transfer_buffer_length;
2413         dwc2_urb->setup_packet = urb->setup_packet;
2414         dwc2_urb->setup_dma = urb->setup_dma;
2415         dwc2_urb->flags = tflags;
2416         dwc2_urb->interval = urb->interval;
2417         dwc2_urb->status = -EINPROGRESS;
2418
2419         for (i = 0; i < urb->number_of_packets; ++i)
2420                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2421                                                  urb->iso_frame_desc[i].offset,
2422                                                  urb->iso_frame_desc[i].length);
2423
2424         urb->hcpriv = dwc2_urb;
2425
2426         spin_lock_irqsave(&hsotg->lock, flags);
2427         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2428         spin_unlock_irqrestore(&hsotg->lock, flags);
2429         if (retval)
2430                 goto fail1;
2431
2432         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2433         if (retval)
2434                 goto fail2;
2435
2436         if (alloc_bandwidth) {
2437                 spin_lock_irqsave(&hsotg->lock, flags);
2438                 dwc2_allocate_bus_bandwidth(hcd,
2439                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2440                                 urb);
2441                 spin_unlock_irqrestore(&hsotg->lock, flags);
2442         }
2443
2444         return 0;
2445
2446 fail2:
2447         spin_lock_irqsave(&hsotg->lock, flags);
2448         dwc2_urb->priv = NULL;
2449         usb_hcd_unlink_urb_from_ep(hcd, urb);
2450         spin_unlock_irqrestore(&hsotg->lock, flags);
2451 fail1:
2452         urb->hcpriv = NULL;
2453         kfree(dwc2_urb);
2454
2455         return retval;
2456 }
2457
2458 /*
2459  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2460  */
2461 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2462                                  int status)
2463 {
2464         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2465         int rc;
2466         unsigned long flags;
2467
2468         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2469         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2470
2471         spin_lock_irqsave(&hsotg->lock, flags);
2472
2473         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2474         if (rc)
2475                 goto out;
2476
2477         if (!urb->hcpriv) {
2478                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2479                 goto out;
2480         }
2481
2482         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2483
2484         usb_hcd_unlink_urb_from_ep(hcd, urb);
2485
2486         kfree(urb->hcpriv);
2487         urb->hcpriv = NULL;
2488
2489         /* Higher layer software sets URB status */
2490         spin_unlock(&hsotg->lock);
2491         usb_hcd_giveback_urb(hcd, urb, status);
2492         spin_lock(&hsotg->lock);
2493
2494         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2495         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2496 out:
2497         spin_unlock_irqrestore(&hsotg->lock, flags);
2498
2499         return rc;
2500 }
2501
2502 /*
2503  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2504  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2505  * must already be dequeued.
2506  */
2507 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2508                                        struct usb_host_endpoint *ep)
2509 {
2510         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2511
2512         dev_dbg(hsotg->dev,
2513                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2514                 ep->desc.bEndpointAddress, ep->hcpriv);
2515         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2516 }
2517
2518 /*
2519  * Resets endpoint specific parameter values, in current version used to reset
2520  * the data toggle (as a WA). This function can be called from usb_clear_halt
2521  * routine.
2522  */
2523 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2524                                      struct usb_host_endpoint *ep)
2525 {
2526         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2527         int is_control = usb_endpoint_xfer_control(&ep->desc);
2528         int is_out = usb_endpoint_dir_out(&ep->desc);
2529         int epnum = usb_endpoint_num(&ep->desc);
2530         struct usb_device *udev;
2531         unsigned long flags;
2532
2533         dev_dbg(hsotg->dev,
2534                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2535                 ep->desc.bEndpointAddress);
2536
2537         udev = to_usb_device(hsotg->dev);
2538
2539         spin_lock_irqsave(&hsotg->lock, flags);
2540
2541         usb_settoggle(udev, epnum, is_out, 0);
2542         if (is_control)
2543                 usb_settoggle(udev, epnum, !is_out, 0);
2544         dwc2_hcd_endpoint_reset(hsotg, ep);
2545
2546         spin_unlock_irqrestore(&hsotg->lock, flags);
2547 }
2548
2549 /*
2550  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2551  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2552  * interrupt.
2553  *
2554  * This function is called by the USB core when an interrupt occurs
2555  */
2556 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2557 {
2558         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2559
2560         return dwc2_handle_hcd_intr(hsotg);
2561 }
2562
2563 /*
2564  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2565  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2566  * is the status change indicator for the single root port. Returns 1 if either
2567  * change indicator is 1, otherwise returns 0.
2568  */
2569 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2570 {
2571         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2572
2573         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2574         return buf[0] != 0;
2575 }
2576
2577 /* Handles hub class-specific requests */
2578 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2579                                  u16 windex, char *buf, u16 wlength)
2580 {
2581         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2582                                           wvalue, windex, buf, wlength);
2583         return retval;
2584 }
2585
2586 /* Handles hub TT buffer clear completions */
2587 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2588                                                struct usb_host_endpoint *ep)
2589 {
2590         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2591         struct dwc2_qh *qh;
2592         unsigned long flags;
2593
2594         qh = ep->hcpriv;
2595         if (!qh)
2596                 return;
2597
2598         spin_lock_irqsave(&hsotg->lock, flags);
2599         qh->tt_buffer_dirty = 0;
2600
2601         if (hsotg->flags.b.port_connect_status)
2602                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2603
2604         spin_unlock_irqrestore(&hsotg->lock, flags);
2605 }
2606
2607 static struct hc_driver dwc2_hc_driver = {
2608         .description = "dwc2_hsotg",
2609         .product_desc = "DWC OTG Controller",
2610         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2611
2612         .irq = _dwc2_hcd_irq,
2613         .flags = HCD_MEMORY | HCD_USB2,
2614
2615         .start = _dwc2_hcd_start,
2616         .stop = _dwc2_hcd_stop,
2617         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2618         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2619         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2620         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2621         .get_frame_number = _dwc2_hcd_get_frame_number,
2622
2623         .hub_status_data = _dwc2_hcd_hub_status_data,
2624         .hub_control = _dwc2_hcd_hub_control,
2625         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2626 };
2627
2628 /*
2629  * Frees secondary storage associated with the dwc2_hsotg structure contained
2630  * in the struct usb_hcd field
2631  */
2632 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2633 {
2634         u32 ahbcfg;
2635         u32 dctl;
2636         int i;
2637
2638         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2639
2640         /* Free memory for QH/QTD lists */
2641         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2642         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2643         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2644         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2645         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2646         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2647
2648         /* Free memory for the host channels */
2649         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2650                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2651
2652                 if (chan != NULL) {
2653                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2654                                 i, chan);
2655                         hsotg->hc_ptr_array[i] = NULL;
2656                         kfree(chan);
2657                 }
2658         }
2659
2660         if (hsotg->core_params->dma_enable > 0) {
2661                 if (hsotg->status_buf) {
2662                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2663                                           hsotg->status_buf,
2664                                           hsotg->status_buf_dma);
2665                         hsotg->status_buf = NULL;
2666                 }
2667         } else {
2668                 kfree(hsotg->status_buf);
2669                 hsotg->status_buf = NULL;
2670         }
2671
2672         ahbcfg = readl(hsotg->regs + GAHBCFG);
2673
2674         /* Disable all interrupts */
2675         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2676         writel(ahbcfg, hsotg->regs + GAHBCFG);
2677         writel(0, hsotg->regs + GINTMSK);
2678
2679         if (hsotg->snpsid >= DWC2_CORE_REV_3_00a) {
2680                 dctl = readl(hsotg->regs + DCTL);
2681                 dctl |= DCTL_SFTDISCON;
2682                 writel(dctl, hsotg->regs + DCTL);
2683         }
2684
2685         if (hsotg->wq_otg) {
2686                 if (!cancel_work_sync(&hsotg->wf_otg))
2687                         flush_workqueue(hsotg->wq_otg);
2688                 destroy_workqueue(hsotg->wq_otg);
2689         }
2690
2691         kfree(hsotg->core_params);
2692         hsotg->core_params = NULL;
2693         del_timer(&hsotg->wkp_timer);
2694 }
2695
2696 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2697 {
2698         /* Turn off all host-specific interrupts */
2699         dwc2_disable_host_interrupts(hsotg);
2700
2701         dwc2_hcd_free(hsotg);
2702 }
2703
2704 /*
2705  * Sets all parameters to the given value.
2706  *
2707  * Assumes that the dwc2_core_params struct contains only integers.
2708  */
2709 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
2710 {
2711         int *p = (int *)params;
2712         size_t size = sizeof(*params) / sizeof(*p);
2713         int i;
2714
2715         for (i = 0; i < size; i++)
2716                 p[i] = value;
2717 }
2718 EXPORT_SYMBOL_GPL(dwc2_set_all_params);
2719
2720 /*
2721  * Initializes the HCD. This function allocates memory for and initializes the
2722  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2723  * USB bus with the core and calls the hc_driver->start() function. It returns
2724  * a negative error on failure.
2725  */
2726 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
2727                   const struct dwc2_core_params *params)
2728 {
2729         struct usb_hcd *hcd;
2730         struct dwc2_host_chan *channel;
2731         u32 gusbcfg, hcfg;
2732         int i, num_channels;
2733         int retval = -ENOMEM;
2734
2735         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2736
2737         /*
2738          * Attempt to ensure this device is really a DWC_otg Controller.
2739          * Read and verify the GSNPSID register contents. The value should be
2740          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
2741          * as in "OTG version 2.xx" or "OTG version 3.xx".
2742          */
2743         hsotg->snpsid = readl(hsotg->regs + GSNPSID);
2744         if ((hsotg->snpsid & 0xfffff000) != 0x4f542000 &&
2745             (hsotg->snpsid & 0xfffff000) != 0x4f543000) {
2746                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
2747                         hsotg->snpsid);
2748                 retval = -ENODEV;
2749                 goto error1;
2750         }
2751
2752         /*
2753          * Store the contents of the hardware configuration registers here for
2754          * easy access later
2755          */
2756         hsotg->hwcfg1 = readl(hsotg->regs + GHWCFG1);
2757         hsotg->hwcfg2 = readl(hsotg->regs + GHWCFG2);
2758         hsotg->hwcfg3 = readl(hsotg->regs + GHWCFG3);
2759         hsotg->hwcfg4 = readl(hsotg->regs + GHWCFG4);
2760
2761         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hsotg->hwcfg1);
2762         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hsotg->hwcfg2);
2763         dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hsotg->hwcfg3);
2764         dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hsotg->hwcfg4);
2765
2766         /* Force host mode to get HPTXFSIZ exact power on value */
2767         gusbcfg = readl(hsotg->regs + GUSBCFG);
2768         gusbcfg |= GUSBCFG_FORCEHOSTMODE;
2769         writel(gusbcfg, hsotg->regs + GUSBCFG);
2770         usleep_range(100000, 150000);
2771
2772         hsotg->hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
2773         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hsotg->hptxfsiz);
2774         gusbcfg = readl(hsotg->regs + GUSBCFG);
2775         gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
2776         writel(gusbcfg, hsotg->regs + GUSBCFG);
2777         usleep_range(100000, 150000);
2778
2779         hcfg = readl(hsotg->regs + HCFG);
2780         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2781         dev_dbg(hsotg->dev, "op_mode=%0x\n",
2782                 hsotg->hwcfg2 >> GHWCFG2_OP_MODE_SHIFT &
2783                 GHWCFG2_OP_MODE_MASK >> GHWCFG2_OP_MODE_SHIFT);
2784         dev_dbg(hsotg->dev, "arch=%0x\n",
2785                 hsotg->hwcfg2 >> GHWCFG2_ARCHITECTURE_SHIFT &
2786                 GHWCFG2_ARCHITECTURE_MASK >> GHWCFG2_ARCHITECTURE_SHIFT);
2787         dev_dbg(hsotg->dev, "num_dev_ep=%d\n",
2788                 hsotg->hwcfg2 >> GHWCFG2_NUM_DEV_EP_SHIFT &
2789                 GHWCFG2_NUM_DEV_EP_MASK >> GHWCFG2_NUM_DEV_EP_SHIFT);
2790         dev_dbg(hsotg->dev, "max_host_chan=%d\n",
2791                 hsotg->hwcfg2 >> GHWCFG2_NUM_HOST_CHAN_SHIFT &
2792                 GHWCFG2_NUM_HOST_CHAN_MASK >> GHWCFG2_NUM_HOST_CHAN_SHIFT);
2793         dev_dbg(hsotg->dev, "nonperio_tx_q_depth=0x%0x\n",
2794                 hsotg->hwcfg2 >> GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT &
2795                 GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK >>
2796                                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT);
2797         dev_dbg(hsotg->dev, "host_perio_tx_q_depth=0x%0x\n",
2798                 hsotg->hwcfg2 >> GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT &
2799                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK >>
2800                                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT);
2801         dev_dbg(hsotg->dev, "dev_token_q_depth=0x%0x\n",
2802                 hsotg->hwcfg2 >> GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT &
2803                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK >>
2804                                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
2805
2806 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2807         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2808                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2809         if (!hsotg->frame_num_array)
2810                 goto error1;
2811         hsotg->last_frame_num_array = kzalloc(
2812                         sizeof(*hsotg->last_frame_num_array) *
2813                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2814         if (!hsotg->last_frame_num_array)
2815                 goto error1;
2816         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2817 #endif
2818
2819         hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2820         if (!hsotg->core_params)
2821                 goto error1;
2822
2823         dwc2_set_all_params(hsotg->core_params, -1);
2824
2825         /* Validate parameter values */
2826         dwc2_set_parameters(hsotg, params);
2827
2828         /* Check if the bus driver or platform code has setup a dma_mask */
2829         if (hsotg->core_params->dma_enable > 0 &&
2830             hsotg->dev->dma_mask == NULL) {
2831                 dev_warn(hsotg->dev,
2832                          "dma_mask not set, disabling DMA\n");
2833                 hsotg->core_params->dma_enable = 0;
2834                 hsotg->core_params->dma_desc_enable = 0;
2835         }
2836
2837         /* Set device flags indicating whether the HCD supports DMA */
2838         if (hsotg->core_params->dma_enable > 0) {
2839                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2840                         dev_warn(hsotg->dev, "can't set DMA mask\n");
2841                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2842                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2843         }
2844
2845         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2846         if (!hcd)
2847                 goto error1;
2848
2849         if (hsotg->core_params->dma_enable <= 0)
2850                 hcd->self.uses_dma = 0;
2851
2852         hcd->has_tt = 1;
2853
2854         spin_lock_init(&hsotg->lock);
2855         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2856         hsotg->priv = hcd;
2857
2858         /*
2859          * Disable the global interrupt until all the interrupt handlers are
2860          * installed
2861          */
2862         dwc2_disable_global_interrupts(hsotg);
2863
2864         /* Initialize the DWC_otg core, and select the Phy type */
2865         retval = dwc2_core_init(hsotg, true, irq);
2866         if (retval)
2867                 goto error2;
2868
2869         /* Create new workqueue and init work */
2870         retval = -ENOMEM;
2871         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2872         if (!hsotg->wq_otg) {
2873                 dev_err(hsotg->dev, "Failed to create workqueue\n");
2874                 goto error2;
2875         }
2876         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2877
2878         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x\n",
2879                 hsotg->snpsid >> 12 & 0xf, hsotg->snpsid >> 8 & 0xf,
2880                 hsotg->snpsid >> 4 & 0xf, hsotg->snpsid & 0xf);
2881
2882         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2883                     (unsigned long)hsotg);
2884
2885         /* Initialize the non-periodic schedule */
2886         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2887         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2888
2889         /* Initialize the periodic schedule */
2890         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2891         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2892         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2893         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2894
2895         /*
2896          * Create a host channel descriptor for each host channel implemented
2897          * in the controller. Initialize the channel descriptor array.
2898          */
2899         INIT_LIST_HEAD(&hsotg->free_hc_list);
2900         num_channels = hsotg->core_params->host_channels;
2901         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2902
2903         for (i = 0; i < num_channels; i++) {
2904                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2905                 if (channel == NULL)
2906                         goto error3;
2907                 channel->hc_num = i;
2908                 hsotg->hc_ptr_array[i] = channel;
2909         }
2910
2911         /* Initialize hsotg start work */
2912         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2913
2914         /* Initialize port reset work */
2915         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2916
2917         /*
2918          * Allocate space for storing data on status transactions. Normally no
2919          * data is sent, but this space acts as a bit bucket. This must be
2920          * done after usb_add_hcd since that function allocates the DMA buffer
2921          * pool.
2922          */
2923         if (hsotg->core_params->dma_enable > 0)
2924                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2925                                         DWC2_HCD_STATUS_BUF_SIZE,
2926                                         &hsotg->status_buf_dma, GFP_KERNEL);
2927         else
2928                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2929                                           GFP_KERNEL);
2930
2931         if (!hsotg->status_buf)
2932                 goto error3;
2933
2934         hsotg->otg_port = 1;
2935         hsotg->frame_list = NULL;
2936         hsotg->frame_list_dma = 0;
2937         hsotg->periodic_qh_count = 0;
2938
2939         /* Initiate lx_state to L3 disconnected state */
2940         hsotg->lx_state = DWC2_L3;
2941
2942         hcd->self.otg_port = hsotg->otg_port;
2943
2944         /* Don't support SG list at this point */
2945         hcd->self.sg_tablesize = 0;
2946
2947         /*
2948          * Finish generic HCD initialization and start the HCD. This function
2949          * allocates the DMA buffer pool, registers the USB bus, requests the
2950          * IRQ line, and calls hcd_start method.
2951          */
2952         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2953         if (retval < 0)
2954                 goto error3;
2955
2956         dwc2_hcd_dump_state(hsotg);
2957
2958         dwc2_enable_global_interrupts(hsotg);
2959
2960         return 0;
2961
2962 error3:
2963         dwc2_hcd_release(hsotg);
2964 error2:
2965         usb_put_hcd(hcd);
2966 error1:
2967         kfree(hsotg->core_params);
2968
2969 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2970         kfree(hsotg->last_frame_num_array);
2971         kfree(hsotg->frame_num_array);
2972 #endif
2973
2974         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2975         return retval;
2976 }
2977 EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2978
2979 /*
2980  * Removes the HCD.
2981  * Frees memory and resources associated with the HCD and deregisters the bus.
2982  */
2983 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2984 {
2985         struct usb_hcd *hcd;
2986
2987         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2988
2989         hcd = dwc2_hsotg_to_hcd(hsotg);
2990         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2991
2992         if (!hcd) {
2993                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2994                         __func__);
2995                 return;
2996         }
2997
2998         usb_remove_hcd(hcd);
2999         hsotg->priv = NULL;
3000         dwc2_hcd_release(hsotg);
3001         usb_put_hcd(hcd);
3002
3003 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3004         kfree(hsotg->last_frame_num_array);
3005         kfree(hsotg->frame_num_array);
3006 #endif
3007 }
3008 EXPORT_SYMBOL_GPL(dwc2_hcd_remove);