2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
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14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors for Host mode
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
57 * dwc2_qh_init() - Initializes a QH structure
59 * @hsotg: The HCD state structure for the DWC OTG controller
61 * @urb: Holds the information about the device/endpoint needed to initialize
64 #define SCHEDULE_SLOP 10
65 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
66 struct dwc2_hcd_urb *urb)
68 int dev_speed, hub_addr, hub_port;
71 dev_vdbg(hsotg->dev, "%s()\n", __func__);
74 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
75 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
77 qh->data_toggle = DWC2_HC_PID_DATA0;
78 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
79 INIT_LIST_HEAD(&qh->qtd_list);
80 INIT_LIST_HEAD(&qh->qh_list_entry);
82 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */
83 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
85 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
87 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
88 hub_addr != 0 && hub_addr != 1) {
90 "QH init: EP %d: TT found at hub addr %d, for port %d\n",
91 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
96 if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
97 qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
98 /* Compute scheduling parameters once and save them */
101 /* Todo: Account for split transfers in the bus time */
103 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
105 qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ?
106 USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
107 qh->ep_type == USB_ENDPOINT_XFER_ISOC,
109 /* Start in a slightly future (micro)frame */
110 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
112 qh->interval = urb->interval;
114 /* Increase interrupt polling rate for debugging */
115 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
118 hprt = readl(hsotg->regs + HPRT0);
119 prtspd = hprt & HPRT0_SPD_MASK;
120 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
121 (dev_speed == USB_SPEED_LOW ||
122 dev_speed == USB_SPEED_FULL)) {
124 qh->sched_frame |= 0x7;
125 qh->start_split_frame = qh->sched_frame;
127 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
130 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
131 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
132 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
133 dwc2_hcd_get_dev_addr(&urb->pipe_info));
134 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
135 dwc2_hcd_get_ep_num(&urb->pipe_info),
136 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
138 qh->dev_speed = dev_speed;
154 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
156 switch (qh->ep_type) {
157 case USB_ENDPOINT_XFER_ISOC:
158 type = "isochronous";
160 case USB_ENDPOINT_XFER_INT:
163 case USB_ENDPOINT_XFER_CONTROL:
166 case USB_ENDPOINT_XFER_BULK:
174 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
176 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
177 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
179 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
185 * dwc2_hcd_qh_create() - Allocates and initializes a QH
187 * @hsotg: The HCD state structure for the DWC OTG controller
188 * @urb: Holds the information about the device/endpoint needed
189 * to initialize the QH
190 * @atomic_alloc: Flag to do atomic allocation if needed
192 * Return: Pointer to the newly allocated QH, or NULL on error
194 static struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
195 struct dwc2_hcd_urb *urb,
203 /* Allocate memory */
204 qh = kzalloc(sizeof(*qh), mem_flags);
208 dwc2_qh_init(hsotg, qh, urb);
210 if (hsotg->core_params->dma_desc_enable > 0 &&
211 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
212 dwc2_hcd_qh_free(hsotg, qh);
220 * dwc2_hcd_qh_free() - Frees the QH
222 * @hsotg: HCD instance
223 * @qh: The QH to free
225 * QH should already be removed from the list. QTD list should already be empty
226 * if called from URB Dequeue.
228 * Must NOT be called with interrupt disabled or spinlock held
230 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
234 if (hsotg->core_params->dma_desc_enable > 0) {
235 dwc2_hcd_qh_free_ddma(hsotg, qh);
236 } else if (qh->dw_align_buf) {
237 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC)
240 buf_size = hsotg->core_params->max_transfer_size;
241 dma_free_coherent(hsotg->dev, buf_size, qh->dw_align_buf,
242 qh->dw_align_buf_dma);
249 * dwc2_periodic_channel_available() - Checks that a channel is available for a
252 * @hsotg: The HCD state structure for the DWC OTG controller
254 * Return: 0 if successful, negative error code otherise
256 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
259 * Currently assuming that there is a dedicated host channnel for
260 * each periodic transaction plus at least one host channel for
261 * non-periodic transactions
266 num_channels = hsotg->core_params->host_channels;
267 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
269 && hsotg->periodic_channels < num_channels - 1) {
273 "%s: Total channels: %d, Periodic: %d, "
274 "Non-periodic: %d\n", __func__, num_channels,
275 hsotg->periodic_channels, hsotg->non_periodic_channels);
283 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
284 * for the specified QH in the periodic schedule
286 * @hsotg: The HCD state structure for the DWC OTG controller
287 * @qh: QH containing periodic bandwidth required
289 * Return: 0 if successful, negative error code otherwise
291 * For simplicity, this calculation assumes that all the transfers in the
292 * periodic schedule may occur in the same (micro)frame
294 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
298 s16 max_claimed_usecs;
302 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
305 * Max periodic usecs is 80% x 125 usec = 100 usec
307 max_claimed_usecs = 100 - qh->usecs;
311 * Max periodic usecs is 90% x 1000 usec = 900 usec
313 max_claimed_usecs = 900 - qh->usecs;
316 if (hsotg->periodic_usecs > max_claimed_usecs) {
318 "%s: already claimed usecs %d, required usecs %d\n",
319 __func__, hsotg->periodic_usecs, qh->usecs);
327 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
328 * host channel is large enough to handle the maximum data transfer in a single
329 * (micro)frame for a periodic transfer
331 * @hsotg: The HCD state structure for the DWC OTG controller
332 * @qh: QH for a periodic endpoint
334 * Return: 0 if successful, negative error code otherwise
336 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
340 u32 max_channel_xfer_size;
343 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
344 max_channel_xfer_size = hsotg->core_params->max_transfer_size;
346 if (max_xfer_size > max_channel_xfer_size) {
348 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
349 __func__, max_xfer_size, max_channel_xfer_size);
357 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
358 * the periodic schedule
360 * @hsotg: The HCD state structure for the DWC OTG controller
361 * @qh: QH for the periodic transfer. The QH should already contain the
362 * scheduling information.
364 * Return: 0 if successful, negative error code otherwise
366 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
370 status = dwc2_periodic_channel_available(hsotg);
373 "%s: No host channel available for periodic transfer\n",
378 status = dwc2_check_periodic_bandwidth(hsotg, qh);
381 "%s: Insufficient periodic bandwidth for periodic transfer\n",
386 status = dwc2_check_max_xfer_size(hsotg, qh);
389 "%s: Channel max transfer size too small for periodic transfer\n",
394 if (hsotg->core_params->dma_desc_enable > 0)
395 /* Don't rely on SOF and start in ready schedule */
396 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
398 /* Always start in inactive schedule */
399 list_add_tail(&qh->qh_list_entry,
400 &hsotg->periodic_sched_inactive);
402 /* Reserve periodic channel */
403 hsotg->periodic_channels++;
405 /* Update claimed usecs per (micro)frame */
406 hsotg->periodic_usecs += qh->usecs;
412 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
413 * from the periodic schedule
415 * @hsotg: The HCD state structure for the DWC OTG controller
416 * @qh: QH for the periodic transfer
418 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
421 list_del_init(&qh->qh_list_entry);
423 /* Release periodic channel reservation */
424 hsotg->periodic_channels--;
426 /* Update claimed usecs per (micro)frame */
427 hsotg->periodic_usecs -= qh->usecs;
431 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
432 * schedule if it is not already in the schedule. If the QH is already in
433 * the schedule, no action is taken.
435 * @hsotg: The HCD state structure for the DWC OTG controller
438 * Return: 0 if successful, negative error code otherwise
440 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
446 dev_vdbg(hsotg->dev, "%s()\n", __func__);
448 if (!list_empty(&qh->qh_list_entry))
449 /* QH already in a schedule */
452 /* Add the new QH to the appropriate schedule */
453 if (dwc2_qh_is_non_per(qh)) {
454 /* Always start in inactive schedule */
455 list_add_tail(&qh->qh_list_entry,
456 &hsotg->non_periodic_sched_inactive);
458 status = dwc2_schedule_periodic(hsotg, qh);
460 if (!hsotg->periodic_qh_count) {
461 intr_mask = readl(hsotg->regs + GINTMSK);
462 intr_mask |= GINTSTS_SOF;
463 writel(intr_mask, hsotg->regs + GINTMSK);
465 hsotg->periodic_qh_count++;
473 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
474 * schedule. Memory is not freed.
476 * @hsotg: The HCD state structure
477 * @qh: QH to remove from schedule
479 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
483 dev_vdbg(hsotg->dev, "%s()\n", __func__);
485 if (list_empty(&qh->qh_list_entry))
486 /* QH is not in a schedule */
489 if (dwc2_qh_is_non_per(qh)) {
490 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
491 hsotg->non_periodic_qh_ptr =
492 hsotg->non_periodic_qh_ptr->next;
493 list_del_init(&qh->qh_list_entry);
495 dwc2_deschedule_periodic(hsotg, qh);
496 hsotg->periodic_qh_count--;
497 if (!hsotg->periodic_qh_count) {
498 intr_mask = readl(hsotg->regs + GINTMSK);
499 intr_mask &= ~GINTSTS_SOF;
500 writel(intr_mask, hsotg->regs + GINTMSK);
506 * Schedule the next continuing periodic split transfer
508 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
509 struct dwc2_qh *qh, u16 frame_number,
510 int sched_next_periodic_split)
514 if (sched_next_periodic_split) {
515 qh->sched_frame = frame_number;
516 incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
517 if (dwc2_frame_num_le(frame_number, incr)) {
519 * Allow one frame to elapse after start split
520 * microframe before scheduling complete split, but
521 * DON'T if we are doing the next start split in the
522 * same frame for an ISOC out
524 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
527 dwc2_frame_num_inc(qh->sched_frame, 1);
531 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame,
533 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
534 qh->sched_frame = frame_number;
535 qh->sched_frame |= 0x7;
536 qh->start_split_frame = qh->sched_frame;
541 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
542 * non-periodic schedule. The QH is added to the inactive non-periodic
543 * schedule if any QTDs are still attached to the QH.
545 * For periodic QHs, the QH is removed from the periodic queued schedule. If
546 * there are any QTDs still attached to the QH, the QH is added to either the
547 * periodic inactive schedule or the periodic ready schedule and its next
548 * scheduled frame is calculated. The QH is placed in the ready schedule if
549 * the scheduled frame has been reached already. Otherwise it's placed in the
550 * inactive schedule. If there are no QTDs attached to the QH, the QH is
551 * completely removed from the periodic schedule.
553 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
554 int sched_next_periodic_split)
557 dev_vdbg(hsotg->dev, "%s()\n", __func__);
559 if (dwc2_qh_is_non_per(qh)) {
560 dwc2_hcd_qh_unlink(hsotg, qh);
561 if (!list_empty(&qh->qtd_list))
562 /* Add back to inactive non-periodic schedule */
563 dwc2_hcd_qh_add(hsotg, qh);
565 u16 frame_number = dwc2_hcd_get_frame_number(hsotg);
568 dwc2_sched_periodic_split(hsotg, qh, frame_number,
569 sched_next_periodic_split);
571 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame,
573 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
574 qh->sched_frame = frame_number;
577 if (list_empty(&qh->qtd_list)) {
578 dwc2_hcd_qh_unlink(hsotg, qh);
581 * Remove from periodic_sched_queued and move to
584 if (qh->sched_frame == frame_number)
585 list_move(&qh->qh_list_entry,
586 &hsotg->periodic_sched_ready);
588 list_move(&qh->qh_list_entry,
589 &hsotg->periodic_sched_inactive);
595 * dwc2_hcd_qtd_init() - Initializes a QTD structure
597 * @qtd: The QTD to initialize
598 * @urb: The associated URB
600 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
603 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
604 USB_ENDPOINT_XFER_CONTROL) {
606 * The only time the QTD data toggle is used is on the data
607 * phase of control transfers. This phase always starts with
610 qtd->data_toggle = DWC2_HC_PID_DATA1;
611 qtd->control_phase = DWC2_CONTROL_SETUP;
615 qtd->complete_split = 0;
616 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
617 qtd->isoc_split_offset = 0;
620 /* Store the qtd ptr in the urb to reference the QTD */
625 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
627 * @hsotg: The DWC HCD structure
628 * @qtd: The QTD to add
629 * @qh: Out parameter to return queue head
630 * @atomic_alloc: Flag to do atomic alloc if needed
632 * Return: 0 if successful, negative error code otherwise
634 * Finds the correct QH to place the QTD into. If it does not find a QH, it
635 * will create a new QH. If the QH to which the QTD is added is not currently
636 * scheduled, it is placed into the proper schedule based on its EP type.
638 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
639 struct dwc2_qh **qh, gfp_t mem_flags)
641 struct dwc2_hcd_urb *urb = qtd->urb;
647 * Get the QH which holds the QTD-list to insert to. Create QH if it
651 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags);
657 spin_lock_irqsave(&hsotg->lock, flags);
659 retval = dwc2_hcd_qh_add(hsotg, *qh);
664 list_add_tail(&qtd->qtd_list_entry, &(*qh)->qtd_list);
665 spin_unlock_irqrestore(&hsotg->lock, flags);
671 struct dwc2_qtd *qtd2, *qtd2_tmp;
672 struct dwc2_qh *qh_tmp = *qh;
675 dwc2_hcd_qh_unlink(hsotg, qh_tmp);
677 /* Free each QTD in the QH's QTD list */
678 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh_tmp->qtd_list,
680 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp);
682 spin_unlock_irqrestore(&hsotg->lock, flags);
683 dwc2_hcd_qh_free(hsotg, qh_tmp);
685 spin_unlock_irqrestore(&hsotg->lock, flags);