2 * EMXX FCD (Function Controller Driver) for USB.
4 * Copyright (C) 2010 Renesas Electronics Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA.
28 /*---------------------------------------------------------------------------*/
29 /*----------------- Default undef */
32 #define UDC_DEBUG_DUMP
35 /* #define USE_INT_COUNT_OVER */
37 /*----------------- Default define */
39 #define USE_SUSPEND_WAIT 1
49 /*------------ Board dependence(Resource) */
50 #define VBUS_VALUE GPIO_VBUS
52 /* below hacked up for staging integration */
53 #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */
54 #define INT_VBUS 0 /* IRQ for GPIO_P153 */
56 /*------------ Board dependence(Wait) */
58 /* CHATTERING wait time ms */
59 #define VBUS_CHATTERING_MDELAY 1
60 /* DMA Abort wait time ms */
61 #define DMA_DISABLE_TIME 10
65 /*------------ Controller dependence */
66 #define NUM_ENDPOINTS 14 /* Endpoint */
67 #define REG_EP_NUM 15 /* Endpoint Register */
68 #define DMA_MAX_COUNT 256 /* DMA Block */
72 #define EPC_RST_DISABLE_TIME 1 /* 1 usec */
73 #define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */
74 #define EPC_PLL_LOCK_COUNT 1000 /* 1000 */
75 #define IN_DATA_EMPTY_COUNT 1000 /* 1000 */
77 #define CHATGER_TIME 700 /* 700msec */
78 #define USB_SUSPEND_TIME 2000 /* 2 sec */
87 #define BIT00 0x00000001
88 #define BIT01 0x00000002
89 #define BIT02 0x00000004
90 #define BIT03 0x00000008
91 #define BIT04 0x00000010
92 #define BIT05 0x00000020
93 #define BIT06 0x00000040
94 #define BIT07 0x00000080
95 #define BIT08 0x00000100
96 #define BIT09 0x00000200
97 #define BIT10 0x00000400
98 #define BIT11 0x00000800
99 #define BIT12 0x00001000
100 #define BIT13 0x00002000
101 #define BIT14 0x00004000
102 #define BIT15 0x00008000
103 #define BIT16 0x00010000
104 #define BIT17 0x00020000
105 #define BIT18 0x00040000
106 #define BIT19 0x00080000
107 #define BIT20 0x00100000
108 #define BIT21 0x00200000
109 #define BIT22 0x00400000
110 #define BIT23 0x00800000
111 #define BIT24 0x01000000
112 #define BIT25 0x02000000
113 #define BIT26 0x04000000
114 #define BIT27 0x08000000
115 #define BIT28 0x10000000
116 #define BIT29 0x20000000
117 #define BIT30 0x40000000
118 #define BIT31 0x80000000
121 /*------- (0x0000) USB Control Register */
122 #define USBTESTMODE (BIT18+BIT17+BIT16)
125 #define TEST_SE0_NAK (BIT17+BIT16)
126 #define TEST_PACKET BIT18
128 #define TEST_FORCE_ENABLE (BIT18+BIT16)
130 #define INT_SEL BIT10
131 #define CONSTFS BIT09
132 #define SOF_RCV BIT08
133 #define RSUM_IN BIT07
134 #define SUSPEND BIT06
136 #define DEFAULT BIT04
137 #define CONNECTB BIT03
140 #define MAX_TEST_MODE_NUM 0x05
141 #define TEST_MODE_SHIFT 16
143 /*------- (0x0004) USB Status Register */
144 #define SPEED_MODE BIT06
145 #define HIGH_SPEED BIT06
148 #define DEFAULT BIT04
149 #define USB_RST BIT03
150 #define SPND_OUT BIT02
151 #define RSUM_OUT BIT01
153 /*------- (0x0008) USB Address Register */
154 #define USB_ADDR 0x007F0000
155 #define SOF_STATUS BIT15
156 #define UFRAME (BIT14+BIT13+BIT12)
157 #define FRAME 0x000007FF
159 #define USB_ADRS_SHIFT 16
161 /*------- (0x000C) UTMI Characteristic 1 Register */
162 #define SQUSET (BIT07+BIT06+BIT05+BIT04)
164 #define USB_SQUSET (BIT06+BIT05+BIT04)
166 /*------- (0x0010) TEST Control Register */
167 #define FORCEHS BIT02
168 #define CS_TESTMODEEN BIT01
169 #define LOOPBACK BIT00
171 /*------- (0x0018) Setup Data 0 Register */
172 /*------- (0x001C) Setup Data 1 Register */
174 /*------- (0x0020) USB Interrupt Status Register */
175 #define EPn_INT 0x00FFFF00
176 #define EP15_INT BIT23
177 #define EP14_INT BIT22
178 #define EP13_INT BIT21
179 #define EP12_INT BIT20
180 #define EP11_INT BIT19
181 #define EP10_INT BIT18
182 #define EP9_INT BIT17
183 #define EP8_INT BIT16
184 #define EP7_INT BIT15
185 #define EP6_INT BIT14
186 #define EP5_INT BIT13
187 #define EP4_INT BIT12
188 #define EP3_INT BIT11
189 #define EP2_INT BIT10
190 #define EP1_INT BIT09
191 #define EP0_INT BIT08
192 #define SPEED_MODE_INT BIT06
193 #define SOF_ERROR_INT BIT05
194 #define SOF_INT BIT04
195 #define USB_RST_INT BIT03
196 #define SPND_INT BIT02
197 #define RSUM_INT BIT01
199 #define USB_INT_STA_RW 0x7E
201 /*------- (0x0024) USB Interrupt Enable Register */
202 #define EP15_0_EN 0x00FFFF00
203 #define EP15_EN BIT23
204 #define EP14_EN BIT22
205 #define EP13_EN BIT21
206 #define EP12_EN BIT20
207 #define EP11_EN BIT19
208 #define EP10_EN BIT18
219 #define SPEED_MODE_EN BIT06
220 #define SOF_ERROR_EN BIT05
222 #define USB_RST_EN BIT03
223 #define SPND_EN BIT02
224 #define RSUM_EN BIT01
226 #define USB_INT_EN_BIT \
227 (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN)
229 /*------- (0x0028) EP0 Control Register */
230 #define EP0_STGSEL BIT18
231 #define EP0_OVERSEL BIT17
232 #define EP0_AUTO BIT16
233 #define EP0_PIDCLR BIT09
234 #define EP0_BCLR BIT08
235 #define EP0_DEND BIT07
236 #define EP0_DW (BIT06+BIT05)
238 #define EP0_DW3 (BIT06+BIT05)
239 #define EP0_DW2 BIT06
240 #define EP0_DW1 BIT05
242 #define EP0_INAK_EN BIT04
243 #define EP0_PERR_NAK_CLR BIT03
244 #define EP0_STL BIT02
245 #define EP0_INAK BIT01
246 #define EP0_ONAK BIT00
248 /*------- (0x002C) EP0 Status Register */
249 #define EP0_PID BIT18
250 #define EP0_PERR_NAK BIT17
251 #define EP0_PERR_NAK_INT BIT16
252 #define EP0_OUT_NAK_INT BIT15
253 #define EP0_OUT_NULL BIT14
254 #define EP0_OUT_FULL BIT13
255 #define EP0_OUT_EMPTY BIT12
256 #define EP0_IN_NAK_INT BIT11
257 #define EP0_IN_DATA BIT10
258 #define EP0_IN_FULL BIT09
259 #define EP0_IN_EMPTY BIT08
260 #define EP0_OUT_NULL_INT BIT07
261 #define EP0_OUT_OR_INT BIT06
262 #define EP0_OUT_INT BIT05
263 #define EP0_IN_INT BIT04
264 #define EP0_STALL_INT BIT03
265 #define STG_END_INT BIT02
266 #define STG_START_INT BIT01
267 #define SETUP_INT BIT00
269 #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)
271 /*------- (0x0030) EP0 Interrupt Enable Register */
272 #define EP0_PERR_NAK_EN BIT16
273 #define EP0_OUT_NAK_EN BIT15
275 #define EP0_IN_NAK_EN BIT11
277 #define EP0_OUT_NULL_EN BIT07
278 #define EP0_OUT_OR_EN BIT06
279 #define EP0_OUT_EN BIT05
280 #define EP0_IN_EN BIT04
281 #define EP0_STALL_EN BIT03
282 #define STG_END_EN BIT02
283 #define STG_START_EN BIT01
284 #define SETUP_EN BIT00
286 #define EP0_INT_EN_BIT \
287 (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN)
289 /*------- (0x0034) EP0 Length Register */
290 #define EP0_LDATA 0x0000007F
292 /*------- (0x0038) EP0 Read Register */
293 /*------- (0x003C) EP0 Write Register */
295 /*------- (0x0040:) EPn Control Register */
297 #define EPn_BUF_TYPE BIT30
298 #define EPn_BUF_SINGLE BIT30
300 #define EPn_DIR0 BIT26
301 #define EPn_MODE (BIT25+BIT24)
303 #define EPn_INTERRUPT BIT24
304 #define EPn_ISO BIT25
306 #define EPn_OVERSEL BIT17
307 #define EPn_AUTO BIT16
309 #define EPn_IPIDCLR BIT11
310 #define EPn_OPIDCLR BIT10
311 #define EPn_BCLR BIT09
312 #define EPn_CBCLR BIT08
313 #define EPn_DEND BIT07
314 #define EPn_DW (BIT06+BIT05)
316 #define EPn_DW3 (BIT06+BIT05)
317 #define EPn_DW2 BIT06
318 #define EPn_DW1 BIT05
320 #define EPn_OSTL_EN BIT04
321 #define EPn_ISTL BIT03
322 #define EPn_OSTL BIT02
324 #define EPn_ONAK BIT00
326 /*------- (0x0044:) EPn Status Register */
327 #define EPn_ISO_PIDERR BIT29 /* R */
328 #define EPn_OPID BIT28 /* R */
329 #define EPn_OUT_NOTKN BIT27 /* R */
330 #define EPn_ISO_OR BIT26 /* R */
332 #define EPn_ISO_CRC BIT24 /* R */
333 #define EPn_OUT_END_INT BIT23 /* RW */
334 #define EPn_OUT_OR_INT BIT22 /* RW */
335 #define EPn_OUT_NAK_ERR_INT BIT21 /* RW */
336 #define EPn_OUT_STALL_INT BIT20 /* RW */
337 #define EPn_OUT_INT BIT19 /* RW */
338 #define EPn_OUT_NULL_INT BIT18 /* RW */
339 #define EPn_OUT_FULL BIT17 /* R */
340 #define EPn_OUT_EMPTY BIT16 /* R */
342 #define EPn_IPID BIT10 /* R */
343 #define EPn_IN_NOTKN BIT09 /* R */
344 #define EPn_ISO_UR BIT08 /* R */
345 #define EPn_IN_END_INT BIT07 /* RW */
347 #define EPn_IN_NAK_ERR_INT BIT05 /* RW */
348 #define EPn_IN_STALL_INT BIT04 /* RW */
349 #define EPn_IN_INT BIT03 /* RW */
350 #define EPn_IN_DATA BIT02 /* R */
351 #define EPn_IN_FULL BIT01 /* R */
352 #define EPn_IN_EMPTY BIT00 /* R */
355 (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT)
357 /*------- (0x0048:) EPn Interrupt Enable Register */
358 #define EPn_OUT_END_EN BIT23 /* RW */
359 #define EPn_OUT_OR_EN BIT22 /* RW */
360 #define EPn_OUT_NAK_ERR_EN BIT21 /* RW */
361 #define EPn_OUT_STALL_EN BIT20 /* RW */
362 #define EPn_OUT_EN BIT19 /* RW */
363 #define EPn_OUT_NULL_EN BIT18 /* RW */
365 #define EPn_IN_END_EN BIT07 /* RW */
367 #define EPn_IN_NAK_ERR_EN BIT05 /* RW */
368 #define EPn_IN_STALL_EN BIT04 /* RW */
369 #define EPn_IN_EN BIT03 /* RW */
371 /*------- (0x004C:) EPn Interrupt Enable Register */
372 #define EPn_STOP_MODE BIT11
373 #define EPn_DEND_SET BIT10
374 #define EPn_BURST_SET BIT09
375 #define EPn_STOP_SET BIT08
377 #define EPn_DMA_EN BIT04
379 #define EPn_DMAMODE0 BIT00
381 /*------- (0x0050:) EPn MaxPacket & BaseAddress Register */
382 #define EPn_BASEAD 0x1FFF0000
383 #define EPn_MPKT 0x000007FF
385 /*------- (0x0054:) EPn Length & DMA Count Register */
386 #define EPn_DMACNT 0x01FF0000
387 #define EPn_LDATA 0x000007FF
389 /*------- (0x0058:) EPn Read Register */
390 /*------- (0x005C:) EPn Write Register */
392 /*------- (0x1000) AHBSCTR Register */
393 #define WAIT_MODE BIT00
395 /*------- (0x1004) AHBMCTR Register */
396 #define ARBITER_CTR BIT31 /* RW */
397 #define MCYCLE_RST BIT12 /* RW */
399 #define ENDIAN_CTR (BIT09+BIT08) /* RW */
400 #define ENDIAN_BYTE_SWAP BIT09
401 #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR
403 #define HBUSREQ_MODE BIT05 /* RW */
404 #define HTRANS_MODE BIT04 /* RW */
406 #define WBURST_TYPE BIT02 /* RW */
407 #define BURST_TYPE (BIT01+BIT00) /* RW */
408 #define BURST_MAX_16 0
409 #define BURST_MAX_8 BIT00
410 #define BURST_MAX_4 BIT01
411 #define BURST_SINGLE BURST_TYPE
413 /*------- (0x1008) AHBBINT Register */
414 #define DMA_ENDINT 0xFFFE0000 /* RW */
416 #define AHB_VBUS_INT BIT13 /* RW */
418 #define MBUS_ERRINT BIT06 /* RW */
420 #define SBUS_ERRINT0 BIT04 /* RW */
421 #define ERR_MASTER 0x0000000F /* R */
423 /*------- (0x100C) AHBBINTEN Register */
424 #define DMA_ENDINTEN 0xFFFE0000 /* RW */
426 #define VBUS_INTEN BIT13 /* RW */
428 #define MBUS_ERRINTEN BIT06 /* RW */
430 #define SBUS_ERRINT0EN BIT04 /* RW */
432 /*------- (0x1010) EPCTR Register */
433 #define DIRPD BIT12 /* RW */
435 #define VBUS_LEVEL BIT08 /* R */
437 #define PLL_RESUME BIT05 /* RW */
438 #define PLL_LOCK BIT04 /* R */
440 #define EPC_RST BIT00 /* RW */
442 /*------- (0x1014) USBF_EPTEST Register */
443 #define LINESTATE (BIT09+BIT08) /* R */
444 #define DM_LEVEL BIT09 /* R */
445 #define DP_LEVEL BIT08 /* R */
447 #define PHY_TST BIT01 /* RW */
448 #define PHY_TSTCLK BIT00 /* RW */
450 /*------- (0x1020) USBSSVER Register */
451 #define AHBB_VER 0x00FF0000 /* R */
452 #define EPC_VER 0x0000FF00 /* R */
453 #define SS_VER 0x000000FF /* R */
455 /*------- (0x1024) USBSSCONF Register */
456 #define EP_AVAILABLE 0xFFFF0000 /* R */
457 #define DMA_AVAILABLE 0x0000FFFF /* R */
459 /*------- (0x1110:) EPnDCR1 Register */
460 #define DCR1_EPn_DMACNT 0x00FF0000 /* RW */
462 #define DCR1_EPn_DIR0 BIT01 /* RW */
463 #define DCR1_EPn_REQEN BIT00 /* RW */
465 /*------- (0x1114:) EPnDCR2 Register */
466 #define DCR2_EPn_LMPKT 0x07FF0000 /* RW */
468 #define DCR2_EPn_MPKT 0x000007FF /* RW */
470 /*------- (0x1118:) EPnTADR Register */
471 #define EPn_TADR 0xFFFFFFFF /* RW */
475 /*===========================================================================*/
479 u32 EP_CONTROL; /* EP Control */
480 u32 EP_STATUS; /* EP Status */
481 u32 EP_INT_ENA; /* EP Interrupt Enable */
482 u32 EP_DMA_CTRL; /* EP DMA Control */
483 u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */
484 u32 EP_LEN_DCNT; /* EP Length & DMA count */
485 u32 EP_READ; /* EP Read */
486 u32 EP_WRITE; /* EP Write */
491 u32 EP_DCR1; /* EP_DCR1 */
492 u32 EP_DCR2; /* EP_DCR2 */
493 u32 EP_TADR; /* EP_TADR */
494 u32 Reserved; /* Reserved */
497 /*------- Function Registers */
499 u32 USB_CONTROL; /* (0x0000) USB Control */
500 u32 USB_STATUS; /* (0x0004) USB Status */
501 u32 USB_ADDRESS; /* (0x0008) USB Address */
502 u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */
503 u32 TEST_CONTROL; /* (0x0010) TEST Control */
504 u32 Reserved_14; /* (0x0014) Reserved */
505 u32 SETUP_DATA0; /* (0x0018) Setup Data0 */
506 u32 SETUP_DATA1; /* (0x001C) Setup Data1 */
507 u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */
508 u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */
509 u32 EP0_CONTROL; /* (0x0028) EP0 Control */
510 u32 EP0_STATUS; /* (0x002C) EP0 Status */
511 u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */
512 u32 EP0_LENGTH; /* (0x0034) EP0 Length */
513 u32 EP0_READ; /* (0x0038) EP0 Read */
514 u32 EP0_WRITE; /* (0x003C) EP0 Write */
516 struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */
518 u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */
520 u32 AHBSCTR; /* (0x1000) AHBSCTR */
521 u32 AHBMCTR; /* (0x1004) AHBMCTR */
522 u32 AHBBINT; /* (0x1008) AHBBINT */
523 u32 AHBBINTEN; /* (0x100C) AHBBINTEN */
524 u32 EPCTR; /* (0x1010) EPCTR */
525 u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */
527 u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */
529 u32 USBSSVER; /* (0x1020) USBSSVER */
530 u32 USBSSCONF; /* (0x1024) USBSSCONF */
532 u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */
534 struct ep_dcr EP_DCR[REG_EP_NUM]; /* */
536 u8 Reserved1200[0x1000-0x200]; /* Reserved */
546 #define EP0_PACKETSIZE 64
547 #define EP_PACKETSIZE 1024
550 #define D_RAM_SIZE_CTRL 64
552 /* EPn Bulk Endpoint Max Packet Size */
553 #define D_FS_RAM_SIZE_BULK 64
554 #define D_HS_RAM_SIZE_BULK 512
565 EP0_OUT_STATUS_PAHSE,
572 struct usb_request req;
573 struct list_head queue;
586 struct list_head queue;
588 struct nbu2ss_udc *udc;
590 const struct usb_endpoint_descriptor *desc;
606 struct usb_gadget gadget;
607 struct usb_gadget_driver *driver;
608 struct platform_device *pdev;
611 struct completion *pdone;
613 enum ep0_state ep0state;
614 enum usb_device_state devstate;
615 struct usb_ctrlrequest ctrl;
616 struct nbu2ss_req ep0_req;
617 u8 ep0_buf[EP0_PACKETSIZE];
619 struct nbu2ss_ep ep[NUM_ENDPOINTS];
621 unsigned softconnect:1;
622 unsigned vbus_active:1;
623 unsigned linux_suspended:1;
624 unsigned linux_resume:1;
625 unsigned usb_suspended:1;
626 unsigned remote_wakeup:1;
627 unsigned udc_enabled:1;
631 u32 curr_config; /* Current Configuration Number */
633 struct fc_regs *p_regs;
636 /* USB register access structure */
637 union usb_reg_access {
639 unsigned char DATA[4];
644 /*-------------------------------------------------------------------------*/
646 #endif /* _LINUX_EMXX_H */