3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_address_map.h - Contains the register mapping for the ET1310
13 *------------------------------------------------------------------------------
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58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
92 * Interrupt status reg at address 0x0018
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
115 * Same masks as above
119 * Software reset reg at address 0x0028
125 * 5: mac_stat_sw_reset
131 * SLV Timer reg at address 0x002C (low 24 bits)
135 * MSI Configuration reg at address 0x0030
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
142 * Loopback reg located at address 0x0034
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
152 struct global_regs { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
171 /* START OF TXDMA REGISTER ADDRESS MAP */
174 * txdma control status reg at address 0x1000
177 #define ET_TXDMA_CSR_HALT 0x00000001
178 #define ET_TXDMA_DROP_TLP 0x00000002
179 #define ET_TXDMA_CACHE_THRS 0x000000F0
180 #define ET_TXDMA_CACHE_SHIFT 4
181 #define ET_TXDMA_SNGL_EPKT 0x00000100
182 #define ET_TXDMA_CLASS 0x00001E00
185 * structure for txdma packet ring base address hi reg in txdma address map
186 * located at address 0x1004
187 * Defined earlier (u32)
191 * structure for txdma packet ring base address low reg in txdma address map
192 * located at address 0x1008
193 * Defined earlier (u32)
197 * structure for txdma packet ring number of descriptor reg in txdma address
198 * map. Located at address 0x100C
204 #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
205 #define ET_DMA12_WRAP 0x1000
206 #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x0400
208 #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x0010
211 #define INDEX12(x) ((x) & ET_DMA12_MASK)
212 #define INDEX10(x) ((x) & ET_DMA10_MASK)
213 #define INDEX4(x) ((x) & ET_DMA4_MASK)
215 extern inline void add_10bit(u32 *v, int n)
217 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
220 extern inline void add_12bit(u32 *v, int n)
222 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
226 * 10bit DMA with wrap
227 * txdma tx queue write address reg in txdma address map at 0x1010
228 * txdma tx queue write address external reg in txdma address map at 0x1014
229 * txdma tx queue read address reg in txdma address map at 0x1018
232 * txdma status writeback address hi reg in txdma address map at0x101C
233 * txdma status writeback address lo reg in txdma address map at 0x1020
235 * 10bit DMA with wrap
236 * txdma service request reg in txdma address map at 0x1024
237 * structure for txdma service complete reg in txdma address map at 0x1028
240 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
241 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
243 * txdma error reg in txdma address map at address 0x1034
253 * Tx DMA Module of JAGCore Address Mapping
254 * Located at address 0x1000
256 struct txdma_regs { /* Location: */
257 u32 csr; /* 0x1000 */
258 u32 pr_base_hi; /* 0x1004 */
259 u32 pr_base_lo; /* 0x1008 */
260 u32 pr_num_des; /* 0x100C */
261 u32 txq_wr_addr; /* 0x1010 */
262 u32 txq_wr_addr_ext; /* 0x1014 */
263 u32 txq_rd_addr; /* 0x1018 */
264 u32 dma_wb_base_hi; /* 0x101C */
265 u32 dma_wb_base_lo; /* 0x1020 */
266 u32 service_request; /* 0x1024 */
267 u32 service_complete; /* 0x1028 */
268 u32 cache_rd_index; /* 0x102C */
269 u32 cache_wr_index; /* 0x1030 */
270 u32 TxDmaError; /* 0x1034 */
271 u32 DescAbortCount; /* 0x1038 */
272 u32 PayloadAbortCnt; /* 0x103c */
273 u32 WriteBackAbortCnt; /* 0x1040 */
274 u32 DescTimeoutCnt; /* 0x1044 */
275 u32 PayloadTimeoutCnt; /* 0x1048 */
276 u32 WriteBackTimeoutCnt; /* 0x104c */
277 u32 DescErrorCount; /* 0x1050 */
278 u32 PayloadErrorCnt; /* 0x1054 */
279 u32 WriteBackErrorCnt; /* 0x1058 */
280 u32 DroppedTLPCount; /* 0x105c */
281 u32 NewServiceComplete; /* 0x1060 */
282 u32 EthernetPacketCount; /* 0x1064 */
285 /* END OF TXDMA REGISTER ADDRESS MAP */
288 /* START OF RXDMA REGISTER ADDRESS MAP */
291 * structure for control status reg in rxdma address map
292 * Located at address 0x2000
306 * 15: pkt_drop_disable
314 * structure for dma writeback lo reg in rxdma address map
315 * located at address 0x2004
316 * Defined earlier (u32)
320 * structure for dma writeback hi reg in rxdma address map
321 * located at address 0x2008
322 * Defined earlier (u32)
326 * structure for number of packets done reg in rxdma address map
327 * located at address 0x200C
334 * structure for max packet time reg in rxdma address map
335 * located at address 0x2010
342 * structure for rx queue read address reg in rxdma address map
343 * located at address 0x2014
344 * Defined earlier (u32)
348 * structure for rx queue read address external reg in rxdma address map
349 * located at address 0x2018
350 * Defined earlier (u32)
354 * structure for rx queue write address reg in rxdma address map
355 * located at address 0x201C
356 * Defined earlier (u32)
360 * structure for packet status ring base address lo reg in rxdma address map
361 * located at address 0x2020
362 * Defined earlier (u32)
366 * structure for packet status ring base address hi reg in rxdma address map
367 * located at address 0x2024
368 * Defined earlier (u32)
372 * structure for packet status ring number of descriptors reg in rxdma address
373 * map. Located at address 0x2028
380 * structure for packet status ring available offset reg in rxdma address map
381 * located at address 0x202C
389 * structure for packet status ring full offset reg in rxdma address map
390 * located at address 0x2030
398 * structure for packet status ring access index reg in rxdma address map
399 * located at address 0x2034
406 * structure for packet status ring minimum descriptors reg in rxdma address
407 * map. Located at address 0x2038
414 * structure for free buffer ring base lo address reg in rxdma address map
415 * located at address 0x203C
416 * Defined earlier (u32)
420 * structure for free buffer ring base hi address reg in rxdma address map
421 * located at address 0x2040
422 * Defined earlier (u32)
426 * structure for free buffer ring number of descriptors reg in rxdma address
427 * map. Located at address 0x2044
434 * structure for free buffer ring 0 available offset reg in rxdma address map
435 * located at address 0x2048
436 * Defined earlier (u32)
440 * structure for free buffer ring 0 full offset reg in rxdma address map
441 * located at address 0x204C
442 * Defined earlier (u32)
446 * structure for free buffer cache 0 full offset reg in rxdma address map
447 * located at address 0x2050
454 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
455 * located at address 0x2054
462 * structure for free buffer ring 1 base address lo reg in rxdma address map
463 * located at address 0x2058 - 0x205C
464 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
468 * structure for free buffer ring 1 number of descriptors reg in rxdma address
469 * map. Located at address 0x2060
470 * Defined earlier (RXDMA_FBR_NUM_DES_t)
474 * structure for free buffer ring 1 available offset reg in rxdma address map
475 * located at address 0x2064
476 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
480 * structure for free buffer ring 1 full offset reg in rxdma address map
481 * located at address 0x2068
482 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
486 * structure for free buffer cache 1 read index reg in rxdma address map
487 * located at address 0x206C
488 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
492 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
493 * located at address 0x2070
494 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
498 * Rx DMA Module of JAGCore Address Mapping
499 * Located at address 0x2000
501 struct rxdma_regs { /* Location: */
502 u32 csr; /* 0x2000 */
503 u32 dma_wb_base_lo; /* 0x2004 */
504 u32 dma_wb_base_hi; /* 0x2008 */
505 u32 num_pkt_done; /* 0x200C */
506 u32 max_pkt_time; /* 0x2010 */
507 u32 rxq_rd_addr; /* 0x2014 */
508 u32 rxq_rd_addr_ext; /* 0x2018 */
509 u32 rxq_wr_addr; /* 0x201C */
510 u32 psr_base_lo; /* 0x2020 */
511 u32 psr_base_hi; /* 0x2024 */
512 u32 psr_num_des; /* 0x2028 */
513 u32 psr_avail_offset; /* 0x202C */
514 u32 psr_full_offset; /* 0x2030 */
515 u32 psr_access_index; /* 0x2034 */
516 u32 psr_min_des; /* 0x2038 */
517 u32 fbr0_base_lo; /* 0x203C */
518 u32 fbr0_base_hi; /* 0x2040 */
519 u32 fbr0_num_des; /* 0x2044 */
520 u32 fbr0_avail_offset; /* 0x2048 */
521 u32 fbr0_full_offset; /* 0x204C */
522 u32 fbr0_rd_index; /* 0x2050 */
523 u32 fbr0_min_des; /* 0x2054 */
524 u32 fbr1_base_lo; /* 0x2058 */
525 u32 fbr1_base_hi; /* 0x205C */
526 u32 fbr1_num_des; /* 0x2060 */
527 u32 fbr1_avail_offset; /* 0x2064 */
528 u32 fbr1_full_offset; /* 0x2068 */
529 u32 fbr1_rd_index; /* 0x206C */
530 u32 fbr1_min_des; /* 0x2070 */
533 /* END OF RXDMA REGISTER ADDRESS MAP */
536 /* START OF TXMAC REGISTER ADDRESS MAP */
539 * structure for control reg in txmac address map
540 * located at address 0x3000
555 * structure for shadow pointer reg in txmac address map
556 * located at address 0x3004
564 * structure for error count reg in txmac address map
565 * located at address 0x3008
574 * structure for max fill reg in txmac address map
575 * located at address 0x300C
581 * structure for cf parameter reg in txmac address map
582 * located at address 0x3010
588 * structure for tx test reg in txmac address map
589 * located at address 0x3014
594 * 10-0: txq test pointer
598 * structure for error reg in txmac address map
599 * located at address 0x3018
613 * structure for error interrupt reg in txmac address map
614 * located at address 0x301C
628 * structure for error interrupt reg in txmac address map
629 * located at address 0x3020
637 * Tx MAC Module of JAGCore Address Mapping
639 struct txmac_regs { /* Location: */
640 u32 ctl; /* 0x3000 */
641 u32 shadow_ptr; /* 0x3004 */
642 u32 err_cnt; /* 0x3008 */
643 u32 max_fill; /* 0x300C */
644 u32 cf_param; /* 0x3010 */
645 u32 tx_test; /* 0x3014 */
646 u32 err; /* 0x3018 */
647 u32 err_int; /* 0x301C */
648 u32 bp_ctrl; /* 0x3020 */
651 /* END OF TXMAC REGISTER ADDRESS MAP */
653 /* START OF RXMAC REGISTER ADDRESS MAP */
656 * structure for rxmac control reg in rxmac address map
657 * located at address 0x4000
660 * 6: rxmac_int_disable
664 * 2: pkt_filter_disable
670 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
671 * located at address 0x4004
685 * structure for CRC 1 and CRC 2 reg in rxmac address map
686 * located at address 0x4008
693 * structure for CRC 3 and CRC 4 reg in rxmac address map
694 * located at address 0x400C
701 * structure for Wake On Lan Source Address Lo reg in rxmac address map
702 * located at address 0x4010
704 typedef union _RXMAC_WOL_SA_LO_t {
707 #ifdef _BIT_FIELDS_HTOL
708 u32 sa3:8; /* bits 24-31 */
709 u32 sa4:8; /* bits 16-23 */
710 u32 sa5:8; /* bits 8-15 */
711 u32 sa6:8; /* bits 0-7 */
713 u32 sa6:8; /* bits 0-7 */
714 u32 sa5:8; /* bits 8-15 */
715 u32 sa4:8; /* bits 16-23 */
716 u32 sa3:8; /* bits 24-31 */
719 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
722 * structure for Wake On Lan Source Address Hi reg in rxmac address map
723 * located at address 0x4014
725 typedef union _RXMAC_WOL_SA_HI_t {
728 #ifdef _BIT_FIELDS_HTOL
729 u32 reserved:16; /* bits 16-31 */
730 u32 sa1:8; /* bits 8-15 */
731 u32 sa2:8; /* bits 0-7 */
733 u32 sa2:8; /* bits 0-7 */
734 u32 sa1:8; /* bits 8-15 */
735 u32 reserved:16; /* bits 16-31 */
738 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
741 * structure for Wake On Lan mask reg in rxmac address map
742 * located at address 0x4018 - 0x4064
743 * Defined earlier (u32)
747 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
748 * located at address 0x4068
750 typedef union _RXMAC_UNI_PF_ADDR1_t {
753 #ifdef _BIT_FIELDS_HTOL
754 u32 addr1_3:8; /* bits 24-31 */
755 u32 addr1_4:8; /* bits 16-23 */
756 u32 addr1_5:8; /* bits 8-15 */
757 u32 addr1_6:8; /* bits 0-7 */
759 u32 addr1_6:8; /* bits 0-7 */
760 u32 addr1_5:8; /* bits 8-15 */
761 u32 addr1_4:8; /* bits 16-23 */
762 u32 addr1_3:8; /* bits 24-31 */
765 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
768 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
769 * located at address 0x406C
771 typedef union _RXMAC_UNI_PF_ADDR2_t {
774 #ifdef _BIT_FIELDS_HTOL
775 u32 addr2_3:8; /* bits 24-31 */
776 u32 addr2_4:8; /* bits 16-23 */
777 u32 addr2_5:8; /* bits 8-15 */
778 u32 addr2_6:8; /* bits 0-7 */
780 u32 addr2_6:8; /* bits 0-7 */
781 u32 addr2_5:8; /* bits 8-15 */
782 u32 addr2_4:8; /* bits 16-23 */
783 u32 addr2_3:8; /* bits 24-31 */
786 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
789 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
790 * located at address 0x4070
792 typedef union _RXMAC_UNI_PF_ADDR3_t {
795 #ifdef _BIT_FIELDS_HTOL
796 u32 addr2_1:8; /* bits 24-31 */
797 u32 addr2_2:8; /* bits 16-23 */
798 u32 addr1_1:8; /* bits 8-15 */
799 u32 addr1_2:8; /* bits 0-7 */
801 u32 addr1_2:8; /* bits 0-7 */
802 u32 addr1_1:8; /* bits 8-15 */
803 u32 addr2_2:8; /* bits 16-23 */
804 u32 addr2_1:8; /* bits 24-31 */
807 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
810 * structure for Multicast Hash reg in rxmac address map
811 * located at address 0x4074 - 0x4080
812 * Defined earlier (u32)
816 * structure for Packet Filter Control reg in rxmac address map
817 * located at address 0x4084
820 * 22-16: min_pkt_size
829 * structure for Memory Controller Interface Control Max Segment reg in rxmac
830 * address map. Located at address 0x4088
839 * structure for Memory Controller Interface Water Mark reg in rxmac address
840 * map. Located at address 0x408C
849 * structure for Rx Queue Dialog reg in rxmac address map.
850 * located at address 0x4090
859 * structure for space available reg in rxmac address map.
860 * located at address 0x4094
869 * structure for management interface reg in rxmac address map.
870 * located at address 0x4098
874 * 16-0: drop_pkt_mask
878 * structure for Error reg in rxmac address map.
879 * located at address 0x409C
889 * Rx MAC Module of JAGCore Address Mapping
891 typedef struct _RXMAC_t { /* Location: */
892 u32 ctrl; /* 0x4000 */
893 u32 crc0; /* 0x4004 */
894 u32 crc12; /* 0x4008 */
895 u32 crc34; /* 0x400C */
896 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
897 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
898 u32 mask0_word0; /* 0x4018 */
899 u32 mask0_word1; /* 0x401C */
900 u32 mask0_word2; /* 0x4020 */
901 u32 mask0_word3; /* 0x4024 */
902 u32 mask1_word0; /* 0x4028 */
903 u32 mask1_word1; /* 0x402C */
904 u32 mask1_word2; /* 0x4030 */
905 u32 mask1_word3; /* 0x4034 */
906 u32 mask2_word0; /* 0x4038 */
907 u32 mask2_word1; /* 0x403C */
908 u32 mask2_word2; /* 0x4040 */
909 u32 mask2_word3; /* 0x4044 */
910 u32 mask3_word0; /* 0x4048 */
911 u32 mask3_word1; /* 0x404C */
912 u32 mask3_word2; /* 0x4050 */
913 u32 mask3_word3; /* 0x4054 */
914 u32 mask4_word0; /* 0x4058 */
915 u32 mask4_word1; /* 0x405C */
916 u32 mask4_word2; /* 0x4060 */
917 u32 mask4_word3; /* 0x4064 */
918 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
919 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
920 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
921 u32 multi_hash1; /* 0x4074 */
922 u32 multi_hash2; /* 0x4078 */
923 u32 multi_hash3; /* 0x407C */
924 u32 multi_hash4; /* 0x4080 */
925 u32 pf_ctrl; /* 0x4084 */
926 u32 mcif_ctrl_max_seg; /* 0x4088 */
927 u32 mcif_water_mark; /* 0x408C */
928 u32 rxq_diag; /* 0x4090 */
929 u32 space_avail; /* 0x4094 */
931 u32 mif_ctrl; /* 0x4098 */
932 u32 err_reg; /* 0x409C */
933 } RXMAC_t, *PRXMAC_t;
935 /* END OF RXMAC REGISTER ADDRESS MAP */
938 /* START OF MAC REGISTER ADDRESS MAP */
941 * structure for configuration #1 reg in mac address map.
942 * located at address 0x5000
962 #define CFG1_LOOPBACK 0x00000100
963 #define CFG1_RX_FLOW 0x00000020
964 #define CFG1_TX_FLOW 0x00000010
965 #define CFG1_RX_ENABLE 0x00000004
966 #define CFG1_TX_ENABLE 0x00000001
967 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
970 * structure for configuration #2 reg in mac address map.
971 * located at address 0x5004
987 * structure for Interpacket gap reg in mac address map.
988 * located at address 0x5008
991 * 30-24: non B2B ipg 1
993 * 22-16: non B2B ipg 2
994 * 15-8: Min ifg enforce
997 * structure for half duplex reg in mac address map.
998 * located at address 0x500C
1000 * 23-20: Alt BEB trunc
1001 * 19: Alt BEB enable
1005 * 15-12: re-xmit max
1007 * 9-0: collision window
1011 * structure for Maximum Frame Length reg in mac address map.
1012 * located at address 0x5010: bits 0-15 hold the length.
1016 * structure for Reserve 1 reg in mac address map.
1017 * located at address 0x5014 - 0x5018
1018 * Defined earlier (u32)
1022 * structure for Test reg in mac address map.
1023 * located at address 0x501C
1024 * test: bits 0-2, rest unused
1028 * structure for MII Management Configuration reg in mac address map.
1029 * located at address 0x5020
1031 * 31: reset MII mgmt
1033 * 5: scan auto increment
1034 * 4: preamble suppress
1036 * 2-0: mgmt clock reset
1040 * structure for MII Management Command reg in mac address map.
1041 * located at address 0x5024
1047 * structure for MII Management Address reg in mac address map.
1048 * located at address 0x5028
1055 #define MII_ADDR(phy, reg) ((phy) << 8 | (reg))
1058 * structure for MII Management Control reg in mac address map.
1059 * located at address 0x502C
1065 * structure for MII Management Status reg in mac address map.
1066 * located at address 0x5030
1072 * structure for MII Management Indicators reg in mac address map.
1073 * located at address 0x5034
1080 #define MGMT_BUSY 0x00000001 /* busy */
1081 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1084 * structure for Interface Control reg in mac address map.
1085 * located at address 0x5038
1087 * 31: reset if module
1100 * 8: disable link fail
1103 * 0: enable jabber protection
1107 * structure for Interface Status reg in mac address map.
1108 * located at address 0x503C
1115 * 5: phy_full_duplex
1117 * 3: pe100x_link_fail
1118 * 2: pe10t_loss_carrier
1119 * 1: pe10t_sqe_error
1124 * structure for Mac Station Address, Part 1 reg in mac address map.
1125 * located at address 0x5040
1127 typedef union _MAC_STATION_ADDR1_t {
1130 #ifdef _BIT_FIELDS_HTOL
1131 u32 Octet6:8; /* bits 24-31 */
1132 u32 Octet5:8; /* bits 16-23 */
1133 u32 Octet4:8; /* bits 8-15 */
1134 u32 Octet3:8; /* bits 0-7 */
1136 u32 Octet3:8; /* bits 0-7 */
1137 u32 Octet4:8; /* bits 8-15 */
1138 u32 Octet5:8; /* bits 16-23 */
1139 u32 Octet6:8; /* bits 24-31 */
1142 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1145 * structure for Mac Station Address, Part 2 reg in mac address map.
1146 * located at address 0x5044
1148 typedef union _MAC_STATION_ADDR2_t {
1151 #ifdef _BIT_FIELDS_HTOL
1152 u32 Octet2:8; /* bits 24-31 */
1153 u32 Octet1:8; /* bits 16-23 */
1154 u32 reserved:16; /* bits 0-15 */
1156 u32 reserved:16; /* bit 0-15 */
1157 u32 Octet1:8; /* bits 16-23 */
1158 u32 Octet2:8; /* bits 24-31 */
1161 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1164 * MAC Module of JAGCore Address Mapping
1166 typedef struct _MAC_t { /* Location: */
1167 u32 cfg1; /* 0x5000 */
1168 u32 cfg2; /* 0x5004 */
1169 u32 ipg; /* 0x5008 */
1170 u32 hfdp; /* 0x500C */
1171 u32 max_fm_len; /* 0x5010 */
1172 u32 rsv1; /* 0x5014 */
1173 u32 rsv2; /* 0x5018 */
1174 u32 mac_test; /* 0x501C */
1175 u32 mii_mgmt_cfg; /* 0x5020 */
1176 u32 mii_mgmt_cmd; /* 0x5024 */
1177 u32 mii_mgmt_addr; /* 0x5028 */
1178 u32 mii_mgmt_ctrl; /* 0x502C */
1179 u32 mii_mgmt_stat; /* 0x5030 */
1180 u32 mii_mgmt_indicator; /* 0x5034 */
1181 u32 if_ctrl; /* 0x5038 */
1182 u32 if_stat; /* 0x503C */
1183 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1184 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1187 /* END OF MAC REGISTER ADDRESS MAP */
1189 /* START OF MAC STAT REGISTER ADDRESS MAP */
1192 * structure for Carry Register One and it's Mask Register reg located in mac
1193 * stat address map address 0x6130 and 0x6138.
1223 * structure for Carry Register Two Mask Register reg in mac stat address map.
1224 * located at address 0x613C
1250 * MAC STATS Module of JAGCore Address Mapping
1252 struct macstat_regs { /* Location: */
1253 u32 pad[32]; /* 0x6000 - 607C */
1255 /* Tx/Rx 0-64 Byte Frame Counter */
1256 u32 TR64; /* 0x6080 */
1258 /* Tx/Rx 65-127 Byte Frame Counter */
1259 u32 TR127; /* 0x6084 */
1261 /* Tx/Rx 128-255 Byte Frame Counter */
1262 u32 TR255; /* 0x6088 */
1264 /* Tx/Rx 256-511 Byte Frame Counter */
1265 u32 TR511; /* 0x608C */
1267 /* Tx/Rx 512-1023 Byte Frame Counter */
1268 u32 TR1K; /* 0x6090 */
1270 /* Tx/Rx 1024-1518 Byte Frame Counter */
1271 u32 TRMax; /* 0x6094 */
1273 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1274 u32 TRMgv; /* 0x6098 */
1276 /* Rx Byte Counter */
1277 u32 RByt; /* 0x609C */
1279 /* Rx Packet Counter */
1280 u32 RPkt; /* 0x60A0 */
1282 /* Rx FCS Error Counter */
1283 u32 RFcs; /* 0x60A4 */
1285 /* Rx Multicast Packet Counter */
1286 u32 RMca; /* 0x60A8 */
1288 /* Rx Broadcast Packet Counter */
1289 u32 RBca; /* 0x60AC */
1291 /* Rx Control Frame Packet Counter */
1292 u32 RxCf; /* 0x60B0 */
1294 /* Rx Pause Frame Packet Counter */
1295 u32 RxPf; /* 0x60B4 */
1297 /* Rx Unknown OP Code Counter */
1298 u32 RxUo; /* 0x60B8 */
1300 /* Rx Alignment Error Counter */
1301 u32 RAln; /* 0x60BC */
1303 /* Rx Frame Length Error Counter */
1304 u32 RFlr; /* 0x60C0 */
1306 /* Rx Code Error Counter */
1307 u32 RCde; /* 0x60C4 */
1309 /* Rx Carrier Sense Error Counter */
1310 u32 RCse; /* 0x60C8 */
1312 /* Rx Undersize Packet Counter */
1313 u32 RUnd; /* 0x60CC */
1315 /* Rx Oversize Packet Counter */
1316 u32 ROvr; /* 0x60D0 */
1318 /* Rx Fragment Counter */
1319 u32 RFrg; /* 0x60D4 */
1321 /* Rx Jabber Counter */
1322 u32 RJbr; /* 0x60D8 */
1325 u32 RDrp; /* 0x60DC */
1327 /* Tx Byte Counter */
1328 u32 TByt; /* 0x60E0 */
1330 /* Tx Packet Counter */
1331 u32 TPkt; /* 0x60E4 */
1333 /* Tx Multicast Packet Counter */
1334 u32 TMca; /* 0x60E8 */
1336 /* Tx Broadcast Packet Counter */
1337 u32 TBca; /* 0x60EC */
1339 /* Tx Pause Control Frame Counter */
1340 u32 TxPf; /* 0x60F0 */
1342 /* Tx Deferral Packet Counter */
1343 u32 TDfr; /* 0x60F4 */
1345 /* Tx Excessive Deferral Packet Counter */
1346 u32 TEdf; /* 0x60F8 */
1348 /* Tx Single Collision Packet Counter */
1349 u32 TScl; /* 0x60FC */
1351 /* Tx Multiple Collision Packet Counter */
1352 u32 TMcl; /* 0x6100 */
1354 /* Tx Late Collision Packet Counter */
1355 u32 TLcl; /* 0x6104 */
1357 /* Tx Excessive Collision Packet Counter */
1358 u32 TXcl; /* 0x6108 */
1360 /* Tx Total Collision Packet Counter */
1361 u32 TNcl; /* 0x610C */
1363 /* Tx Pause Frame Honored Counter */
1364 u32 TPfh; /* 0x6110 */
1366 /* Tx Drop Frame Counter */
1367 u32 TDrp; /* 0x6114 */
1369 /* Tx Jabber Frame Counter */
1370 u32 TJbr; /* 0x6118 */
1372 /* Tx FCS Error Counter */
1373 u32 TFcs; /* 0x611C */
1375 /* Tx Control Frame Counter */
1376 u32 TxCf; /* 0x6120 */
1378 /* Tx Oversize Frame Counter */
1379 u32 TOvr; /* 0x6124 */
1381 /* Tx Undersize Frame Counter */
1382 u32 TUnd; /* 0x6128 */
1384 /* Tx Fragments Frame Counter */
1385 u32 TFrg; /* 0x612C */
1387 /* Carry Register One Register */
1388 u32 Carry1; /* 0x6130 */
1390 /* Carry Register Two Register */
1391 u32 Carry2; /* 0x6134 */
1393 /* Carry Register One Mask Register */
1394 u32 Carry1M; /* 0x6138 */
1396 /* Carry Register Two Mask Register */
1397 u32 Carry2M; /* 0x613C */
1400 /* END OF MAC STAT REGISTER ADDRESS MAP */
1403 /* START OF MMC REGISTER ADDRESS MAP */
1406 * Main Memory Controller Control reg in mmc address map.
1407 * located at address 0x7000
1410 #define ET_MMC_ENABLE 1
1411 #define ET_MMC_ARB_DISABLE 2
1412 #define ET_MMC_RXMAC_DISABLE 4
1413 #define ET_MMC_TXMAC_DISABLE 8
1414 #define ET_MMC_TXDMA_DISABLE 16
1415 #define ET_MMC_RXDMA_DISABLE 32
1416 #define ET_MMC_FORCE_CE 64
1419 * Main Memory Controller Host Memory Access Address reg in mmc
1420 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1423 #define ET_SRAM_REQ_ACCESS 1
1424 #define ET_SRAM_WR_ACCESS 2
1425 #define ET_SRAM_IS_CTRL 4
1428 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1429 * address map. Located at address 0x7008 - 0x7014
1430 * Defined earlier (u32)
1434 * Memory Control Module of JAGCore Address Mapping
1436 struct mmc_regs { /* Location: */
1437 u32 mmc_ctrl; /* 0x7000 */
1438 u32 sram_access; /* 0x7004 */
1439 u32 sram_word1; /* 0x7008 */
1440 u32 sram_word2; /* 0x700C */
1441 u32 sram_word3; /* 0x7010 */
1442 u32 sram_word4; /* 0x7014 */
1445 /* END OF MMC REGISTER ADDRESS MAP */
1449 * JAGCore Address Mapping
1451 typedef struct _ADDRESS_MAP_t {
1452 struct global_regs global;
1453 /* unused section of global address map */
1454 u8 unused_global[4096 - sizeof(struct global_regs)];
1455 struct txdma_regs txdma;
1456 /* unused section of txdma address map */
1457 u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
1458 struct rxdma_regs rxdma;
1459 /* unused section of rxdma address map */
1460 u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
1461 struct txmac_regs txmac;
1462 /* unused section of txmac address map */
1463 u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
1465 /* unused section of rxmac address map */
1466 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1468 /* unused section of mac address map */
1469 u8 unused_mac[4096 - sizeof(MAC_t)];
1470 struct macstat_regs macstat;
1471 /* unused section of mac stat address map */
1472 u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
1473 struct mmc_regs mmc;
1474 /* unused section of mmc address map */
1475 u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
1476 /* unused section of address map */
1477 u8 unused_[1015808];
1479 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1480 u8 unused__[524288]; /* unused section of address map */
1481 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1483 #endif /* _ET1310_ADDRESS_MAP_H_ */