3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright * 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_phy.c - Routines for configuring and accessing the PHY
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright * 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/ctype.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
74 #include <linux/delay.h>
76 #include <linux/bitops.h>
77 #include <asm/system.h>
79 #include <linux/netdevice.h>
80 #include <linux/etherdevice.h>
81 #include <linux/skbuff.h>
82 #include <linux/if_arp.h>
83 #include <linux/ioport.h>
84 #include <linux/random.h>
86 #include "et1310_phy.h"
88 #include "et131x_adapter.h"
90 #include "et1310_address_map.h"
91 #include "et1310_tx.h"
92 #include "et1310_rx.h"
96 /* Prototypes for functions with local scope */
97 static void et131x_xcvr_init(struct et131x_adapter *etdev);
100 * PhyMiRead - Read from the PHY through the MII Interface on the MAC
101 * @etdev: pointer to our private adapter structure
102 * @xcvrAddr: the address of the transciever
103 * @xcvrReg: the register to read
104 * @value: pointer to a 16-bit value in which the value will be stored
106 * Returns 0 on success, errno on failure (as defined in errno.h)
108 int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
109 u8 xcvrReg, u16 *value)
111 struct _MAC_t __iomem *mac = &etdev->regs->mac;
118 /* Save a local copy of the registers we are dealing with so we can
121 miiAddr = readl(&mac->mii_mgmt_addr);
122 miiCmd = readl(&mac->mii_mgmt_cmd);
124 /* Stop the current operation */
125 writel(0, &mac->mii_mgmt_cmd);
127 /* Set up the register we need to read from on the correct PHY */
128 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
130 /* Kick the read cycle off */
133 writel(0x1, &mac->mii_mgmt_cmd);
138 miiIndicator = readl(&mac->mii_mgmt_indicator);
139 } while ((miiIndicator & MGMT_WAIT) && delay < 50);
141 /* If we hit the max delay, we could not read the register */
143 dev_warn(&etdev->pdev->dev,
144 "xcvrReg 0x%08x could not be read\n", xcvrReg);
145 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
151 /* If we hit here we were able to read the register and we need to
152 * return the value to the caller */
153 *value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
155 /* Stop the read operation */
156 writel(0, &mac->mii_mgmt_cmd);
158 /* set the registers we touched back to the state at which we entered
161 writel(miiAddr, &mac->mii_mgmt_addr);
162 writel(miiCmd, &mac->mii_mgmt_cmd);
168 * MiWrite - Write to a PHY register through the MII interface of the MAC
169 * @etdev: pointer to our private adapter structure
170 * @xcvrReg: the register to read
171 * @value: 16-bit value to write
173 * FIXME: one caller in netdev still
175 * Return 0 on success, errno on failure (as defined in errno.h)
177 int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
179 struct _MAC_t __iomem *mac = &etdev->regs->mac;
181 u8 xcvrAddr = etdev->Stats.xcvr_addr;
187 /* Save a local copy of the registers we are dealing with so we can
190 miiAddr = readl(&mac->mii_mgmt_addr);
191 miiCmd = readl(&mac->mii_mgmt_cmd);
193 /* Stop the current operation */
194 writel(0, &mac->mii_mgmt_cmd);
196 /* Set up the register we need to write to on the correct PHY */
197 writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
199 /* Add the value to write to the registers to the mac */
200 writel(value, &mac->mii_mgmt_ctrl);
206 miiIndicator = readl(&mac->mii_mgmt_indicator);
207 } while ((miiIndicator & MGMT_BUSY) && delay < 100);
209 /* If we hit the max delay, we could not write the register */
213 dev_warn(&etdev->pdev->dev,
214 "xcvrReg 0x%08x could not be written", xcvrReg);
215 dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
217 dev_warn(&etdev->pdev->dev, "command is 0x%08x\n",
218 readl(&mac->mii_mgmt_cmd));
220 MiRead(etdev, xcvrReg, &TempValue);
224 /* Stop the write operation */
225 writel(0, &mac->mii_mgmt_cmd);
227 /* set the registers we touched back to the state at which we entered
230 writel(miiAddr, &mac->mii_mgmt_addr);
231 writel(miiCmd, &mac->mii_mgmt_cmd);
237 * et131x_xcvr_find - Find the PHY ID
238 * @etdev: pointer to our private adapter structure
240 * Returns 0 on success, errno on failure (as defined in errno.h)
242 int et131x_xcvr_find(struct et131x_adapter *etdev)
249 /* We need to get xcvr id and address we just get the first one */
250 for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
251 /* Read the ID from the PHY */
252 PhyMiRead(etdev, xcvr_addr,
253 (u8) offsetof(MI_REGS_t, idr1),
255 PhyMiRead(etdev, xcvr_addr,
256 (u8) offsetof(MI_REGS_t, idr2),
259 xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
261 if (idr1.value != 0 && idr1.value != 0xffff) {
262 etdev->Stats.xcvr_id = xcvr_id;
263 etdev->Stats.xcvr_addr = xcvr_addr;
270 void ET1310_PhyReset(struct et131x_adapter *etdev)
272 MiWrite(etdev, PHY_CONTROL, 0x8000);
276 * ET1310_PhyPowerDown - PHY power control
277 * @etdev: device to control
278 * @down: true for off/false for back on
280 * one hundred, ten, one thousand megs
281 * How would you like to have your LAN accessed
282 * Can't you see that this code processed
283 * Phy power, phy power..
286 void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
290 MiRead(etdev, PHY_CONTROL, &data);
291 data &= ~0x0800; /* Power UP */
292 if (down) /* Power DOWN */
294 MiWrite(etdev, PHY_CONTROL, data);
298 * ET130_PhyAutoNEg - autonegotiate control
299 * @etdev: device to control
300 * @enabe: autoneg on/off
302 * Set up the autonegotiation state according to whether we will be
303 * negotiating the state or forcing a speed.
306 static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
310 MiRead(etdev, PHY_CONTROL, &data);
311 data &= ~0x1000; /* Autonegotiation OFF */
313 data |= 0x1000; /* Autonegotiation ON */
314 MiWrite(etdev, PHY_CONTROL, data);
318 * ET130_PhyDuplexMode - duplex control
319 * @etdev: device to control
320 * @duplex: duplex on/off
322 * Set up the duplex state on the PHY
325 static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
329 MiRead(etdev, PHY_CONTROL, &data);
330 data &= ~0x100; /* Set Half Duplex */
331 if (duplex == TRUEPHY_DUPLEX_FULL)
332 data |= 0x100; /* Set Full Duplex */
333 MiWrite(etdev, PHY_CONTROL, data);
337 * ET130_PhySpeedSelect - speed control
338 * @etdev: device to control
339 * @duplex: duplex on/off
341 * Set the speed of our PHY.
344 static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
347 static const u16 bits[3]={0x0000, 0x2000, 0x0040};
349 /* Read the PHY control register */
350 MiRead(etdev, PHY_CONTROL, &data);
351 /* Clear all Speed settings (Bits 6, 13) */
353 /* Write back the new speed */
354 MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
358 * ET1310_PhyLinkStatus - read link state
359 * @etdev: device to read
360 * @link_status: reported link state
361 * @autoneg: reported autonegotiation state (complete/incomplete/disabled)
362 * @linkspeed: returnedlink speed in use
363 * @duplex_mode: reported half/full duplex state
364 * @mdi_mdix: not yet working
365 * @masterslave: report whether we are master or slave
366 * @polarity: link polarity
368 * I can read your lan like a magazine
370 * I know your link speed
371 * I see all the setting that you'd rather keep
374 static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
380 u32 *masterslave, u32 *polarity)
384 u16 vmi_phystatus = 0;
387 MiRead(etdev, PHY_STATUS, &mistatus);
388 MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
389 MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
390 MiRead(etdev, PHY_CONTROL, &control);
392 *link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
393 *autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
394 TRUEPHY_ANEG_COMPLETE :
395 TRUEPHY_ANEG_NOT_COMPLETE) :
396 TRUEPHY_ANEG_DISABLED;
397 *linkspeed = (vmi_phystatus & 0x0300) >> 8;
398 *duplex_mode = (vmi_phystatus & 0x0080) >> 7;
399 /* NOTE: Need to complete this */
402 *masterslave = (is1000BaseT & 0x4000) ?
403 TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
404 *polarity = (vmi_phystatus & 0x0400) ?
405 TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
408 static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
409 u16 regnum, u16 andMask, u16 orMask)
413 MiRead(etdev, regnum, ®);
416 MiWrite(etdev, regnum, reg);
419 /* Still used from _mac for BIT_READ */
420 void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
421 u16 regnum, u16 bitnum, u8 *value)
424 u16 mask = 0x0001 << bitnum;
426 /* Read the requested register */
427 MiRead(etdev, regnum, ®);
430 case TRUEPHY_BIT_READ:
431 *value = (reg & mask) >> bitnum;
434 case TRUEPHY_BIT_SET:
435 MiWrite(etdev, regnum, reg | mask);
438 case TRUEPHY_BIT_CLEAR:
439 MiWrite(etdev, regnum, reg & ~mask);
447 void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
452 /* Read the PHY 1000 Base-T Control Register */
453 MiRead(etdev, PHY_1000_CONTROL, &data);
459 case TRUEPHY_ADV_DUPLEX_NONE:
460 /* Duplex already cleared, do nothing */
463 case TRUEPHY_ADV_DUPLEX_FULL:
468 case TRUEPHY_ADV_DUPLEX_HALF:
473 case TRUEPHY_ADV_DUPLEX_BOTH:
479 /* Write back advertisement */
480 MiWrite(etdev, PHY_1000_CONTROL, data);
483 static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
488 /* Read the Autonegotiation Register (10/100) */
489 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
495 case TRUEPHY_ADV_DUPLEX_NONE:
496 /* Duplex already cleared, do nothing */
499 case TRUEPHY_ADV_DUPLEX_FULL:
504 case TRUEPHY_ADV_DUPLEX_HALF:
509 case TRUEPHY_ADV_DUPLEX_BOTH:
516 /* Write back advertisement */
517 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
520 static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
525 /* Read the Autonegotiation Register (10/100) */
526 MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
532 case TRUEPHY_ADV_DUPLEX_NONE:
533 /* Duplex already cleared, do nothing */
536 case TRUEPHY_ADV_DUPLEX_FULL:
541 case TRUEPHY_ADV_DUPLEX_HALF:
546 case TRUEPHY_ADV_DUPLEX_BOTH:
553 /* Write back advertisement */
554 MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
558 * et131x_setphy_normal - Set PHY for normal operation.
559 * @etdev: pointer to our private adapter structure
561 * Used by Power Management to force the PHY into 10 Base T half-duplex mode,
562 * when going to D3 in WOL mode. Also used during initialization to set the
563 * PHY for normal operation.
565 void et131x_setphy_normal(struct et131x_adapter *etdev)
567 /* Make sure the PHY is powered up */
568 ET1310_PhyPowerDown(etdev, 0);
569 et131x_xcvr_init(etdev);
574 * et131x_xcvr_init - Init the phy if we are setting it into force mode
575 * @etdev: pointer to our private adapter structure
578 static void et131x_xcvr_init(struct et131x_adapter *etdev)
584 /* Zero out the adapter structure variable representing BMSR */
585 etdev->Bmsr.value = 0;
587 MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
588 MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
590 /* Set the link status interrupt only. Bad behavior when link status
591 * and auto neg are set, we run into a nested interrupt problem
593 imr.bits.int_en = 0x1;
594 imr.bits.link_status = 0x1;
595 imr.bits.autoneg_status = 0x1;
597 MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
599 /* Set the LED behavior such that LED 1 indicates speed (off =
600 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
601 * link and activity (on for link, blink off for activity).
603 * NOTE: Some customizations have been added here for specific
604 * vendors; The LED behavior is now determined by vendor data in the
605 * EEPROM. However, the above description is the default.
607 if ((etdev->eepromData[1] & 0x4) == 0) {
608 MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
610 if ((etdev->eepromData[1] & 0x8) == 0)
611 lcr2.bits.led_tx_rx = 0x3;
613 lcr2.bits.led_tx_rx = 0x4;
614 lcr2.bits.led_link = 0xa;
615 MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
619 /* Determine if we need to go into a force mode and set it */
620 if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
621 if (etdev->RegistryFlowControl == TxOnly ||
622 etdev->RegistryFlowControl == Both)
623 ET1310_PhyAccessMiBit(etdev,
624 TRUEPHY_BIT_SET, 4, 11, NULL);
626 ET1310_PhyAccessMiBit(etdev,
627 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
629 if (etdev->RegistryFlowControl == Both)
630 ET1310_PhyAccessMiBit(etdev,
631 TRUEPHY_BIT_SET, 4, 10, NULL);
633 ET1310_PhyAccessMiBit(etdev,
634 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
636 /* Set the phy to autonegotiation */
637 ET1310_PhyAutoNeg(etdev, true);
639 /* NOTE - Do we need this? */
640 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
644 ET1310_PhyAutoNeg(etdev, false);
646 /* Set to the correct force mode. */
647 if (etdev->AiForceDpx != 1) {
648 if (etdev->RegistryFlowControl == TxOnly ||
649 etdev->RegistryFlowControl == Both)
650 ET1310_PhyAccessMiBit(etdev,
651 TRUEPHY_BIT_SET, 4, 11, NULL);
653 ET1310_PhyAccessMiBit(etdev,
654 TRUEPHY_BIT_CLEAR, 4, 11, NULL);
656 if (etdev->RegistryFlowControl == Both)
657 ET1310_PhyAccessMiBit(etdev,
658 TRUEPHY_BIT_SET, 4, 10, NULL);
660 ET1310_PhyAccessMiBit(etdev,
661 TRUEPHY_BIT_CLEAR, 4, 10, NULL);
663 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
664 ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
666 ET1310_PhyPowerDown(etdev, 1);
667 switch (etdev->AiForceSpeed) {
669 /* First we need to turn off all other advertisement */
670 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
671 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
672 if (etdev->AiForceDpx == 1) {
673 /* Set our advertise values accordingly */
674 ET1310_PhyAdvertise10BaseT(etdev,
675 TRUEPHY_ADV_DUPLEX_HALF);
676 } else if (etdev->AiForceDpx == 2) {
677 /* Set our advertise values accordingly */
678 ET1310_PhyAdvertise10BaseT(etdev,
679 TRUEPHY_ADV_DUPLEX_FULL);
681 /* Disable autoneg */
682 ET1310_PhyAutoNeg(etdev, false);
683 /* Disable rest of the advertisements */
684 ET1310_PhyAdvertise10BaseT(etdev,
685 TRUEPHY_ADV_DUPLEX_NONE);
687 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
688 /* Force Full duplex */
689 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
693 /* first we need to turn off all other advertisement */
694 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
695 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
696 if (etdev->AiForceDpx == 1) {
697 /* Set our advertise values accordingly */
698 ET1310_PhyAdvertise100BaseT(etdev,
699 TRUEPHY_ADV_DUPLEX_HALF);
701 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
702 } else if (etdev->AiForceDpx == 2) {
703 /* Set our advertise values accordingly */
704 ET1310_PhyAdvertise100BaseT(etdev,
705 TRUEPHY_ADV_DUPLEX_FULL);
707 /* Disable autoneg */
708 ET1310_PhyAutoNeg(etdev, false);
709 /* Disable other advertisement */
710 ET1310_PhyAdvertise100BaseT(etdev,
711 TRUEPHY_ADV_DUPLEX_NONE);
713 ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
714 /* Force Full duplex */
715 ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
719 /* first we need to turn off all other advertisement */
720 ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
721 ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
722 /* set our advertise values accordingly */
723 ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
726 ET1310_PhyPowerDown(etdev, 0);
729 void et131x_Mii_check(struct et131x_adapter *etdev,
730 MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
741 if (bmsr_ints.bits.link_status) {
742 if (bmsr.bits.link_status) {
743 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
745 /* Update our state variables and indicate the
748 spin_lock_irqsave(&etdev->Lock, flags);
750 etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
751 etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
753 spin_unlock_irqrestore(&etdev->Lock, flags);
755 netif_carrier_on(etdev->netdev);
757 dev_warn(&etdev->pdev->dev,
758 "Link down - cable problem ?\n");
760 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
761 /* NOTE - Is there a way to query this without
763 * && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
767 MiRead(etdev, 0x12, &Register18);
768 MiWrite(etdev, 0x12, Register18 | 0x4);
769 MiWrite(etdev, 0x10, Register18 | 0x8402);
770 MiWrite(etdev, 0x11, Register18 | 511);
771 MiWrite(etdev, 0x12, Register18);
774 /* For the first N seconds of life, we are in "link
775 * detection" When we are in this state, we should
776 * only report "connected". When the LinkDetection
777 * Timer expires, we can report disconnected (handled
778 * in the LinkDetectionDPC).
780 if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
781 (etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
782 spin_lock_irqsave(&etdev->Lock, flags);
784 NETIF_STATUS_MEDIA_DISCONNECT;
785 spin_unlock_irqrestore(&etdev->Lock,
788 netif_carrier_off(etdev->netdev);
791 etdev->linkspeed = 0;
792 etdev->duplex_mode = 0;
794 /* Free the packets being actively sent & stopped */
795 et131x_free_busy_send_packets(etdev);
797 /* Re-initialize the send structures */
798 et131x_init_send(etdev);
800 /* Reset the RFD list and re-start RU */
801 et131x_reset_recv(etdev);
804 * Bring the device back to the state it was during
805 * init prior to autonegotiation being complete. This
806 * way, when we get the auto-neg complete interrupt,
807 * we can complete init by calling ConfigMacREGS2.
809 et131x_soft_reset(etdev);
811 /* Setup ET1310 as per the documentation */
812 et131x_adapter_setup(etdev);
814 /* Setup the PHY into coma mode until the cable is
817 if (etdev->RegistryPhyComa == 1)
818 EnablePhyComa(etdev);
822 if (bmsr_ints.bits.auto_neg_complete ||
823 (etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
824 if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
825 ET1310_PhyLinkStatus(etdev,
826 &link_status, &autoneg_status,
827 &speed, &duplex, &mdi_mdix,
828 &masterslave, &polarity);
830 etdev->linkspeed = speed;
831 etdev->duplex_mode = duplex;
833 etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
835 if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
837 * NOTE - Is there a way to query this without
839 * && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
843 MiRead(etdev, 0x12, &Register18);
844 MiWrite(etdev, 0x12, Register18 | 0x4);
845 MiWrite(etdev, 0x10, Register18 | 0x8402);
846 MiWrite(etdev, 0x11, Register18 | 511);
847 MiWrite(etdev, 0x12, Register18);
850 ConfigFlowControl(etdev);
852 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
853 etdev->RegistryJumboPacket > 2048)
854 ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
857 SetRxDmaTimer(etdev);
858 ConfigMACRegs2(etdev);
864 * The routines which follow provide low-level access to the PHY, and are used
865 * primarily by the routines above (although there are a few places elsewhere
866 * in the driver where this level of access is required).
869 static const u16 ConfigPhy[25][2] = {
870 /* Reg Value Register */
872 {0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
873 {0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
874 {0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
876 {0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
877 {0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
878 {0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
880 {0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
881 {0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
882 {0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
884 {0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
885 {0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
886 {0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
888 {0x300D, 1}, /* DisableNorm */
890 {0x280C, 0x0180}, /* LinkHoldEnd */
892 {0x1C21, 0x0002}, /* AlphaM */
894 {0x3821, 6}, /* FfeLkgTx0 */
895 {0x381D, 1}, /* FfeLkg1g4 */
896 {0x381E, 1}, /* FfeLkg1g5 */
897 {0x381F, 1}, /* FfeLkg1g6 */
898 {0x3820, 1}, /* FfeLkg1g7 */
900 {0x8402, 0x01F0}, /* Btinact */
901 {0x800E, 20}, /* LftrainTime */
902 {0x800F, 24}, /* DvguardTime */
903 {0x8010, 46}, /* IdlguardTime */
909 /* condensed version of the phy initialization routine */
910 void ET1310_PhyInit(struct et131x_adapter *etdev)
917 /* get the identity (again ?) */
918 MiRead(etdev, PHY_ID_1, &data);
919 MiRead(etdev, PHY_ID_2, &data);
921 /* what does this do/achieve ? */
922 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
923 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
925 /* read modem register 0402, should I do something with the return
927 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
928 MiRead(etdev, PHY_DATA_REG, &data);
930 /* what does this do/achieve ? */
931 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
933 /* get the identity (again ?) */
934 MiRead(etdev, PHY_ID_1, &data);
935 MiRead(etdev, PHY_ID_2, &data);
937 /* what does this achieve ? */
938 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
939 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
941 /* read modem register 0402, should I do something with
943 MiWrite(etdev, PHY_INDEX_REG, 0x0402);
944 MiRead(etdev, PHY_DATA_REG, &data);
946 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
948 /* what does this achieve (should return 0x1040) */
949 MiRead(etdev, PHY_CONTROL, &data);
950 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
951 MiWrite(etdev, PHY_CONTROL, 0x1840);
953 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
955 /* here the writing of the array starts.... */
957 while (ConfigPhy[index][0] != 0x0000) {
959 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
960 MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
963 MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
964 MiRead(etdev, PHY_DATA_REG, &data);
966 /* do a check on the value read back ? */
969 /* here the writing of the array ends... */
971 MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
972 MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
973 MiWrite(etdev, PHY_CONTROL, 0x1040);
974 MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);