3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
5 * Copyright © 2005 Agere Systems Inc.
9 *------------------------------------------------------------------------------
11 * et1310_tx.c - Routines used to perform data transmission.
13 *------------------------------------------------------------------------------
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
58 #include "et131x_version.h"
59 #include "et131x_defs.h"
61 #include <linux/pci.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/types.h>
65 #include <linux/kernel.h>
67 #include <linux/sched.h>
68 #include <linux/ptrace.h>
69 #include <linux/slab.h>
70 #include <linux/ctype.h>
71 #include <linux/string.h>
72 #include <linux/timer.h>
73 #include <linux/interrupt.h>
75 #include <linux/delay.h>
77 #include <linux/bitops.h>
78 #include <asm/system.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/if_arp.h>
84 #include <linux/ioport.h>
86 #include "et1310_phy.h"
87 #include "et1310_pm.h"
88 #include "et1310_jagcore.h"
90 #include "et131x_adapter.h"
91 #include "et131x_initpci.h"
92 #include "et131x_isr.h"
94 #include "et1310_tx.h"
97 static inline void et131x_free_send_packet(struct et131x_adapter *etdev,
99 static int et131x_send_packet(struct sk_buff *skb,
100 struct et131x_adapter *etdev);
101 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb);
104 * et131x_tx_dma_memory_alloc
105 * @adapter: pointer to our private adapter structure
107 * Returns 0 on success and errno on failure (as defined in errno.h).
109 * Allocates memory that will be visible both to the device and to the CPU.
110 * The OS will pass us packets, pointers to which we will insert in the Tx
111 * Descriptor queue. The device will read this queue to find the packets in
112 * memory. The device will update the "status" in memory each time it xmits a
115 int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
118 struct tx_ring *tx_ring = &adapter->tx_ring;
120 /* Allocate memory for the TCB's (Transmit Control Block) */
121 adapter->tx_ring.MpTcbMem = (struct tcb *)
122 kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA);
123 if (!adapter->tx_ring.MpTcbMem) {
124 dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n");
128 /* Allocate enough memory for the Tx descriptor ring, and allocate
129 * some extra so that the ring can be aligned on a 4k boundary.
131 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX) + 4096 - 1;
132 tx_ring->tx_desc_ring =
133 (struct tx_desc *) pci_alloc_consistent(adapter->pdev, desc_size,
134 &tx_ring->tx_desc_ring_pa);
135 if (!adapter->tx_ring.tx_desc_ring) {
136 dev_err(&adapter->pdev->dev, "Cannot alloc memory for Tx Ring\n");
140 /* Save physical address
142 * NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
143 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
144 * are ever returned, make sure the high part is retrieved here before
145 * storing the adjusted address.
147 /* Allocate memory for the Tx status block */
148 tx_ring->pTxStatusVa = pci_alloc_consistent(adapter->pdev,
149 sizeof(TX_STATUS_BLOCK_t),
150 &tx_ring->pTxStatusPa);
151 if (!adapter->tx_ring.pTxStatusPa) {
152 dev_err(&adapter->pdev->dev,
153 "Cannot alloc memory for Tx status block\n");
157 /* Allocate memory for a dummy buffer */
158 tx_ring->pTxDummyBlkVa = pci_alloc_consistent(adapter->pdev,
160 &tx_ring->pTxDummyBlkPa);
161 if (!adapter->tx_ring.pTxDummyBlkPa) {
162 dev_err(&adapter->pdev->dev,
163 "Cannot alloc memory for Tx dummy buffer\n");
171 * et131x_tx_dma_memory_free - Free all memory allocated within this module
172 * @adapter: pointer to our private adapter structure
174 * Returns 0 on success and errno on failure (as defined in errno.h).
176 void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
180 if (adapter->tx_ring.tx_desc_ring) {
181 /* Free memory relating to Tx rings here */
182 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX)
184 pci_free_consistent(adapter->pdev,
186 adapter->tx_ring.tx_desc_ring,
187 adapter->tx_ring.tx_desc_ring_pa);
188 adapter->tx_ring.tx_desc_ring = NULL;
191 /* Free memory for the Tx status block */
192 if (adapter->tx_ring.pTxStatusVa) {
193 pci_free_consistent(adapter->pdev,
194 sizeof(TX_STATUS_BLOCK_t),
195 adapter->tx_ring.pTxStatusVa,
196 adapter->tx_ring.pTxStatusPa);
198 adapter->tx_ring.pTxStatusVa = NULL;
201 /* Free memory for the dummy buffer */
202 if (adapter->tx_ring.pTxDummyBlkVa) {
203 pci_free_consistent(adapter->pdev,
205 adapter->tx_ring.pTxDummyBlkVa,
206 adapter->tx_ring.pTxDummyBlkPa);
208 adapter->tx_ring.pTxDummyBlkVa = NULL;
211 /* Free the memory for the tcb structures */
212 kfree(adapter->tx_ring.MpTcbMem);
216 * ConfigTxDmaRegs - Set up the tx dma section of the JAGCore.
217 * @etdev: pointer to our private adapter structure
219 void ConfigTxDmaRegs(struct et131x_adapter *etdev)
221 struct _TXDMA_t __iomem *txdma = &etdev->regs->txdma;
223 /* Load the hardware with the start of the transmit descriptor ring. */
224 writel((u32) ((u64)etdev->tx_ring.tx_desc_ring_pa >> 32),
226 writel((u32) etdev->tx_ring.tx_desc_ring_pa,
229 /* Initialise the transmit DMA engine */
230 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des.value);
232 /* Load the completion writeback physical address */
233 writel((u32)((u64)etdev->tx_ring.pTxStatusPa >> 32),
234 &txdma->dma_wb_base_hi);
235 writel((u32)etdev->tx_ring.pTxStatusPa, &txdma->dma_wb_base_lo);
237 memset(etdev->tx_ring.pTxStatusVa, 0, sizeof(TX_STATUS_BLOCK_t));
239 writel(0, &txdma->service_request);
240 etdev->tx_ring.txDmaReadyToSend = 0;
244 * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310
245 * @etdev: pointer to our adapter structure
247 void et131x_tx_dma_disable(struct et131x_adapter *etdev)
249 /* Setup the tramsmit dma configuration register */
250 writel(ET_TXDMA_CSR_HALT|ET_TXDMA_SNGL_EPKT,
251 &etdev->regs->txdma.csr);
255 * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
256 * @etdev: pointer to our adapter structure
258 * Mainly used after a return to the D0 (full-power) state from a lower state.
260 void et131x_tx_dma_enable(struct et131x_adapter *etdev)
262 /* Setup the transmit dma configuration register for normal
265 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
266 &etdev->regs->txdma.csr);
270 * et131x_init_send - Initialize send data structures
271 * @adapter: pointer to our private adapter structure
273 void et131x_init_send(struct et131x_adapter *adapter)
277 struct tx_ring *tx_ring;
279 /* Setup some convenience pointers */
280 tx_ring = &adapter->tx_ring;
281 tcb = adapter->tx_ring.MpTcbMem;
283 tx_ring->TCBReadyQueueHead = tcb;
285 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
287 /* Go through and set up each TCB */
288 for (ct = 0; ct++ < NUM_TCB; tcb++) {
289 /* Set the link pointer in HW TCB to the next TCB in the
290 * chain. If this is the last TCB in the chain, also set the
296 tx_ring->TCBReadyQueueTail = tcb;
298 /* Curr send queue should now be empty */
299 tx_ring->CurrSendHead = NULL;
300 tx_ring->CurrSendTail = NULL;
304 * et131x_send_packets - This function is called by the OS to send packets
305 * @skb: the packet(s) to send
306 * @netdev:device on which to TX the above packet(s)
308 * Return 0 in almost all cases; non-zero value in extreme hard failure only
310 int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
313 struct et131x_adapter *etdev = NULL;
315 etdev = netdev_priv(netdev);
317 /* Send these packets
319 * NOTE: The Linux Tx entry point is only given one packet at a time
320 * to Tx, so the PacketCount and it's array used makes no sense here
323 /* TCB is not available */
324 if (etdev->tx_ring.nBusySend >= NUM_TCB) {
325 /* NOTE: If there's an error on send, no need to queue the
326 * packet under Linux; if we just send an error up to the
327 * netif layer, it will resend the skb to us.
331 /* We need to see if the link is up; if it's not, make the
332 * netif layer think we're good and drop the packet
334 if ((etdev->Flags & fMP_ADAPTER_FAIL_SEND_MASK) ||
335 !netif_carrier_ok(netdev)) {
336 dev_kfree_skb_any(skb);
339 etdev->net_stats.tx_dropped++;
341 status = et131x_send_packet(skb, etdev);
342 if (status != 0 && status != -ENOMEM) {
343 /* On any other error, make netif think we're
344 * OK and drop the packet
346 dev_kfree_skb_any(skb);
348 etdev->net_stats.tx_dropped++;
356 * et131x_send_packet - Do the work to send a packet
357 * @skb: the packet(s) to send
358 * @etdev: a pointer to the device's private adapter structure
360 * Return 0 in almost all cases; non-zero value in extreme hard failure only.
362 * Assumption: Send spinlock has been acquired
364 static int et131x_send_packet(struct sk_buff *skb,
365 struct et131x_adapter *etdev)
368 struct tcb *tcb = NULL;
372 /* All packets must have at least a MAC address and a protocol type */
373 if (skb->len < ETH_HLEN)
376 /* Get a TCB for this packet */
377 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
379 tcb = etdev->tx_ring.TCBReadyQueueHead;
382 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
386 etdev->tx_ring.TCBReadyQueueHead = tcb->Next;
388 if (etdev->tx_ring.TCBReadyQueueHead == NULL)
389 etdev->tx_ring.TCBReadyQueueTail = NULL;
391 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
393 tcb->PacketLength = skb->len;
396 if ((skb->data != NULL) && ((skb->len - skb->data_len) >= 6)) {
397 shbufva = (u16 *) skb->data;
399 if ((shbufva[0] == 0xffff) &&
400 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) {
401 tcb->Flags |= fMP_DEST_BROAD;
402 } else if ((shbufva[0] & 0x3) == 0x0001) {
403 tcb->Flags |= fMP_DEST_MULTI;
409 /* Call the NIC specific send handler. */
410 status = nic_send_packet(etdev, tcb);
413 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
415 if (etdev->tx_ring.TCBReadyQueueTail) {
416 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
418 /* Apparently ready Q is empty. */
419 etdev->tx_ring.TCBReadyQueueHead = tcb;
422 etdev->tx_ring.TCBReadyQueueTail = tcb;
423 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
426 WARN_ON(etdev->tx_ring.nBusySend > NUM_TCB);
431 * nic_send_packet - NIC specific send handler for version B silicon.
432 * @etdev: pointer to our adapter
433 * @tcb: pointer to struct tcb
435 * Returns 0 or errno.
437 static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
440 struct tx_desc desc[24]; /* 24 x 16 byte */
442 u32 thiscopy, remainder;
443 struct sk_buff *skb = tcb->Packet;
444 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
445 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
448 /* Part of the optimizations of this send routine restrict us to
449 * sending 24 fragments at a pass. In practice we should never see
450 * more than 5 fragments.
452 * NOTE: The older version of this function (below) can handle any
453 * number of fragments. If needed, we can call this function,
454 * although it is less efficient.
459 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
461 for (i = 0; i < nr_frags; i++) {
462 /* If there is something in this element, lets get a
463 * descriptor from the ring and get the necessary data
466 /* If the fragments are smaller than a standard MTU,
467 * then map them to a single descriptor in the Tx
468 * Desc ring. However, if they're larger, as is
469 * possible with support for jumbo packets, then
470 * split them each across 2 descriptors.
472 * This will work until we determine why the hardware
473 * doesn't seem to like large fragments.
475 if ((skb->len - skb->data_len) <= 1514) {
476 desc[frag].addr_hi = 0;
477 /* Low 16bits are length, high is vlan and
478 unused currently so zero */
479 desc[frag].len_vlan =
480 skb->len - skb->data_len;
482 /* NOTE: Here, the dma_addr_t returned from
483 * pci_map_single() is implicitly cast as a
484 * u32. Although dma_addr_t can be
485 * 64-bit, the address returned by
486 * pci_map_single() is always 32-bit
487 * addressable (as defined by the pci/dma
490 desc[frag++].addr_lo =
491 pci_map_single(etdev->pdev,
497 desc[frag].addr_hi = 0;
498 desc[frag].len_vlan =
499 (skb->len - skb->data_len) / 2;
501 /* NOTE: Here, the dma_addr_t returned from
502 * pci_map_single() is implicitly cast as a
503 * u32. Although dma_addr_t can be
504 * 64-bit, the address returned by
505 * pci_map_single() is always 32-bit
506 * addressable (as defined by the pci/dma
509 desc[frag++].addr_lo =
510 pci_map_single(etdev->pdev,
515 desc[frag].addr_hi = 0;
517 desc[frag].len_vlan =
518 (skb->len - skb->data_len) / 2;
520 /* NOTE: Here, the dma_addr_t returned from
521 * pci_map_single() is implicitly cast as a
522 * u32. Although dma_addr_t can be
523 * 64-bit, the address returned by
524 * pci_map_single() is always 32-bit
525 * addressable (as defined by the pci/dma
528 desc[frag++].addr_lo =
529 pci_map_single(etdev->pdev,
538 desc[frag].addr_hi = 0;
539 desc[frag].len_vlan =
542 /* NOTE: Here, the dma_addr_t returned from
543 * pci_map_page() is implicitly cast as a u32.
544 * Although dma_addr_t can be 64-bit, the address
545 * returned by pci_map_page() is always 32-bit
546 * addressable (as defined by the pci/dma subsystem)
548 desc[frag++].addr_lo =
549 pci_map_page(etdev->pdev,
551 frags[i - 1].page_offset,
560 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
561 if (++etdev->tx_ring.TxPacketsSinceLastinterrupt ==
562 PARM_TX_NUM_BUFS_DEF) {
563 /* Last element & Interrupt flag */
564 desc[frag - 1].flags = 0x5;
565 etdev->tx_ring.TxPacketsSinceLastinterrupt = 0;
566 } else { /* Last element */
567 desc[frag - 1].flags = 0x1;
570 desc[frag - 1].flags = 0x5;
572 desc[0].flags |= 2; /* First element flag */
574 tcb->WrIndexStart = etdev->tx_ring.txDmaReadyToSend;
575 tcb->PacketStaleCount = 0;
577 spin_lock_irqsave(&etdev->SendHWLock, flags);
579 thiscopy = NUM_DESC_PER_RING_TX -
580 INDEX10(etdev->tx_ring.txDmaReadyToSend);
582 if (thiscopy >= frag) {
586 remainder = frag - thiscopy;
589 memcpy(etdev->tx_ring.tx_desc_ring +
590 INDEX10(etdev->tx_ring.txDmaReadyToSend), desc,
591 sizeof(struct tx_desc) * thiscopy);
593 add_10bit(&etdev->tx_ring.txDmaReadyToSend, thiscopy);
595 if (INDEX10(etdev->tx_ring.txDmaReadyToSend)== 0 ||
596 INDEX10(etdev->tx_ring.txDmaReadyToSend) == NUM_DESC_PER_RING_TX) {
597 etdev->tx_ring.txDmaReadyToSend &= ~ET_DMA10_MASK;
598 etdev->tx_ring.txDmaReadyToSend ^= ET_DMA10_WRAP;
602 memcpy(etdev->tx_ring.tx_desc_ring,
604 sizeof(struct tx_desc) * remainder);
606 add_10bit(&etdev->tx_ring.txDmaReadyToSend, remainder);
609 if (INDEX10(etdev->tx_ring.txDmaReadyToSend) == 0) {
610 if (etdev->tx_ring.txDmaReadyToSend)
611 tcb->WrIndex = NUM_DESC_PER_RING_TX - 1;
613 tcb->WrIndex= ET_DMA10_WRAP | (NUM_DESC_PER_RING_TX - 1);
615 tcb->WrIndex = etdev->tx_ring.txDmaReadyToSend - 1;
617 spin_lock(&etdev->TCBSendQLock);
619 if (etdev->tx_ring.CurrSendTail)
620 etdev->tx_ring.CurrSendTail->Next = tcb;
622 etdev->tx_ring.CurrSendHead = tcb;
624 etdev->tx_ring.CurrSendTail = tcb;
626 WARN_ON(tcb->Next != NULL);
628 etdev->tx_ring.nBusySend++;
630 spin_unlock(&etdev->TCBSendQLock);
632 /* Write the new write pointer back to the device. */
633 writel(etdev->tx_ring.txDmaReadyToSend,
634 &etdev->regs->txdma.service_request);
636 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
637 * timer to wake us up if this packet isn't followed by N more.
639 if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS) {
640 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
641 &etdev->regs->global.watchdog_timer);
643 spin_unlock_irqrestore(&etdev->SendHWLock, flags);
650 * et131x_free_send_packet - Recycle a struct tcb
651 * @etdev: pointer to our adapter
652 * @tcb: pointer to struct tcb
654 * Complete the packet if necessary
655 * Assumption - Send spinlock has been acquired
657 inline void et131x_free_send_packet(struct et131x_adapter *etdev,
661 struct tx_desc *desc = NULL;
662 struct net_device_stats *stats = &etdev->net_stats;
664 if (tcb->Flags & fMP_DEST_BROAD)
665 atomic_inc(&etdev->Stats.brdcstxmt);
666 else if (tcb->Flags & fMP_DEST_MULTI)
667 atomic_inc(&etdev->Stats.multixmt);
669 atomic_inc(&etdev->Stats.unixmt);
672 stats->tx_bytes += tcb->Packet->len;
674 /* Iterate through the TX descriptors on the ring
675 * corresponding to this packet and umap the fragments
679 desc =(struct tx_desc *) (etdev->tx_ring.tx_desc_ring +
680 INDEX10(tcb->WrIndexStart));
682 pci_unmap_single(etdev->pdev,
684 desc->len_vlan, PCI_DMA_TODEVICE);
686 add_10bit(&tcb->WrIndexStart, 1);
687 if (INDEX10(tcb->WrIndexStart) >=
688 NUM_DESC_PER_RING_TX) {
689 tcb->WrIndexStart &= ~ET_DMA10_MASK;
690 tcb->WrIndexStart ^= ET_DMA10_WRAP;
692 } while (desc != (etdev->tx_ring.tx_desc_ring +
693 INDEX10(tcb->WrIndex)));
695 dev_kfree_skb_any(tcb->Packet);
698 memset(tcb, 0, sizeof(struct tcb));
700 /* Add the TCB to the Ready Q */
701 spin_lock_irqsave(&etdev->TCBReadyQLock, flags);
703 etdev->Stats.opackets++;
705 if (etdev->tx_ring.TCBReadyQueueTail)
706 etdev->tx_ring.TCBReadyQueueTail->Next = tcb;
708 /* Apparently ready Q is empty. */
709 etdev->tx_ring.TCBReadyQueueHead = tcb;
711 etdev->tx_ring.TCBReadyQueueTail = tcb;
713 spin_unlock_irqrestore(&etdev->TCBReadyQLock, flags);
714 WARN_ON(etdev->tx_ring.nBusySend < 0);
718 * et131x_free_busy_send_packets - Free and complete the stopped active sends
719 * @etdev: pointer to our adapter
721 * Assumption - Send spinlock has been acquired
723 void et131x_free_busy_send_packets(struct et131x_adapter *etdev)
729 /* Any packets being sent? Check the first TCB on the send list */
730 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
732 tcb = etdev->tx_ring.CurrSendHead;
734 while ((tcb != NULL) && (freed < NUM_TCB)) {
735 struct tcb *pNext = tcb->Next;
737 etdev->tx_ring.CurrSendHead = pNext;
740 etdev->tx_ring.CurrSendTail = NULL;
742 etdev->tx_ring.nBusySend--;
744 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
747 et131x_free_send_packet(etdev, tcb);
749 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
751 tcb = etdev->tx_ring.CurrSendHead;
754 WARN_ON(freed == NUM_TCB);
756 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
758 etdev->tx_ring.nBusySend = 0;
762 * et131x_handle_send_interrupt - Interrupt handler for sending processing
763 * @etdev: pointer to our adapter
765 * Re-claim the send resources, complete sends and get more to send from
766 * the send wait queue.
768 * Assumption - Send spinlock has been acquired
770 void et131x_handle_send_interrupt(struct et131x_adapter *etdev)
777 serviced = readl(&etdev->regs->txdma.NewServiceComplete);
778 index = INDEX10(serviced);
780 /* Has the ring wrapped? Process any descriptors that do not have
781 * the same "wrap" indicator as the current completion indicator
783 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
785 tcb = etdev->tx_ring.CurrSendHead;
788 ((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP) &&
789 index < INDEX10(tcb->WrIndex)) {
790 etdev->tx_ring.nBusySend--;
791 etdev->tx_ring.CurrSendHead = tcb->Next;
792 if (tcb->Next == NULL)
793 etdev->tx_ring.CurrSendTail = NULL;
795 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
796 et131x_free_send_packet(etdev, tcb);
797 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
799 /* Goto the next packet */
800 tcb = etdev->tx_ring.CurrSendHead;
803 !((serviced ^ tcb->WrIndex) & ET_DMA10_WRAP)
804 && index > (tcb->WrIndex & ET_DMA10_MASK)) {
805 etdev->tx_ring.nBusySend--;
806 etdev->tx_ring.CurrSendHead = tcb->Next;
807 if (tcb->Next == NULL)
808 etdev->tx_ring.CurrSendTail = NULL;
810 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);
811 et131x_free_send_packet(etdev, tcb);
812 spin_lock_irqsave(&etdev->TCBSendQLock, flags);
814 /* Goto the next packet */
815 tcb = etdev->tx_ring.CurrSendHead;
818 /* Wake up the queue when we hit a low-water mark */
819 if (etdev->tx_ring.nBusySend <= (NUM_TCB / 3))
820 netif_wake_queue(etdev->netdev);
822 spin_unlock_irqrestore(&etdev->TCBSendQLock, flags);