2 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 * Copyright © 2005 Agere Systems Inc.
8 * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
10 *------------------------------------------------------------------------------
14 * This software is provided subject to the following terms and conditions,
15 * which you should read carefully before using the software. Using this
16 * software indicates your acceptance of these terms and conditions. If you do
17 * not agree with these terms and conditions, do not use the software.
19 * Copyright © 2005 Agere Systems Inc.
20 * All rights reserved.
22 * Redistribution and use in source or binary forms, with or without
23 * modifications, are permitted provided that the following conditions are met:
25 * . Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following Disclaimer as comments in the code as
27 * well as in the documentation and/or other materials provided with the
30 * . Redistributions in binary form must reproduce the above copyright notice,
31 * this list of conditions and the following Disclaimer in the documentation
32 * and/or other materials provided with the distribution.
34 * . Neither the name of Agere Systems Inc. nor the names of the contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
41 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
42 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
43 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
44 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/pci.h>
57 #include <linux/init.h>
58 #include <linux/module.h>
59 #include <linux/types.h>
60 #include <linux/kernel.h>
62 #include <linux/sched.h>
63 #include <linux/ptrace.h>
64 #include <linux/slab.h>
65 #include <linux/ctype.h>
66 #include <linux/string.h>
67 #include <linux/timer.h>
68 #include <linux/interrupt.h>
70 #include <linux/delay.h>
71 #include <linux/bitops.h>
74 #include <linux/netdevice.h>
75 #include <linux/etherdevice.h>
76 #include <linux/skbuff.h>
77 #include <linux/if_arp.h>
78 #include <linux/ioport.h>
79 #include <linux/crc32.h>
80 #include <linux/random.h>
81 #include <linux/phy.h>
85 MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
86 MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
87 MODULE_LICENSE("Dual BSD/GPL");
88 MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
91 #define MAX_NUM_REGISTER_POLLS 1000
92 #define MAX_NUM_WRITE_RETRIES 2
95 #define COUNTER_WRAP_16_BIT 0x10000
96 #define COUNTER_WRAP_12_BIT 0x1000
99 #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
100 #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
103 /* For interrupts, normal running is:
104 * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
105 * watchdog_interrupt & txdma_xfer_done
107 * In both cases, when flow control is enabled for either Tx or bi-direction,
108 * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
109 * buffer rings are running low.
111 #define INT_MASK_DISABLE 0xffffffff
113 /* NOTE: Masking out MAC_STAT Interrupt for now...
114 * #define INT_MASK_ENABLE 0xfff6bf17
115 * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
117 #define INT_MASK_ENABLE 0xfffebf17
118 #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
120 /* General defines */
121 /* Packet and header sizes */
122 #define NIC_MIN_PACKET_SIZE 60
124 /* Multicast list size */
125 #define NIC_MAX_MCAST_LIST 128
127 /* Supported Filters */
128 #define ET131X_PACKET_TYPE_DIRECTED 0x0001
129 #define ET131X_PACKET_TYPE_MULTICAST 0x0002
130 #define ET131X_PACKET_TYPE_BROADCAST 0x0004
131 #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
132 #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
135 #define ET131X_TX_TIMEOUT (1 * HZ)
136 #define NIC_SEND_HANG_THRESHOLD 0
139 #define FMP_DEST_MULTI 0x00000001
140 #define FMP_DEST_BROAD 0x00000002
142 /* MP_ADAPTER flags */
143 #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
145 /* MP_SHARED flags */
146 #define FMP_ADAPTER_LOWER_POWER 0x00200000
148 #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
149 #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
151 #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
153 /* Some offsets in PCI config space that are actually used. */
154 #define ET1310_PCI_MAC_ADDRESS 0xA4
155 #define ET1310_PCI_EEPROM_STATUS 0xB2
156 #define ET1310_PCI_ACK_NACK 0xC0
157 #define ET1310_PCI_REPLAY 0xC2
158 #define ET1310_PCI_L0L1LATENCY 0xCF
160 /* PCI Product IDs */
161 #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
162 #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
164 /* Define order of magnitude converter */
165 #define NANO_IN_A_MICRO 1000
167 #define PARM_RX_NUM_BUFS_DEF 4
168 #define PARM_RX_TIME_INT_DEF 10
169 #define PARM_RX_MEM_END_DEF 0x2bc
170 #define PARM_TX_TIME_INT_DEF 40
171 #define PARM_TX_NUM_BUFS_DEF 4
172 #define PARM_DMA_CACHE_DEF 0
175 #define FBR_CHUNKS 32
176 #define MAX_DESC_PER_RING_RX 1024
178 /* number of RFDs - default and min */
179 #define RFD_LOW_WATER_MARK 40
180 #define NIC_DEFAULT_NUM_RFD 1024
183 #define NUM_PACKETS_HANDLED 256
185 #define ALCATEL_MULTICAST_PKT 0x01000000
186 #define ALCATEL_BROADCAST_PKT 0x02000000
188 /* typedefs for Free Buffer Descriptors */
192 u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
195 /* Packet Status Ring Descriptors
199 * top 16 bits are from the Alcatel Status Word as enumerated in
200 * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
203 * 1: ipa IP checksum assist
204 * 2: ipp IP checksum pass
205 * 3: tcpa TCP checksum assist
206 * 4: tcpp TCP checksum pass
208 * 6: rxmac_error RXMAC Error Indicator
209 * 7: drop Drop packet
210 * 8: ft Frame Truncated
214 * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
215 * 17: asw_RX_DV_event short receive event detected
216 * 18: asw_false_carrier_event bad carrier since last good packet
217 * 19: asw_code_err one or more nibbles signalled as errors
218 * 20: asw_CRC_err CRC error
219 * 21: asw_len_chk_err frame length field incorrect
220 * 22: asw_too_long frame length > 1518 bytes
221 * 23: asw_OK valid CRC + no code error
222 * 24: asw_multicast has a multicast address
223 * 25: asw_broadcast has a broadcast address
224 * 26: asw_dribble_nibble spurious bits after EOP
225 * 27: asw_control_frame is a control frame
226 * 28: asw_pause_frame is a pause frame
227 * 29: asw_unsupported_op unsupported OP code
228 * 30: asw_VLAN_tag VLAN tag detected
229 * 31: asw_long_evt Rx long event
232 * 0-15: length length in bytes
233 * 16-25: bi Buffer Index
234 * 26-27: ri Ring Index
238 struct pkt_stat_desc {
243 /* Typedefs for the RX DMA status word */
245 /* rx status word 0 holds part of the status bits of the Rx DMA engine
246 * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
247 * which contains the Free Buffer ring 0 and 1 available offset.
249 * bit 0-9 FBR1 offset
250 * bit 10 Wrap flag for FBR1
251 * bit 16-25 FBR0 offset
252 * bit 26 Wrap flag for FBR0
255 /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
256 * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
257 * which contains the Packet Status Ring available offset.
260 * bit 16-27 PSRoffset
265 /* struct rx_status_block is a structure representing the status of the Rx
266 * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
268 struct rx_status_block {
273 /* Structure for look-up table holding free buffer ring pointers, addresses
277 void *virt[MAX_DESC_PER_RING_RX];
278 u32 bus_high[MAX_DESC_PER_RING_RX];
279 u32 bus_low[MAX_DESC_PER_RING_RX];
281 dma_addr_t ring_physaddr;
282 void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
283 dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
289 /* struct rx_ring is the sructure representing the adaptor's local
290 * reference(s) to the rings
293 struct fbr_lookup *fbr[NUM_FBRS];
294 void *ps_ring_virtaddr;
295 dma_addr_t ps_ring_physaddr;
299 struct rx_status_block *rx_status_block;
300 dma_addr_t rx_status_bus;
303 struct list_head recv_list;
308 bool unfinished_receives;
312 /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
314 * 0-15: length of packet
317 * 29-31: VLAN priority
319 * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
321 * 0: last packet in the sequence
322 * 1: first packet in the sequence
323 * 2: interrupt the processor when this pkt sent
324 * 3: Control word - no packet data
325 * 4: Issue half-duplex backpressure : XON/XOFF
326 * 5: send pause frame
327 * 6: Tx frame has error
331 * 10: Packet is a Huge packet
332 * 11: append VLAN tag
333 * 12: IP checksum assist
334 * 13: TCP checksum assist
335 * 14: UDP checksum assist
338 #define TXDESC_FLAG_LASTPKT 0x0001
339 #define TXDESC_FLAG_FIRSTPKT 0x0002
340 #define TXDESC_FLAG_INTPROC 0x0004
342 /* struct tx_desc represents each descriptor on the ring */
346 u32 len_vlan; /* control words how to xmit the */
347 u32 flags; /* data (detailed above) */
350 /* The status of the Tx DMA engine it sits in free memory, and is pointed to
351 * by 0x101c / 0x1020. This is a DMA10 type
354 /* TCB (Transmit Control Block: Host Side) */
356 struct tcb *next; /* Next entry in ring */
357 u32 flags; /* Our flags for the packet */
358 u32 count; /* Used to spot stuck/lost packets */
359 u32 stale; /* Used to spot stuck/lost packets */
360 struct sk_buff *skb; /* Network skb we are tied to */
361 u32 index; /* Ring indexes */
365 /* Structure representing our local reference(s) to the ring */
367 /* TCB (Transmit Control Block) memory and lists */
368 struct tcb *tcb_ring;
370 /* List of TCBs that are ready to be used */
371 struct tcb *tcb_qhead;
372 struct tcb *tcb_qtail;
374 /* list of TCBs that are currently being sent. NOTE that access to all
375 * three of these (including used) are controlled via the
376 * TCBSendQLock. This lock should be secured prior to incementing /
377 * decrementing used, or any queue manipulation on send_head /
380 struct tcb *send_head;
381 struct tcb *send_tail;
384 /* The actual descriptor ring */
385 struct tx_desc *tx_desc_ring;
386 dma_addr_t tx_desc_ring_pa;
388 /* send_idx indicates where we last wrote to in the descriptor ring. */
391 /* The location of the write-back status block */
393 dma_addr_t tx_status_pa;
395 /* Packets since the last IRQ: used for interrupt coalescing */
399 /* Do not change these values: if changed, then change also in respective
400 * TXdma and Rxdma engines
402 #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
405 /* These values are all superseded by registry entries to facilitate tuning.
406 * Once the desired performance has been achieved, the optimal registry values
407 * should be re-populated to these #defines:
409 #define TX_ERROR_PERIOD 1000
411 #define LO_MARK_PERCENT_FOR_PSR 15
412 #define LO_MARK_PERCENT_FOR_RX 15
414 /* RFD (Receive Frame Descriptor) */
416 struct list_head list_node;
418 u32 len; /* total size of receive frame */
425 #define FLOW_TXONLY 1
426 #define FLOW_RXONLY 2
429 /* Struct to define some device statistics */
433 * NOTE: atomic_t types are only guaranteed to store 24-bits; if we
434 * MUST have 32, then we'll need another way to perform atomic
437 u32 unicast_pkts_rcvd;
438 atomic_t unicast_pkts_xmtd;
439 u32 multicast_pkts_rcvd;
440 atomic_t multicast_pkts_xmtd;
441 u32 broadcast_pkts_rcvd;
442 atomic_t broadcast_pkts_xmtd;
443 u32 rcvd_pkts_dropped;
449 u32 tx_excessive_collisions;
450 u32 tx_first_collisions;
451 u32 tx_late_collisions;
461 u32 rx_code_violations;
464 u32 synchronous_iterations;
465 u32 interrupt_status;
468 /* The private adapter structure */
469 struct et131x_adapter {
470 struct net_device *netdev;
471 struct pci_dev *pdev;
472 struct mii_bus *mii_bus;
473 struct phy_device *phydev;
474 struct work_struct task;
476 /* Flags that indicate current state of the adapter */
479 /* local link state, to determine if a state change has occurred */
483 u8 rom_addr[ETH_ALEN];
491 spinlock_t tcb_send_qlock;
492 spinlock_t tcb_ready_qlock;
493 spinlock_t send_hw_lock;
498 /* Packet Filter and look ahead size */
502 u32 multicast_addr_count;
503 u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
505 /* Pointer to the device's PCI register space */
506 struct address_map __iomem *regs;
508 /* Registry parameters */
509 u8 wanted_flow; /* Flow we want for 802.3x flow control */
510 u32 registry_jumbo_packet; /* Max supported ethernet packet size */
512 /* Derived from the registry: */
513 u8 flowcontrol; /* flow control validated by the far-end */
515 /* Minimize init-time */
516 struct timer_list error_timer;
518 /* variable putting the phy into coma mode when boot up with no cable
519 * plugged in after 5 seconds
523 /* Next two used to save power information at power down. This
524 * information will be used during power up to set up parts of Power
525 * Management in JAGCore
530 /* Tx Memory Variables */
531 struct tx_ring tx_ring;
533 /* Rx Memory Variables */
534 struct rx_ring rx_ring;
537 struct ce_stats stats;
539 struct net_device_stats net_stats;
542 static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
547 /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
548 * bits 7,1:0 both equal to 1, at least once after reset.
549 * Subsequent operations need only to check that bits 1:0 are equal
550 * to 1 prior to starting a single byte read/write
553 for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
554 /* Read registers grouped in DWORD1 */
555 if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
558 /* I2C idle and Phy Queue Avail both true */
559 if ((reg & 0x3000) == 0x3000) {
568 /* eeprom_write - Write a byte to the ET1310's EEPROM
569 * @adapter: pointer to our private adapter structure
570 * @addr: the address to write
571 * @data: the value to write
573 * Returns 1 for a successful write.
575 static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
577 struct pci_dev *pdev = adapter->pdev;
586 /* For an EEPROM, an I2C single byte write is defined as a START
587 * condition followed by the device address, EEPROM address, one byte
588 * of data and a STOP condition. The STOP condition will trigger the
589 * EEPROM's internally timed write cycle to the nonvolatile memory.
590 * All inputs are disabled during this write cycle and the EEPROM will
591 * not respond to any access until the internal write is complete.
594 err = eeprom_wait_ready(pdev, NULL);
598 /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
599 * and bits 1:0 both =0. Bit 5 should be set according to the
600 * type of EEPROM being accessed (1=two byte addressing, 0=one
603 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
604 LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE))
609 /* Prepare EEPROM address for Step 3 */
611 for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
612 /* Write the address to the LBCIF Address Register */
613 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
615 /* Write the data to the LBCIF Data Register (the I2C write
618 if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
620 /* Monitor bit 1:0 of the LBCIF Status Register. When bits
621 * 1:0 are both equal to 1, the I2C write has completed and the
622 * internal write cycle of the EEPROM is about to start.
623 * (bits 1:0 = 01 is a legal state while waiting from both
624 * equal to 1, but bits 1:0 = 10 is invalid and implies that
625 * something is broken).
627 err = eeprom_wait_ready(pdev, &status);
631 /* Check bit 3 of the LBCIF Status Register. If equal to 1,
632 * an error has occurred.Don't break here if we are revision
633 * 1, this is so we do a blind write for load bug.
635 if ((status & LBCIF_STATUS_GENERAL_ERROR)
636 && adapter->pdev->revision == 0)
639 /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
640 * ACK error has occurred on the address phase of the write.
641 * This could be due to an actual hardware failure or the
642 * EEPROM may still be in its internal write cycle from a
643 * previous write. This write operation was ignored and must be
646 if (status & LBCIF_STATUS_ACK_ERROR) {
647 /* This could be due to an actual hardware failure
648 * or the EEPROM may still be in its internal write
649 * cycle from a previous write. This write operation
650 * was ignored and must be repeated later.
660 /* Set bit 6 of the LBCIF Control Register = 0.
665 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
666 LBCIF_CONTROL_LBCIF_ENABLE))
669 /* Do read until internal ACK_ERROR goes away meaning write
673 pci_write_config_dword(pdev,
674 LBCIF_ADDRESS_REGISTER,
677 pci_read_config_dword(pdev,
678 LBCIF_DATA_REGISTER, &val);
679 } while ((val & 0x00010000) == 0);
680 } while (val & 0x00040000);
682 if ((val & 0xFF00) != 0xC000 || index == 10000)
686 return writeok ? 0 : -EIO;
689 /* eeprom_read - Read a byte from the ET1310's EEPROM
690 * @adapter: pointer to our private adapter structure
691 * @addr: the address from which to read
692 * @pdata: a pointer to a byte in which to store the value of the read
693 * @eeprom_id: the ID of the EEPROM
694 * @addrmode: how the EEPROM is to be accessed
696 * Returns 1 for a successful read
698 static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
700 struct pci_dev *pdev = adapter->pdev;
704 /* A single byte read is similar to the single byte write, with the
705 * exception of the data flow:
708 err = eeprom_wait_ready(pdev, NULL);
711 /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
712 * and bits 1:0 both =0. Bit 5 should be set according to the type
713 * of EEPROM being accessed (1=two byte addressing, 0=one byte
716 if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
717 LBCIF_CONTROL_LBCIF_ENABLE))
719 /* Write the address to the LBCIF Address Register (I2C read will
722 if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
724 /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
725 * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
728 err = eeprom_wait_ready(pdev, &status);
731 /* Regardless of error status, read data byte from LBCIF Data
735 /* Check bit 2 of the LBCIF Status Register. If = 1,
736 * then an error has occurred.
738 return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
741 static int et131x_init_eeprom(struct et131x_adapter *adapter)
743 struct pci_dev *pdev = adapter->pdev;
746 /* We first need to check the EEPROM Status code located at offset
747 * 0xB2 of config space
749 pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
751 /* THIS IS A WORKAROUND:
752 * I need to call this function twice to get my card in a
753 * LG M1 Express Dual running. I tried also a msleep before this
754 * function, because I thought there could be some time conditions
755 * but it didn't work. Call the whole function twice also work.
757 if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
759 "Could not read PCI config space for EEPROM Status\n");
763 /* Determine if the error(s) we care about are present. If they are
764 * present we need to fail.
766 if (eestatus & 0x4C) {
767 int write_failed = 0;
768 if (pdev->revision == 0x01) {
770 static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
772 /* Re-write the first 4 bytes if we have an eeprom
773 * present and the revision id is 1, this fixes the
774 * corruption seen with 1310 B Silicon
776 for (i = 0; i < 3; i++)
777 if (eeprom_write(adapter, i, eedata[i]) < 0)
780 if (pdev->revision != 0x01 || write_failed) {
782 "Fatal EEPROM Status Error - 0x%04x\n", eestatus);
784 /* This error could mean that there was an error
785 * reading the eeprom or that the eeprom doesn't exist.
786 * We will treat each case the same and not try to
787 * gather additional information that normally would
788 * come from the eeprom, like MAC Address
790 adapter->has_eeprom = 0;
794 adapter->has_eeprom = 1;
796 /* Read the EEPROM for information regarding LED behavior. Refer to
797 * ET1310_phy.c, et131x_xcvr_init(), for its use.
799 eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
800 eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
802 if (adapter->eeprom_data[0] != 0xcd)
803 /* Disable all optional features */
804 adapter->eeprom_data[1] = 0x00;
809 /* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
810 * @adapter: pointer to our adapter structure
812 static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
814 /* Setup the receive dma configuration register for normal operation */
815 u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
817 if (adapter->rx_ring.fbr[1]->buffsize == 4096)
818 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
819 else if (adapter->rx_ring.fbr[1]->buffsize == 8192)
820 csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
821 else if (adapter->rx_ring.fbr[1]->buffsize == 16384)
822 csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
824 csr |= ET_RXDMA_CSR_FBR0_ENABLE;
825 if (adapter->rx_ring.fbr[0]->buffsize == 256)
826 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
827 else if (adapter->rx_ring.fbr[0]->buffsize == 512)
828 csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
829 else if (adapter->rx_ring.fbr[0]->buffsize == 1024)
830 csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
831 writel(csr, &adapter->regs->rxdma.csr);
833 csr = readl(&adapter->regs->rxdma.csr);
834 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
836 csr = readl(&adapter->regs->rxdma.csr);
837 if (csr & ET_RXDMA_CSR_HALT_STATUS) {
838 dev_err(&adapter->pdev->dev,
839 "RX Dma failed to exit halt state. CSR 0x%08x\n",
845 /* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
846 * @adapter: pointer to our adapter structure
848 static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
851 /* Setup the receive dma configuration register */
852 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
853 &adapter->regs->rxdma.csr);
854 csr = readl(&adapter->regs->rxdma.csr);
855 if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
857 csr = readl(&adapter->regs->rxdma.csr);
858 if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
859 dev_err(&adapter->pdev->dev,
860 "RX Dma failed to enter halt state. CSR 0x%08x\n",
865 /* et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310.
866 * @adapter: pointer to our adapter structure
868 * Mainly used after a return to the D0 (full-power) state from a lower state.
870 static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
872 /* Setup the transmit dma configuration register for normal
875 writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
876 &adapter->regs->txdma.csr);
879 static inline void add_10bit(u32 *v, int n)
881 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
884 static inline void add_12bit(u32 *v, int n)
886 *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
889 /* et1310_config_mac_regs1 - Initialize the first part of MAC regs
890 * @adapter: pointer to our adapter structure
892 static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
894 struct mac_regs __iomem *macregs = &adapter->regs->mac;
899 /* First we need to reset everything. Write to MAC configuration
900 * register 1 to perform reset.
902 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
903 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
904 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
907 /* Next lets configure the MAC Inter-packet gap register */
908 ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
909 ipg |= 0x50 << 8; /* ifg enforce 0x50 */
910 writel(ipg, ¯egs->ipg);
912 /* Next lets configure the MAC Half Duplex register */
913 /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
914 writel(0x00A1F037, ¯egs->hfdp);
916 /* Next lets configure the MAC Interface Control register */
917 writel(0, ¯egs->if_ctrl);
919 /* Let's move on to setting up the mii management configuration */
920 writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
922 /* Next lets configure the MAC Station Address register. These
923 * values are read from the EEPROM during initialization and stored
924 * in the adapter structure. We write what is stored in the adapter
925 * structure to the MAC Station Address registers high and low. This
926 * station address is used for generating and checking pause control
929 station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
930 (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
931 station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
932 (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
933 (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
935 writel(station1, ¯egs->station_addr_1);
936 writel(station2, ¯egs->station_addr_2);
938 /* Max ethernet packet in bytes that will be passed by the mac without
939 * being truncated. Allow the MAC to pass 4 more than our max packet
940 * size. This is 4 for the Ethernet CRC.
942 * Packets larger than (registry_jumbo_packet) that do not contain a
943 * VLAN ID will be dropped by the Rx function.
945 writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
947 /* clear out MAC config reset */
948 writel(0, ¯egs->cfg1);
951 /* et1310_config_mac_regs2 - Initialize the second part of MAC regs
952 * @adapter: pointer to our adapter structure
954 static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
957 struct mac_regs __iomem *mac = &adapter->regs->mac;
958 struct phy_device *phydev = adapter->phydev;
964 ctl = readl(&adapter->regs->txmac.ctl);
965 cfg1 = readl(&mac->cfg1);
966 cfg2 = readl(&mac->cfg2);
967 ifctrl = readl(&mac->if_ctrl);
969 /* Set up the if mode bits */
970 cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
971 if (phydev->speed == SPEED_1000) {
972 cfg2 |= ET_MAC_CFG2_IFMODE_1000;
974 ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
976 cfg2 |= ET_MAC_CFG2_IFMODE_100;
977 ifctrl |= ET_MAC_IFCTRL_PHYMODE;
980 /* We need to enable Rx/Tx */
981 cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
983 /* Initialize loop back to off */
984 cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
985 if (adapter->flowcontrol == FLOW_RXONLY ||
986 adapter->flowcontrol == FLOW_BOTH)
987 cfg1 |= ET_MAC_CFG1_RX_FLOW;
988 writel(cfg1, &mac->cfg1);
990 /* Now we need to initialize the MAC Configuration 2 register */
991 /* preamble 7, check length, huge frame off, pad crc, crc enable
994 cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
995 cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
996 cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
997 cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
998 cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
999 cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
1001 /* Turn on duplex if needed */
1002 if (phydev->duplex == DUPLEX_FULL)
1003 cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
1005 ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
1006 if (phydev->duplex == DUPLEX_HALF)
1007 ifctrl |= ET_MAC_IFCTRL_GHDMODE;
1009 writel(ifctrl, &mac->if_ctrl);
1010 writel(cfg2, &mac->cfg2);
1015 cfg1 = readl(&mac->cfg1);
1016 } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
1019 dev_warn(&adapter->pdev->dev,
1020 "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
1025 ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
1026 writel(ctl, &adapter->regs->txmac.ctl);
1028 /* Ready to start the RXDMA/TXDMA engine */
1029 if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
1030 et131x_rx_dma_enable(adapter);
1031 et131x_tx_dma_enable(adapter);
1035 /* et1310_in_phy_coma - check if the device is in phy coma
1036 * @adapter: pointer to our adapter structure
1038 * Returns 0 if the device is not in phy coma, 1 if it is in phy coma
1040 static int et1310_in_phy_coma(struct et131x_adapter *adapter)
1042 u32 pmcsr = readl(&adapter->regs->global.pm_csr);
1044 return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
1047 static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
1049 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1056 /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
1057 * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
1058 * specified) then we should pass NO multi-cast addresses to the
1061 if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
1064 /* Loop through our multicast array and set up the device */
1065 for (i = 0; i < adapter->multicast_addr_count; i++) {
1068 result = ether_crc(6, adapter->multicast_list[i]);
1070 result = (result & 0x3F800000) >> 23;
1073 hash1 |= (1 << result);
1074 } else if ((31 < result) && (result < 64)) {
1076 hash2 |= (1 << result);
1077 } else if ((63 < result) && (result < 96)) {
1079 hash3 |= (1 << result);
1082 hash4 |= (1 << result);
1087 /* Write out the new hash to the device */
1088 pm_csr = readl(&adapter->regs->global.pm_csr);
1089 if (!et1310_in_phy_coma(adapter)) {
1090 writel(hash1, &rxmac->multi_hash1);
1091 writel(hash2, &rxmac->multi_hash2);
1092 writel(hash3, &rxmac->multi_hash3);
1093 writel(hash4, &rxmac->multi_hash4);
1097 static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
1099 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1105 /* Set up unicast packet filter reg 3 to be the first two octets of
1106 * the MAC address for both address
1108 * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
1109 * MAC address for second address
1111 * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
1112 * MAC address for first address
1114 uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
1115 (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
1116 (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
1119 uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
1120 (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
1121 (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
1124 uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
1125 (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
1126 (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
1129 pm_csr = readl(&adapter->regs->global.pm_csr);
1130 if (!et1310_in_phy_coma(adapter)) {
1131 writel(uni_pf1, &rxmac->uni_pf_addr1);
1132 writel(uni_pf2, &rxmac->uni_pf_addr2);
1133 writel(uni_pf3, &rxmac->uni_pf_addr3);
1137 static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
1139 struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
1140 struct phy_device *phydev = adapter->phydev;
1145 /* Disable the MAC while it is being configured (also disable WOL) */
1146 writel(0x8, &rxmac->ctrl);
1148 /* Initialize WOL to disabled. */
1149 writel(0, &rxmac->crc0);
1150 writel(0, &rxmac->crc12);
1151 writel(0, &rxmac->crc34);
1153 /* We need to set the WOL mask0 - mask4 next. We initialize it to
1154 * its default Values of 0x00000000 because there are not WOL masks
1157 writel(0, &rxmac->mask0_word0);
1158 writel(0, &rxmac->mask0_word1);
1159 writel(0, &rxmac->mask0_word2);
1160 writel(0, &rxmac->mask0_word3);
1162 writel(0, &rxmac->mask1_word0);
1163 writel(0, &rxmac->mask1_word1);
1164 writel(0, &rxmac->mask1_word2);
1165 writel(0, &rxmac->mask1_word3);
1167 writel(0, &rxmac->mask2_word0);
1168 writel(0, &rxmac->mask2_word1);
1169 writel(0, &rxmac->mask2_word2);
1170 writel(0, &rxmac->mask2_word3);
1172 writel(0, &rxmac->mask3_word0);
1173 writel(0, &rxmac->mask3_word1);
1174 writel(0, &rxmac->mask3_word2);
1175 writel(0, &rxmac->mask3_word3);
1177 writel(0, &rxmac->mask4_word0);
1178 writel(0, &rxmac->mask4_word1);
1179 writel(0, &rxmac->mask4_word2);
1180 writel(0, &rxmac->mask4_word3);
1182 /* Lets setup the WOL Source Address */
1183 sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
1184 (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
1185 (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
1187 writel(sa_lo, &rxmac->sa_lo);
1189 sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
1191 writel(sa_hi, &rxmac->sa_hi);
1193 /* Disable all Packet Filtering */
1194 writel(0, &rxmac->pf_ctrl);
1196 /* Let's initialize the Unicast Packet filtering address */
1197 if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
1198 et1310_setup_device_for_unicast(adapter);
1199 pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
1201 writel(0, &rxmac->uni_pf_addr1);
1202 writel(0, &rxmac->uni_pf_addr2);
1203 writel(0, &rxmac->uni_pf_addr3);
1206 /* Let's initialize the Multicast hash */
1207 if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
1208 pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
1209 et1310_setup_device_for_multicast(adapter);
1212 /* Runt packet filtering. Didn't work in version A silicon. */
1213 pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
1214 pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
1216 if (adapter->registry_jumbo_packet > 8192)
1217 /* In order to transmit jumbo packets greater than 8k, the
1218 * FIFO between RxMAC and RxDMA needs to be reduced in size
1219 * to (16k - Jumbo packet size). In order to implement this,
1220 * we must use "cut through" mode in the RxMAC, which chops
1221 * packets down into segments which are (max_size * 16). In
1222 * this case we selected 256 bytes, since this is the size of
1223 * the PCI-Express TLP's that the 1310 uses.
1225 * seg_en on, fc_en off, size 0x10
1227 writel(0x41, &rxmac->mcif_ctrl_max_seg);
1229 writel(0, &rxmac->mcif_ctrl_max_seg);
1231 /* Initialize the MCIF water marks */
1232 writel(0, &rxmac->mcif_water_mark);
1234 /* Initialize the MIF control */
1235 writel(0, &rxmac->mif_ctrl);
1237 /* Initialize the Space Available Register */
1238 writel(0, &rxmac->space_avail);
1240 /* Initialize the the mif_ctrl register
1241 * bit 3: Receive code error. One or more nibbles were signaled as
1242 * errors during the reception of the packet. Clear this
1243 * bit in Gigabit, set it in 100Mbit. This was derived
1244 * experimentally at UNH.
1245 * bit 4: Receive CRC error. The packet's CRC did not match the
1246 * internally generated CRC.
1247 * bit 5: Receive length check error. Indicates that frame length
1248 * field value in the packet does not match the actual data
1249 * byte length and is not a type field.
1250 * bit 16: Receive frame truncated.
1251 * bit 17: Drop packet enable
1253 if (phydev && phydev->speed == SPEED_100)
1254 writel(0x30038, &rxmac->mif_ctrl);
1256 writel(0x30030, &rxmac->mif_ctrl);
1258 /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
1259 * filter is always enabled since it is where the runt packets are
1260 * supposed to be dropped. For version A silicon, runt packet
1261 * dropping doesn't work, so it is disabled in the pf_ctrl register,
1262 * but we still leave the packet filter on.
1264 writel(pf_ctrl, &rxmac->pf_ctrl);
1265 writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
1268 static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
1270 struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
1272 /* We need to update the Control Frame Parameters
1273 * cfpt - control frame pause timer set to 64 (0x40)
1274 * cfep - control frame extended pause timer set to 0x0
1276 if (adapter->flowcontrol == FLOW_NONE)
1277 writel(0, &txmac->cf_param);
1279 writel(0x40, &txmac->cf_param);
1282 static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
1284 struct macstat_regs __iomem *macstat =
1285 &adapter->regs->macstat;
1287 /* Next we need to initialize all the macstat registers to zero on
1290 writel(0, &macstat->txrx_0_64_byte_frames);
1291 writel(0, &macstat->txrx_65_127_byte_frames);
1292 writel(0, &macstat->txrx_128_255_byte_frames);
1293 writel(0, &macstat->txrx_256_511_byte_frames);
1294 writel(0, &macstat->txrx_512_1023_byte_frames);
1295 writel(0, &macstat->txrx_1024_1518_byte_frames);
1296 writel(0, &macstat->txrx_1519_1522_gvln_frames);
1298 writel(0, &macstat->rx_bytes);
1299 writel(0, &macstat->rx_packets);
1300 writel(0, &macstat->rx_fcs_errs);
1301 writel(0, &macstat->rx_multicast_packets);
1302 writel(0, &macstat->rx_broadcast_packets);
1303 writel(0, &macstat->rx_control_frames);
1304 writel(0, &macstat->rx_pause_frames);
1305 writel(0, &macstat->rx_unknown_opcodes);
1306 writel(0, &macstat->rx_align_errs);
1307 writel(0, &macstat->rx_frame_len_errs);
1308 writel(0, &macstat->rx_code_errs);
1309 writel(0, &macstat->rx_carrier_sense_errs);
1310 writel(0, &macstat->rx_undersize_packets);
1311 writel(0, &macstat->rx_oversize_packets);
1312 writel(0, &macstat->rx_fragment_packets);
1313 writel(0, &macstat->rx_jabbers);
1314 writel(0, &macstat->rx_drops);
1316 writel(0, &macstat->tx_bytes);
1317 writel(0, &macstat->tx_packets);
1318 writel(0, &macstat->tx_multicast_packets);
1319 writel(0, &macstat->tx_broadcast_packets);
1320 writel(0, &macstat->tx_pause_frames);
1321 writel(0, &macstat->tx_deferred);
1322 writel(0, &macstat->tx_excessive_deferred);
1323 writel(0, &macstat->tx_single_collisions);
1324 writel(0, &macstat->tx_multiple_collisions);
1325 writel(0, &macstat->tx_late_collisions);
1326 writel(0, &macstat->tx_excessive_collisions);
1327 writel(0, &macstat->tx_total_collisions);
1328 writel(0, &macstat->tx_pause_honored_frames);
1329 writel(0, &macstat->tx_drops);
1330 writel(0, &macstat->tx_jabbers);
1331 writel(0, &macstat->tx_fcs_errs);
1332 writel(0, &macstat->tx_control_frames);
1333 writel(0, &macstat->tx_oversize_frames);
1334 writel(0, &macstat->tx_undersize_frames);
1335 writel(0, &macstat->tx_fragments);
1336 writel(0, &macstat->carry_reg1);
1337 writel(0, &macstat->carry_reg2);
1339 /* Unmask any counters that we want to track the overflow of.
1340 * Initially this will be all counters. It may become clear later
1341 * that we do not need to track all counters.
1343 writel(0xFFFFBE32, &macstat->carry_reg1_mask);
1344 writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
1347 /* et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC
1348 * @adapter: pointer to our private adapter structure
1349 * @addr: the address of the transceiver
1350 * @reg: the register to read
1351 * @value: pointer to a 16-bit value in which the value will be stored
1353 static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
1356 struct mac_regs __iomem *mac = &adapter->regs->mac;
1363 /* Save a local copy of the registers we are dealing with so we can
1366 mii_addr = readl(&mac->mii_mgmt_addr);
1367 mii_cmd = readl(&mac->mii_mgmt_cmd);
1369 /* Stop the current operation */
1370 writel(0, &mac->mii_mgmt_cmd);
1372 /* Set up the register we need to read from on the correct PHY */
1373 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1375 writel(0x1, &mac->mii_mgmt_cmd);
1380 mii_indicator = readl(&mac->mii_mgmt_indicator);
1381 } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
1383 /* If we hit the max delay, we could not read the register */
1385 dev_warn(&adapter->pdev->dev,
1386 "reg 0x%08x could not be read\n", reg);
1387 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1393 /* If we hit here we were able to read the register and we need to
1394 * return the value to the caller
1396 *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
1398 /* Stop the read operation */
1399 writel(0, &mac->mii_mgmt_cmd);
1401 /* set the registers we touched back to the state at which we entered
1404 writel(mii_addr, &mac->mii_mgmt_addr);
1405 writel(mii_cmd, &mac->mii_mgmt_cmd);
1410 static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
1412 struct phy_device *phydev = adapter->phydev;
1417 return et131x_phy_mii_read(adapter, phydev->addr, reg, value);
1420 /* et131x_mii_write - Write to a PHY reg through the MII interface of the MAC
1421 * @adapter: pointer to our private adapter structure
1422 * @reg: the register to read
1423 * @value: 16-bit value to write
1425 static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value)
1427 struct mac_regs __iomem *mac = &adapter->regs->mac;
1428 struct phy_device *phydev = adapter->phydev;
1439 addr = phydev->addr;
1441 /* Save a local copy of the registers we are dealing with so we can
1444 mii_addr = readl(&mac->mii_mgmt_addr);
1445 mii_cmd = readl(&mac->mii_mgmt_cmd);
1447 /* Stop the current operation */
1448 writel(0, &mac->mii_mgmt_cmd);
1450 /* Set up the register we need to write to on the correct PHY */
1451 writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
1453 /* Add the value to write to the registers to the mac */
1454 writel(value, &mac->mii_mgmt_ctrl);
1459 mii_indicator = readl(&mac->mii_mgmt_indicator);
1460 } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
1462 /* If we hit the max delay, we could not write the register */
1466 dev_warn(&adapter->pdev->dev,
1467 "reg 0x%08x could not be written", reg);
1468 dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
1470 dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
1471 readl(&mac->mii_mgmt_cmd));
1473 et131x_mii_read(adapter, reg, &tmp);
1477 /* Stop the write operation */
1478 writel(0, &mac->mii_mgmt_cmd);
1480 /* set the registers we touched back to the state at which we entered
1483 writel(mii_addr, &mac->mii_mgmt_addr);
1484 writel(mii_cmd, &mac->mii_mgmt_cmd);
1489 static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
1495 u16 mask = 1 << bitnum;
1497 /* Read the requested register */
1498 et131x_mii_read(adapter, regnum, ®);
1500 *value = (reg & mask) >> bitnum;
1503 static void et1310_config_flow_control(struct et131x_adapter *adapter)
1505 struct phy_device *phydev = adapter->phydev;
1507 if (phydev->duplex == DUPLEX_HALF) {
1508 adapter->flowcontrol = FLOW_NONE;
1510 char remote_pause, remote_async_pause;
1512 et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
1513 et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
1515 if (remote_pause && remote_async_pause) {
1516 adapter->flowcontrol = adapter->wanted_flow;
1517 } else if (remote_pause && !remote_async_pause) {
1518 if (adapter->wanted_flow == FLOW_BOTH)
1519 adapter->flowcontrol = FLOW_BOTH;
1521 adapter->flowcontrol = FLOW_NONE;
1522 } else if (!remote_pause && !remote_async_pause) {
1523 adapter->flowcontrol = FLOW_NONE;
1525 if (adapter->wanted_flow == FLOW_BOTH)
1526 adapter->flowcontrol = FLOW_RXONLY;
1528 adapter->flowcontrol = FLOW_NONE;
1533 /* et1310_update_macstat_host_counters - Update local copy of the statistics */
1534 static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
1536 struct ce_stats *stats = &adapter->stats;
1537 struct macstat_regs __iomem *macstat =
1538 &adapter->regs->macstat;
1540 stats->tx_collisions += readl(&macstat->tx_total_collisions);
1541 stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
1542 stats->tx_deferred += readl(&macstat->tx_deferred);
1543 stats->tx_excessive_collisions +=
1544 readl(&macstat->tx_multiple_collisions);
1545 stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
1546 stats->tx_underflows += readl(&macstat->tx_undersize_frames);
1547 stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
1549 stats->rx_align_errs += readl(&macstat->rx_align_errs);
1550 stats->rx_crc_errs += readl(&macstat->rx_code_errs);
1551 stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
1552 stats->rx_overflows += readl(&macstat->rx_oversize_packets);
1553 stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
1554 stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
1555 stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
1558 /* et1310_handle_macstat_interrupt
1560 * One of the MACSTAT counters has wrapped. Update the local copy of
1561 * the statistics held in the adapter structure, checking the "wrap"
1562 * bit for each counter.
1564 static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
1569 /* Read the interrupt bits from the register(s). These are Clear On
1572 carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
1573 carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
1575 writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
1576 writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
1578 /* We need to do update the host copy of all the MAC_STAT counters.
1579 * For each counter, check it's overflow bit. If the overflow bit is
1580 * set, then increment the host version of the count by one complete
1581 * revolution of the counter. This routine is called when the counter
1582 * block indicates that one of the counters has wrapped.
1584 if (carry_reg1 & (1 << 14))
1585 adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
1586 if (carry_reg1 & (1 << 8))
1587 adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
1588 if (carry_reg1 & (1 << 7))
1589 adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
1590 if (carry_reg1 & (1 << 2))
1591 adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
1592 if (carry_reg1 & (1 << 6))
1593 adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
1594 if (carry_reg1 & (1 << 3))
1595 adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
1596 if (carry_reg1 & (1 << 0))
1597 adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
1598 if (carry_reg2 & (1 << 16))
1599 adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
1600 if (carry_reg2 & (1 << 15))
1601 adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
1602 if (carry_reg2 & (1 << 6))
1603 adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
1604 if (carry_reg2 & (1 << 8))
1605 adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
1606 if (carry_reg2 & (1 << 5))
1607 adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
1608 if (carry_reg2 & (1 << 4))
1609 adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
1610 if (carry_reg2 & (1 << 2))
1611 adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
1614 static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
1616 struct net_device *netdev = bus->priv;
1617 struct et131x_adapter *adapter = netdev_priv(netdev);
1621 ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
1629 static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
1632 struct net_device *netdev = bus->priv;
1633 struct et131x_adapter *adapter = netdev_priv(netdev);
1635 return et131x_mii_write(adapter, reg, value);
1638 static int et131x_mdio_reset(struct mii_bus *bus)
1640 struct net_device *netdev = bus->priv;
1641 struct et131x_adapter *adapter = netdev_priv(netdev);
1643 et131x_mii_write(adapter, MII_BMCR, BMCR_RESET);
1648 /* et1310_phy_power_switch - PHY power control
1649 * @adapter: device to control
1650 * @down: true for off/false for back on
1652 * one hundred, ten, one thousand megs
1653 * How would you like to have your LAN accessed
1654 * Can't you see that this code processed
1655 * Phy power, phy power..
1657 static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
1661 et131x_mii_read(adapter, MII_BMCR, &data);
1662 data &= ~BMCR_PDOWN;
1665 et131x_mii_write(adapter, MII_BMCR, data);
1668 /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
1669 static void et131x_xcvr_init(struct et131x_adapter *adapter)
1673 /* Set the LED behavior such that LED 1 indicates speed (off =
1674 * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
1675 * link and activity (on for link, blink off for activity).
1677 * NOTE: Some customizations have been added here for specific
1678 * vendors; The LED behavior is now determined by vendor data in the
1679 * EEPROM. However, the above description is the default.
1681 if ((adapter->eeprom_data[1] & 0x4) == 0) {
1682 et131x_mii_read(adapter, PHY_LED_2, &lcr2);
1684 lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
1685 lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
1687 if ((adapter->eeprom_data[1] & 0x8) == 0)
1688 lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
1690 lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
1692 et131x_mii_write(adapter, PHY_LED_2, lcr2);
1696 /* et131x_configure_global_regs - configure JAGCore global regs
1698 * Used to configure the global registers on the JAGCore
1700 static void et131x_configure_global_regs(struct et131x_adapter *adapter)
1702 struct global_regs __iomem *regs = &adapter->regs->global;
1704 writel(0, ®s->rxq_start_addr);
1705 writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
1707 if (adapter->registry_jumbo_packet < 2048) {
1708 /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
1709 * block of RAM that the driver can split between Tx
1710 * and Rx as it desires. Our default is to split it
1713 writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
1714 writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
1715 } else if (adapter->registry_jumbo_packet < 8192) {
1716 /* For jumbo packets > 2k but < 8k, split 50-50. */
1717 writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
1718 writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
1720 /* 9216 is the only packet size greater than 8k that
1721 * is available. The Tx buffer has to be big enough
1722 * for one whole packet on the Tx side. We'll make
1723 * the Tx 9408, and give the rest to Rx
1725 writel(0x01b3, ®s->rxq_end_addr);
1726 writel(0x01b4, ®s->txq_start_addr);
1729 /* Initialize the loopback register. Disable all loopbacks. */
1730 writel(0, ®s->loopback);
1733 writel(0, ®s->msi_config);
1735 /* By default, disable the watchdog timer. It will be enabled when
1736 * a packet is queued.
1738 writel(0, ®s->watchdog_timer);
1741 /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
1742 static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
1744 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
1745 struct rx_ring *rx_local = &adapter->rx_ring;
1746 struct fbr_desc *fbr_entry;
1749 unsigned long flags;
1752 /* Halt RXDMA to perform the reconfigure. */
1753 et131x_rx_dma_disable(adapter);
1755 /* Load the completion writeback physical address */
1756 writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
1757 writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
1759 memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
1761 /* Set the address and parameters of the packet status ring into the
1764 writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
1765 writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
1766 writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des);
1767 writel(0, &rx_dma->psr_full_offset);
1769 psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
1770 writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
1771 &rx_dma->psr_min_des);
1773 spin_lock_irqsave(&adapter->rcv_lock, flags);
1775 /* These local variables track the PSR in the adapter structure */
1776 rx_local->local_psr_full = 0;
1778 for (id = 0; id < NUM_FBRS; id++) {
1779 u32 __iomem *num_des;
1780 u32 __iomem *full_offset;
1781 u32 __iomem *min_des;
1782 u32 __iomem *base_hi;
1783 u32 __iomem *base_lo;
1784 struct fbr_lookup *fbr = rx_local->fbr[id];
1787 num_des = &rx_dma->fbr0_num_des;
1788 full_offset = &rx_dma->fbr0_full_offset;
1789 min_des = &rx_dma->fbr0_min_des;
1790 base_hi = &rx_dma->fbr0_base_hi;
1791 base_lo = &rx_dma->fbr0_base_lo;
1793 num_des = &rx_dma->fbr1_num_des;
1794 full_offset = &rx_dma->fbr1_full_offset;
1795 min_des = &rx_dma->fbr1_min_des;
1796 base_hi = &rx_dma->fbr1_base_hi;
1797 base_lo = &rx_dma->fbr1_base_lo;
1800 /* Now's the best time to initialize FBR contents */
1801 fbr_entry = (struct fbr_desc *) fbr->ring_virtaddr;
1802 for (entry = 0; entry < fbr->num_entries; entry++) {
1803 fbr_entry->addr_hi = fbr->bus_high[entry];
1804 fbr_entry->addr_lo = fbr->bus_low[entry];
1805 fbr_entry->word2 = entry;
1809 /* Set the address and parameters of Free buffer ring 1 and 0
1810 * into the 1310's registers
1812 writel(upper_32_bits(fbr->ring_physaddr), base_hi);
1813 writel(lower_32_bits(fbr->ring_physaddr), base_lo);
1814 writel(fbr->num_entries - 1, num_des);
1815 writel(ET_DMA10_WRAP, full_offset);
1817 /* This variable tracks the free buffer ring 1 full position,
1818 * so it has to match the above.
1820 fbr->local_full = ET_DMA10_WRAP;
1821 writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
1825 /* Program the number of packets we will receive before generating an
1827 * For version B silicon, this value gets updated once autoneg is
1830 writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
1832 /* The "time_done" is not working correctly to coalesce interrupts
1833 * after a given time period, but rather is giving us an interrupt
1834 * regardless of whether we have received packets.
1835 * This value gets updated once autoneg is complete.
1837 writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
1839 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
1842 /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
1844 * Configure the transmit engine with the ring buffers we have created
1845 * and prepare it for use.
1847 static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
1849 struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
1851 /* Load the hardware with the start of the transmit descriptor ring. */
1852 writel(upper_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1853 &txdma->pr_base_hi);
1854 writel(lower_32_bits(adapter->tx_ring.tx_desc_ring_pa),
1855 &txdma->pr_base_lo);
1857 /* Initialise the transmit DMA engine */
1858 writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
1860 /* Load the completion writeback physical address */
1861 writel(upper_32_bits(adapter->tx_ring.tx_status_pa),
1862 &txdma->dma_wb_base_hi);
1863 writel(lower_32_bits(adapter->tx_ring.tx_status_pa),
1864 &txdma->dma_wb_base_lo);
1866 *adapter->tx_ring.tx_status = 0;
1868 writel(0, &txdma->service_request);
1869 adapter->tx_ring.send_idx = 0;
1872 /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
1873 static void et131x_adapter_setup(struct et131x_adapter *adapter)
1875 /* Configure the JAGCore */
1876 et131x_configure_global_regs(adapter);
1878 et1310_config_mac_regs1(adapter);
1880 /* Configure the MMC registers */
1881 /* All we need to do is initialize the Memory Control Register */
1882 writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
1884 et1310_config_rxmac_regs(adapter);
1885 et1310_config_txmac_regs(adapter);
1887 et131x_config_rx_dma_regs(adapter);
1888 et131x_config_tx_dma_regs(adapter);
1890 et1310_config_macstat_regs(adapter);
1892 et1310_phy_power_switch(adapter, 0);
1893 et131x_xcvr_init(adapter);
1896 /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
1897 static void et131x_soft_reset(struct et131x_adapter *adapter)
1901 /* Disable MAC Core */
1902 reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
1903 ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1904 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1905 writel(reg, &adapter->regs->mac.cfg1);
1908 writel(reg, &adapter->regs->global.sw_reset);
1910 reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
1911 ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
1912 writel(reg, &adapter->regs->mac.cfg1);
1913 writel(0, &adapter->regs->mac.cfg1);
1916 /* et131x_enable_interrupts - enable interrupt
1918 * Enable the appropriate interrupts on the ET131x according to our
1921 static void et131x_enable_interrupts(struct et131x_adapter *adapter)
1925 /* Enable all global interrupts */
1926 if (adapter->flowcontrol == FLOW_TXONLY ||
1927 adapter->flowcontrol == FLOW_BOTH)
1928 mask = INT_MASK_ENABLE;
1930 mask = INT_MASK_ENABLE_NO_FLOW;
1932 writel(mask, &adapter->regs->global.int_mask);
1935 /* et131x_disable_interrupts - interrupt disable
1937 * Block all interrupts from the et131x device at the device itself
1939 static void et131x_disable_interrupts(struct et131x_adapter *adapter)
1941 /* Disable all global interrupts */
1942 writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
1945 /* et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 */
1946 static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
1948 /* Setup the tramsmit dma configuration register */
1949 writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
1950 &adapter->regs->txdma.csr);
1953 /* et131x_enable_txrx - Enable tx/rx queues */
1954 static void et131x_enable_txrx(struct net_device *netdev)
1956 struct et131x_adapter *adapter = netdev_priv(netdev);
1958 /* Enable the Tx and Rx DMA engines (if not already enabled) */
1959 et131x_rx_dma_enable(adapter);
1960 et131x_tx_dma_enable(adapter);
1962 /* Enable device interrupts */
1963 if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
1964 et131x_enable_interrupts(adapter);
1966 /* We're ready to move some data, so start the queue */
1967 netif_start_queue(netdev);
1970 /* et131x_disable_txrx - Disable tx/rx queues */
1971 static void et131x_disable_txrx(struct net_device *netdev)
1973 struct et131x_adapter *adapter = netdev_priv(netdev);
1975 /* First thing is to stop the queue */
1976 netif_stop_queue(netdev);
1978 /* Stop the Tx and Rx DMA engines */
1979 et131x_rx_dma_disable(adapter);
1980 et131x_tx_dma_disable(adapter);
1982 /* Disable device interrupts */
1983 et131x_disable_interrupts(adapter);
1986 /* et131x_init_send - Initialize send data structures */
1987 static void et131x_init_send(struct et131x_adapter *adapter)
1991 struct tx_ring *tx_ring;
1993 /* Setup some convenience pointers */
1994 tx_ring = &adapter->tx_ring;
1995 tcb = adapter->tx_ring.tcb_ring;
1997 tx_ring->tcb_qhead = tcb;
1999 memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
2001 /* Go through and set up each TCB */
2002 for (ct = 0; ct++ < NUM_TCB; tcb++)
2003 /* Set the link pointer in HW TCB to the next TCB in the
2006 tcb->next = tcb + 1;
2008 /* Set the tail pointer */
2010 tx_ring->tcb_qtail = tcb;
2012 /* Curr send queue should now be empty */
2013 tx_ring->send_head = NULL;
2014 tx_ring->send_tail = NULL;
2017 /* et1310_enable_phy_coma - called when network cable is unplugged
2019 * driver receive an phy status change interrupt while in D0 and check that
2020 * phy_status is down.
2022 * -- gate off JAGCore;
2023 * -- set gigE PHY in Coma mode
2024 * -- wake on phy_interrupt; Perform software reset JAGCore,
2025 * re-initialize jagcore and gigE PHY
2027 * Add D0-ASPM-PhyLinkDown Support:
2028 * -- while in D0, when there is a phy_interrupt indicating phy link
2029 * down status, call the MPSetPhyComa routine to enter this active
2030 * state power saving mode
2031 * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
2032 * indicating linkup status, call the MPDisablePhyComa routine to
2033 * restore JAGCore and gigE PHY
2035 static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
2037 unsigned long flags;
2040 pmcsr = readl(&adapter->regs->global.pm_csr);
2042 /* Save the GbE PHY speed and duplex modes. Need to restore this
2043 * when cable is plugged back in
2046 /* Stop sending packets. */
2047 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2048 adapter->flags |= FMP_ADAPTER_LOWER_POWER;
2049 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2051 /* Wait for outstanding Receive packets */
2053 et131x_disable_txrx(adapter->netdev);
2055 /* Gate off JAGCore 3 clock domains */
2056 pmcsr &= ~ET_PMCSR_INIT;
2057 writel(pmcsr, &adapter->regs->global.pm_csr);
2059 /* Program gigE PHY in to Coma mode */
2060 pmcsr |= ET_PM_PHY_SW_COMA;
2061 writel(pmcsr, &adapter->regs->global.pm_csr);
2064 /* et1310_disable_phy_coma - Disable the Phy Coma Mode */
2065 static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
2069 pmcsr = readl(&adapter->regs->global.pm_csr);
2071 /* Disable phy_sw_coma register and re-enable JAGCore clocks */
2072 pmcsr |= ET_PMCSR_INIT;
2073 pmcsr &= ~ET_PM_PHY_SW_COMA;
2074 writel(pmcsr, &adapter->regs->global.pm_csr);
2076 /* Restore the GbE PHY speed and duplex modes;
2077 * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
2080 /* Re-initialize the send structures */
2081 et131x_init_send(adapter);
2083 /* Bring the device back to the state it was during init prior to
2084 * autonegotiation being complete. This way, when we get the auto-neg
2085 * complete interrupt, we can complete init by calling ConfigMacREGS2.
2087 et131x_soft_reset(adapter);
2089 /* setup et1310 as per the documentation ?? */
2090 et131x_adapter_setup(adapter);
2092 /* Allow Tx to restart */
2093 adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
2095 et131x_enable_txrx(adapter->netdev);
2098 static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
2100 u32 tmp_free_buff_ring = *free_buff_ring;
2101 tmp_free_buff_ring++;
2102 /* This works for all cases where limit < 1024. The 1023 case
2103 * works because 1023++ is 1024 which means the if condition is not
2104 * taken but the carry of the bit into the wrap bit toggles the wrap
2107 if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
2108 tmp_free_buff_ring &= ~ET_DMA10_MASK;
2109 tmp_free_buff_ring ^= ET_DMA10_WRAP;
2111 /* For the 1023 case */
2112 tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
2113 *free_buff_ring = tmp_free_buff_ring;
2114 return tmp_free_buff_ring;
2117 /* et131x_rx_dma_memory_alloc
2119 * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
2120 * and the Packet Status Ring.
2122 static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
2127 u32 pktstat_ringsize;
2129 struct rx_ring *rx_ring;
2130 struct fbr_lookup *fbr;
2132 /* Setup some convenience pointers */
2133 rx_ring = &adapter->rx_ring;
2135 /* Alloc memory for the lookup table */
2136 rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2137 rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL);
2139 /* The first thing we will do is configure the sizes of the buffer
2140 * rings. These will change based on jumbo packet support. Larger
2141 * jumbo packets increases the size of each entry in FBR0, and the
2142 * number of entries in FBR0, while at the same time decreasing the
2143 * number of entries in FBR1.
2145 * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
2146 * entries are huge in order to accommodate a "jumbo" frame, then it
2147 * will have less entries. Conversely, FBR1 will now be relied upon
2148 * to carry more "normal" frames, thus it's entry size also increases
2149 * and the number of entries goes up too (since it now carries
2150 * "small" + "regular" packets.
2152 * In this scheme, we try to maintain 512 entries between the two
2153 * rings. Also, FBR1 remains a constant size - when it's size doubles
2154 * the number of entries halves. FBR0 increases in size, however.
2157 if (adapter->registry_jumbo_packet < 2048) {
2158 rx_ring->fbr[0]->buffsize = 256;
2159 rx_ring->fbr[0]->num_entries = 512;
2160 rx_ring->fbr[1]->buffsize = 2048;
2161 rx_ring->fbr[1]->num_entries = 512;
2162 } else if (adapter->registry_jumbo_packet < 4096) {
2163 rx_ring->fbr[0]->buffsize = 512;
2164 rx_ring->fbr[0]->num_entries = 1024;
2165 rx_ring->fbr[1]->buffsize = 4096;
2166 rx_ring->fbr[1]->num_entries = 512;
2168 rx_ring->fbr[0]->buffsize = 1024;
2169 rx_ring->fbr[0]->num_entries = 768;
2170 rx_ring->fbr[1]->buffsize = 16384;
2171 rx_ring->fbr[1]->num_entries = 128;
2174 rx_ring->psr_num_entries = rx_ring->fbr[0]->num_entries +
2175 rx_ring->fbr[1]->num_entries;
2177 for (id = 0; id < NUM_FBRS; id++) {
2178 fbr = rx_ring->fbr[id];
2179 /* Allocate an area of memory for Free Buffer Ring */
2180 bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
2181 fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2183 &fbr->ring_physaddr,
2185 if (!fbr->ring_virtaddr) {
2186 dev_err(&adapter->pdev->dev,
2187 "Cannot alloc memory for Free Buffer Ring %d\n", id);
2192 for (id = 0; id < NUM_FBRS; id++) {
2193 fbr = rx_ring->fbr[id];
2194 fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
2196 for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
2197 dma_addr_t fbr_tmp_physaddr;
2199 fbr->mem_virtaddrs[i] = dma_alloc_coherent(
2200 &adapter->pdev->dev, fbr_chunksize,
2201 &fbr->mem_physaddrs[i],
2204 if (!fbr->mem_virtaddrs[i]) {
2205 dev_err(&adapter->pdev->dev,
2206 "Could not alloc memory\n");
2210 /* See NOTE in "Save Physical Address" comment above */
2211 fbr_tmp_physaddr = fbr->mem_physaddrs[i];
2213 for (j = 0; j < FBR_CHUNKS; j++) {
2214 u32 index = (i * FBR_CHUNKS) + j;
2216 /* Save the Virtual address of this index for
2217 * quick access later
2219 fbr->virt[index] = (u8 *)fbr->mem_virtaddrs[i] +
2220 (j * fbr->buffsize);
2222 /* now store the physical address in the
2223 * descriptor so the device can access it
2225 fbr->bus_high[index] =
2226 upper_32_bits(fbr_tmp_physaddr);
2227 fbr->bus_low[index] =
2228 lower_32_bits(fbr_tmp_physaddr);
2230 fbr_tmp_physaddr += fbr->buffsize;
2235 /* Allocate an area of memory for FIFO of Packet Status ring entries */
2237 sizeof(struct pkt_stat_desc) * rx_ring->psr_num_entries;
2239 rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
2241 &rx_ring->ps_ring_physaddr,
2244 if (!rx_ring->ps_ring_virtaddr) {
2245 dev_err(&adapter->pdev->dev,
2246 "Cannot alloc memory for Packet Status Ring\n");
2250 /* NOTE : dma_alloc_coherent(), used above to alloc DMA regions,
2251 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2252 * are ever returned, make sure the high part is retrieved here before
2253 * storing the adjusted address.
2256 /* Allocate an area of memory for writeback of status information */
2257 rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
2258 sizeof(struct rx_status_block),
2259 &rx_ring->rx_status_bus,
2261 if (!rx_ring->rx_status_block) {
2262 dev_err(&adapter->pdev->dev,
2263 "Cannot alloc memory for Status Block\n");
2266 rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
2268 /* The RFDs are going to be put on lists later on, so initialize the
2271 INIT_LIST_HEAD(&rx_ring->recv_list);
2275 /* et131x_rx_dma_memory_free - Free all memory allocated within this module */
2276 static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
2281 u32 pktstat_ringsize;
2283 struct rx_ring *rx_ring;
2285 /* Setup some convenience pointers */
2286 rx_ring = &adapter->rx_ring;
2288 /* Free RFDs and associated packet descriptors */
2289 WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
2291 while (!list_empty(&rx_ring->recv_list)) {
2292 rfd = (struct rfd *) list_entry(rx_ring->recv_list.next,
2293 struct rfd, list_node);
2295 list_del(&rfd->list_node);
2300 /* Free Free Buffer Rings */
2301 for (id = 0; id < NUM_FBRS; id++) {
2302 if (!rx_ring->fbr[id]->ring_virtaddr)
2305 /* First the packet memory */
2307 index < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS);
2309 if (rx_ring->fbr[id]->mem_virtaddrs[index]) {
2311 rx_ring->fbr[id]->buffsize * FBR_CHUNKS;
2313 dma_free_coherent(&adapter->pdev->dev,
2315 rx_ring->fbr[id]->mem_virtaddrs[index],
2316 rx_ring->fbr[id]->mem_physaddrs[index]);
2318 rx_ring->fbr[id]->mem_virtaddrs[index] = NULL;
2323 sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries;
2325 dma_free_coherent(&adapter->pdev->dev, bufsize,
2326 rx_ring->fbr[id]->ring_virtaddr,
2327 rx_ring->fbr[id]->ring_physaddr);
2329 rx_ring->fbr[id]->ring_virtaddr = NULL;
2332 /* Free Packet Status Ring */
2333 if (rx_ring->ps_ring_virtaddr) {
2334 pktstat_ringsize = sizeof(struct pkt_stat_desc) *
2335 adapter->rx_ring.psr_num_entries;
2337 dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize,
2338 rx_ring->ps_ring_virtaddr,
2339 rx_ring->ps_ring_physaddr);
2341 rx_ring->ps_ring_virtaddr = NULL;
2344 /* Free area of memory for the writeback of status information */
2345 if (rx_ring->rx_status_block) {
2346 dma_free_coherent(&adapter->pdev->dev,
2347 sizeof(struct rx_status_block),
2348 rx_ring->rx_status_block, rx_ring->rx_status_bus);
2349 rx_ring->rx_status_block = NULL;
2352 /* Free the FBR Lookup Table */
2353 kfree(rx_ring->fbr[0]);
2354 kfree(rx_ring->fbr[1]);
2356 /* Reset Counters */
2357 rx_ring->num_ready_recv = 0;
2360 /* et131x_init_recv - Initialize receive data structures */
2361 static int et131x_init_recv(struct et131x_adapter *adapter)
2365 struct rx_ring *rx_ring;
2367 /* Setup some convenience pointers */
2368 rx_ring = &adapter->rx_ring;
2370 /* Setup each RFD */
2371 for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
2372 rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA);
2378 /* Add this RFD to the recv_list */
2379 list_add_tail(&rfd->list_node, &rx_ring->recv_list);
2381 /* Increment the available RFD's */
2382 rx_ring->num_ready_recv++;
2388 /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
2389 static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
2391 struct phy_device *phydev = adapter->phydev;
2393 /* For version B silicon, we do not use the RxDMA timer for 10 and 100
2394 * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
2396 if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
2397 writel(0, &adapter->regs->rxdma.max_pkt_time);
2398 writel(1, &adapter->regs->rxdma.num_pkt_done);
2402 /* NICReturnRFD - Recycle a RFD and put it back onto the receive list
2403 * @adapter: pointer to our adapter
2404 * @rfd: pointer to the RFD
2406 static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
2408 struct rx_ring *rx_local = &adapter->rx_ring;
2409 struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
2410 u16 buff_index = rfd->bufferindex;
2411 u8 ring_index = rfd->ringindex;
2412 unsigned long flags;
2414 /* We don't use any of the OOB data besides status. Otherwise, we
2415 * need to clean up OOB data
2417 if (buff_index < rx_local->fbr[ring_index]->num_entries) {
2418 u32 __iomem *offset;
2419 struct fbr_desc *next;
2421 spin_lock_irqsave(&adapter->fbr_lock, flags);
2423 if (ring_index == 0)
2424 offset = &rx_dma->fbr0_full_offset;
2426 offset = &rx_dma->fbr1_full_offset;
2428 next = (struct fbr_desc *)
2429 (rx_local->fbr[ring_index]->ring_virtaddr) +
2430 INDEX10(rx_local->fbr[ring_index]->local_full);
2432 /* Handle the Free Buffer Ring advancement here. Write
2433 * the PA / Buffer Index for the returned buffer into
2434 * the oldest (next to be freed)FBR entry
2436 next->addr_hi = rx_local->fbr[ring_index]->bus_high[buff_index];
2437 next->addr_lo = rx_local->fbr[ring_index]->bus_low[buff_index];
2438 next->word2 = buff_index;
2440 writel(bump_free_buff_ring(
2441 &rx_local->fbr[ring_index]->local_full,
2442 rx_local->fbr[ring_index]->num_entries - 1),
2445 spin_unlock_irqrestore(&adapter->fbr_lock, flags);
2447 dev_err(&adapter->pdev->dev,
2448 "%s illegal Buffer Index returned\n", __func__);
2451 /* The processing on this RFD is done, so put it back on the tail of
2454 spin_lock_irqsave(&adapter->rcv_lock, flags);
2455 list_add_tail(&rfd->list_node, &rx_local->recv_list);
2456 rx_local->num_ready_recv++;
2457 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2459 WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
2462 /* nic_rx_pkts - Checks the hardware for available packets
2464 * Returns rfd, a pointer to our MPRFD.
2466 * Checks the hardware for available packets, using completion ring
2467 * If packets are available, it gets an RFD from the recv_list, attaches
2468 * the packet to it, puts the RFD in the RecvPendList, and also returns
2469 * the pointer to the RFD.
2471 static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
2473 struct rx_ring *rx_local = &adapter->rx_ring;
2474 struct rx_status_block *status;
2475 struct pkt_stat_desc *psr;
2479 unsigned long flags;
2480 struct list_head *element;
2486 struct sk_buff *skb;
2488 /* RX Status block is written by the DMA engine prior to every
2489 * interrupt. It contains the next to be used entry in the Packet
2490 * Status Ring, and also the two Free Buffer rings.
2492 status = rx_local->rx_status_block;
2493 word1 = status->word1 >> 16; /* Get the useful bits */
2495 /* Check the PSR and wrap bits do not match */
2496 if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
2497 return NULL; /* Looks like this ring is not updated yet */
2499 /* The packet status ring indicates that data is available. */
2500 psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) +
2501 (rx_local->local_psr_full & 0xFFF);
2503 /* Grab any information that is required once the PSR is advanced,
2504 * since we can no longer rely on the memory being accurate
2506 len = psr->word1 & 0xFFFF;
2507 ring_index = (psr->word1 >> 26) & 0x03;
2508 buff_index = (psr->word1 >> 16) & 0x3FF;
2511 /* Indicate that we have used this PSR entry. */
2513 add_12bit(&rx_local->local_psr_full, 1);
2515 (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) {
2516 /* Clear psr full and toggle the wrap bit */
2517 rx_local->local_psr_full &= ~0xFFF;
2518 rx_local->local_psr_full ^= 0x1000;
2521 writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
2523 if (ring_index > 1 ||
2524 buff_index > rx_local->fbr[ring_index]->num_entries - 1) {
2525 /* Illegal buffer or ring index cannot be used by S/W*/
2526 dev_err(&adapter->pdev->dev,
2527 "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
2528 rx_local->local_psr_full & 0xFFF, len, buff_index);
2532 /* Get and fill the RFD. */
2533 spin_lock_irqsave(&adapter->rcv_lock, flags);
2535 element = rx_local->recv_list.next;
2536 rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
2539 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2543 list_del(&rfd->list_node);
2544 rx_local->num_ready_recv--;
2546 spin_unlock_irqrestore(&adapter->rcv_lock, flags);
2548 rfd->bufferindex = buff_index;
2549 rfd->ringindex = ring_index;
2551 /* In V1 silicon, there is a bug which screws up filtering of runt
2552 * packets. Therefore runt packet filtering is disabled in the MAC and
2553 * the packets are dropped here. They are also counted here.
2555 if (len < (NIC_MIN_PACKET_SIZE + 4)) {
2556 adapter->stats.rx_other_errs++;
2565 /* Determine if this is a multicast packet coming in */
2566 if ((word0 & ALCATEL_MULTICAST_PKT) &&
2567 !(word0 & ALCATEL_BROADCAST_PKT)) {
2568 /* Promiscuous mode and Multicast mode are not mutually
2569 * exclusive as was first thought. I guess Promiscuous is just
2570 * considered a super-set of the other filters. Generally filter
2571 * is 0x2b when in promiscuous mode.
2573 if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST)
2574 && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS)
2575 && !(adapter->packet_filter &
2576 ET131X_PACKET_TYPE_ALL_MULTICAST)) {
2577 buf = rx_local->fbr[ring_index]->virt[buff_index];
2579 /* Loop through our list to see if the destination
2580 * address of this packet matches one in our list.
2582 for (i = 0; i < adapter->multicast_addr_count; i++) {
2583 if (buf[0] == adapter->multicast_list[i][0]
2584 && buf[1] == adapter->multicast_list[i][1]
2585 && buf[2] == adapter->multicast_list[i][2]
2586 && buf[3] == adapter->multicast_list[i][3]
2587 && buf[4] == adapter->multicast_list[i][4]
2588 && buf[5] == adapter->multicast_list[i][5]) {
2593 /* If our index is equal to the number of Multicast
2594 * address we have, then this means we did not find this
2595 * packet's matching address in our list. Set the len to
2596 * zero, so we free our RFD when we return from this
2599 if (i == adapter->multicast_addr_count)
2604 adapter->stats.multicast_pkts_rcvd++;
2605 } else if (word0 & ALCATEL_BROADCAST_PKT) {
2606 adapter->stats.broadcast_pkts_rcvd++;
2608 /* Not sure what this counter measures in promiscuous mode.
2609 * Perhaps we should check the MAC address to see if it is
2610 * directed to us in promiscuous mode.
2612 adapter->stats.unicast_pkts_rcvd++;
2622 skb = dev_alloc_skb(rfd->len + 2);
2624 dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n");
2628 adapter->net_stats.rx_bytes += rfd->len;
2630 memcpy(skb_put(skb, rfd->len),
2631 rx_local->fbr[ring_index]->virt[buff_index],
2634 skb->protocol = eth_type_trans(skb, adapter->netdev);
2635 skb->ip_summed = CHECKSUM_NONE;
2639 nic_return_rfd(adapter, rfd);
2643 /* et131x_handle_recv_interrupt - Interrupt handler for receive processing
2645 * Assumption, Rcv spinlock has been acquired.
2647 static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter)
2649 struct rfd *rfd = NULL;
2653 /* Process up to available RFD's */
2654 while (count < NUM_PACKETS_HANDLED) {
2655 if (list_empty(&adapter->rx_ring.recv_list)) {
2656 WARN_ON(adapter->rx_ring.num_ready_recv != 0);
2661 rfd = nic_rx_pkts(adapter);
2666 /* Do not receive any packets until a filter has been set.
2667 * Do not receive any packets until we have link.
2668 * If length is zero, return the RFD in order to advance the
2671 if (!adapter->packet_filter ||
2672 !netif_carrier_ok(adapter->netdev) ||
2676 /* Increment the number of packets we received */
2677 adapter->net_stats.rx_packets++;
2679 /* Set the status on the packet, either resources or success */
2680 if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK)
2681 dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
2686 if (count == NUM_PACKETS_HANDLED || !done) {
2687 adapter->rx_ring.unfinished_receives = true;
2688 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2689 &adapter->regs->global.watchdog_timer);
2691 /* Watchdog timer will disable itself if appropriate. */
2692 adapter->rx_ring.unfinished_receives = false;
2695 /* et131x_tx_dma_memory_alloc
2697 * Allocates memory that will be visible both to the device and to the CPU.
2698 * The OS will pass us packets, pointers to which we will insert in the Tx
2699 * Descriptor queue. The device will read this queue to find the packets in
2700 * memory. The device will update the "status" in memory each time it xmits a
2703 static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
2706 struct tx_ring *tx_ring = &adapter->tx_ring;
2708 /* Allocate memory for the TCB's (Transmit Control Block) */
2709 adapter->tx_ring.tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
2710 GFP_ATOMIC | GFP_DMA);
2711 if (!adapter->tx_ring.tcb_ring)
2714 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2715 tx_ring->tx_desc_ring =
2716 (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev,
2718 &tx_ring->tx_desc_ring_pa,
2720 if (!adapter->tx_ring.tx_desc_ring) {
2721 dev_err(&adapter->pdev->dev,
2722 "Cannot alloc memory for Tx Ring\n");
2726 /* Save physical address
2728 * NOTE: dma_alloc_coherent(), used above to alloc DMA regions,
2729 * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
2730 * are ever returned, make sure the high part is retrieved here before
2731 * storing the adjusted address.
2733 /* Allocate memory for the Tx status block */
2734 tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
2736 &tx_ring->tx_status_pa,
2738 if (!adapter->tx_ring.tx_status_pa) {
2739 dev_err(&adapter->pdev->dev,
2740 "Cannot alloc memory for Tx status block\n");
2746 /* et131x_tx_dma_memory_free - Free all memory allocated within this module */
2747 static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
2751 if (adapter->tx_ring.tx_desc_ring) {
2752 /* Free memory relating to Tx rings here */
2753 desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
2754 dma_free_coherent(&adapter->pdev->dev,
2756 adapter->tx_ring.tx_desc_ring,
2757 adapter->tx_ring.tx_desc_ring_pa);
2758 adapter->tx_ring.tx_desc_ring = NULL;
2761 /* Free memory for the Tx status block */
2762 if (adapter->tx_ring.tx_status) {
2763 dma_free_coherent(&adapter->pdev->dev,
2765 adapter->tx_ring.tx_status,
2766 adapter->tx_ring.tx_status_pa);
2768 adapter->tx_ring.tx_status = NULL;
2770 /* Free the memory for the tcb structures */
2771 kfree(adapter->tx_ring.tcb_ring);
2774 /* nic_send_packet - NIC specific send handler for version B silicon.
2775 * @adapter: pointer to our adapter
2776 * @tcb: pointer to struct tcb
2778 static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
2781 struct tx_desc desc[24]; /* 24 x 16 byte */
2783 u32 thiscopy, remainder;
2784 struct sk_buff *skb = tcb->skb;
2785 u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
2786 struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0];
2787 unsigned long flags;
2788 struct phy_device *phydev = adapter->phydev;
2789 dma_addr_t dma_addr;
2791 /* Part of the optimizations of this send routine restrict us to
2792 * sending 24 fragments at a pass. In practice we should never see
2793 * more than 5 fragments.
2795 * NOTE: The older version of this function (below) can handle any
2796 * number of fragments. If needed, we can call this function,
2797 * although it is less efficient.
2800 /* nr_frags should be no more than 18. */
2801 BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
2803 memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
2805 for (i = 0; i < nr_frags; i++) {
2806 /* If there is something in this element, lets get a
2807 * descriptor from the ring and get the necessary data
2810 /* If the fragments are smaller than a standard MTU,
2811 * then map them to a single descriptor in the Tx
2812 * Desc ring. However, if they're larger, as is
2813 * possible with support for jumbo packets, then
2814 * split them each across 2 descriptors.
2816 * This will work until we determine why the hardware
2817 * doesn't seem to like large fragments.
2819 if (skb_headlen(skb) <= 1514) {
2820 /* Low 16bits are length, high is vlan and
2821 * unused currently so zero
2823 desc[frag].len_vlan = skb_headlen(skb);
2824 dma_addr = dma_map_single(&adapter->pdev->dev,
2828 desc[frag].addr_lo = lower_32_bits(dma_addr);
2829 desc[frag].addr_hi = upper_32_bits(dma_addr);
2832 desc[frag].len_vlan = skb_headlen(skb) / 2;
2833 dma_addr = dma_map_single(&adapter->pdev->dev,
2835 (skb_headlen(skb) / 2),
2837 desc[frag].addr_lo = lower_32_bits(dma_addr);
2838 desc[frag].addr_hi = upper_32_bits(dma_addr);
2841 desc[frag].len_vlan = skb_headlen(skb) / 2;
2842 dma_addr = dma_map_single(&adapter->pdev->dev,
2844 (skb_headlen(skb) / 2),
2845 (skb_headlen(skb) / 2),
2847 desc[frag].addr_lo = lower_32_bits(dma_addr);
2848 desc[frag].addr_hi = upper_32_bits(dma_addr);
2852 desc[frag].len_vlan = frags[i - 1].size;
2853 dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
2858 desc[frag].addr_lo = lower_32_bits(dma_addr);
2859 desc[frag].addr_hi = upper_32_bits(dma_addr);
2864 if (phydev && phydev->speed == SPEED_1000) {
2865 if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) {
2866 /* Last element & Interrupt flag */
2867 desc[frag - 1].flags =
2868 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2869 adapter->tx_ring.since_irq = 0;
2870 } else { /* Last element */
2871 desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
2874 desc[frag - 1].flags =
2875 TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
2877 desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
2879 tcb->index_start = adapter->tx_ring.send_idx;
2882 spin_lock_irqsave(&adapter->send_hw_lock, flags);
2884 thiscopy = NUM_DESC_PER_RING_TX - INDEX10(adapter->tx_ring.send_idx);
2886 if (thiscopy >= frag) {
2890 remainder = frag - thiscopy;
2893 memcpy(adapter->tx_ring.tx_desc_ring +
2894 INDEX10(adapter->tx_ring.send_idx), desc,
2895 sizeof(struct tx_desc) * thiscopy);
2897 add_10bit(&adapter->tx_ring.send_idx, thiscopy);
2899 if (INDEX10(adapter->tx_ring.send_idx) == 0 ||
2900 INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) {
2901 adapter->tx_ring.send_idx &= ~ET_DMA10_MASK;
2902 adapter->tx_ring.send_idx ^= ET_DMA10_WRAP;
2906 memcpy(adapter->tx_ring.tx_desc_ring,
2908 sizeof(struct tx_desc) * remainder);
2910 add_10bit(&adapter->tx_ring.send_idx, remainder);
2913 if (INDEX10(adapter->tx_ring.send_idx) == 0) {
2914 if (adapter->tx_ring.send_idx)
2915 tcb->index = NUM_DESC_PER_RING_TX - 1;
2917 tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
2919 tcb->index = adapter->tx_ring.send_idx - 1;
2921 spin_lock(&adapter->tcb_send_qlock);
2923 if (adapter->tx_ring.send_tail)
2924 adapter->tx_ring.send_tail->next = tcb;
2926 adapter->tx_ring.send_head = tcb;
2928 adapter->tx_ring.send_tail = tcb;
2930 WARN_ON(tcb->next != NULL);
2932 adapter->tx_ring.used++;
2934 spin_unlock(&adapter->tcb_send_qlock);
2936 /* Write the new write pointer back to the device. */
2937 writel(adapter->tx_ring.send_idx,
2938 &adapter->regs->txdma.service_request);
2940 /* For Gig only, we use Tx Interrupt coalescing. Enable the software
2941 * timer to wake us up if this packet isn't followed by N more.
2943 if (phydev && phydev->speed == SPEED_1000) {
2944 writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
2945 &adapter->regs->global.watchdog_timer);
2947 spin_unlock_irqrestore(&adapter->send_hw_lock, flags);
2952 /* send_packet - Do the work to send a packet
2954 * Assumption: Send spinlock has been acquired
2956 static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
2959 struct tcb *tcb = NULL;
2961 unsigned long flags;
2963 /* All packets must have at least a MAC address and a protocol type */
2964 if (skb->len < ETH_HLEN)
2967 /* Get a TCB for this packet */
2968 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
2970 tcb = adapter->tx_ring.tcb_qhead;
2973 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2977 adapter->tx_ring.tcb_qhead = tcb->next;
2979 if (adapter->tx_ring.tcb_qhead == NULL)
2980 adapter->tx_ring.tcb_qtail = NULL;
2982 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
2986 if (skb->data != NULL && skb_headlen(skb) >= 6) {
2987 shbufva = (u16 *) skb->data;
2989 if ((shbufva[0] == 0xffff) &&
2990 (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff))
2991 tcb->flags |= FMP_DEST_BROAD;
2992 else if ((shbufva[0] & 0x3) == 0x0001)
2993 tcb->flags |= FMP_DEST_MULTI;
2998 /* Call the NIC specific send handler. */
2999 status = nic_send_packet(adapter, tcb);
3002 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3004 if (adapter->tx_ring.tcb_qtail)
3005 adapter->tx_ring.tcb_qtail->next = tcb;
3007 /* Apparently ready Q is empty. */
3008 adapter->tx_ring.tcb_qhead = tcb;
3010 adapter->tx_ring.tcb_qtail = tcb;
3011 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3014 WARN_ON(adapter->tx_ring.used > NUM_TCB);
3018 /* et131x_send_packets - This function is called by the OS to send packets */
3019 static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev)
3022 struct et131x_adapter *adapter = netdev_priv(netdev);
3024 /* Send these packets
3026 * NOTE: The Linux Tx entry point is only given one packet at a time
3027 * to Tx, so the PacketCount and it's array used makes no sense here
3030 /* TCB is not available */
3031 if (adapter->tx_ring.used >= NUM_TCB) {
3032 /* NOTE: If there's an error on send, no need to queue the
3033 * packet under Linux; if we just send an error up to the
3034 * netif layer, it will resend the skb to us.
3038 /* We need to see if the link is up; if it's not, make the
3039 * netif layer think we're good and drop the packet
3041 if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
3042 !netif_carrier_ok(netdev)) {
3043 dev_kfree_skb_any(skb);
3046 adapter->net_stats.tx_dropped++;
3048 status = send_packet(skb, adapter);
3049 if (status != 0 && status != -ENOMEM) {
3050 /* On any other error, make netif think we're
3051 * OK and drop the packet
3053 dev_kfree_skb_any(skb);
3055 adapter->net_stats.tx_dropped++;
3062 /* free_send_packet - Recycle a struct tcb
3063 * @adapter: pointer to our adapter
3064 * @tcb: pointer to struct tcb
3066 * Complete the packet if necessary
3067 * Assumption - Send spinlock has been acquired
3069 static inline void free_send_packet(struct et131x_adapter *adapter,
3072 unsigned long flags;
3073 struct tx_desc *desc = NULL;
3074 struct net_device_stats *stats = &adapter->net_stats;
3077 if (tcb->flags & FMP_DEST_BROAD)
3078 atomic_inc(&adapter->stats.broadcast_pkts_xmtd);
3079 else if (tcb->flags & FMP_DEST_MULTI)
3080 atomic_inc(&adapter->stats.multicast_pkts_xmtd);
3082 atomic_inc(&adapter->stats.unicast_pkts_xmtd);
3085 stats->tx_bytes += tcb->skb->len;
3087 /* Iterate through the TX descriptors on the ring
3088 * corresponding to this packet and umap the fragments
3092 desc = (struct tx_desc *)
3093 (adapter->tx_ring.tx_desc_ring +
3094 INDEX10(tcb->index_start));
3096 dma_addr = desc->addr_lo;
3097 dma_addr |= (u64)desc->addr_hi << 32;
3099 dma_unmap_single(&adapter->pdev->dev,
3101 desc->len_vlan, DMA_TO_DEVICE);
3103 add_10bit(&tcb->index_start, 1);
3104 if (INDEX10(tcb->index_start) >=
3105 NUM_DESC_PER_RING_TX) {
3106 tcb->index_start &= ~ET_DMA10_MASK;
3107 tcb->index_start ^= ET_DMA10_WRAP;
3109 } while (desc != (adapter->tx_ring.tx_desc_ring +
3110 INDEX10(tcb->index)));
3112 dev_kfree_skb_any(tcb->skb);
3115 memset(tcb, 0, sizeof(struct tcb));
3117 /* Add the TCB to the Ready Q */
3118 spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
3120 adapter->net_stats.tx_packets++;
3122 if (adapter->tx_ring.tcb_qtail)
3123 adapter->tx_ring.tcb_qtail->next = tcb;
3125 /* Apparently ready Q is empty. */
3126 adapter->tx_ring.tcb_qhead = tcb;
3128 adapter->tx_ring.tcb_qtail = tcb;
3130 spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
3131 WARN_ON(adapter->tx_ring.used < 0);
3134 /* et131x_free_busy_send_packets - Free and complete the stopped active sends
3136 * Assumption - Send spinlock has been acquired
3138 static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
3141 unsigned long flags;
3144 /* Any packets being sent? Check the first TCB on the send list */
3145 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3147 tcb = adapter->tx_ring.send_head;
3149 while (tcb != NULL && freed < NUM_TCB) {
3150 struct tcb *next = tcb->next;
3152 adapter->tx_ring.send_head = next;
3155 adapter->tx_ring.send_tail = NULL;
3157 adapter->tx_ring.used--;
3159 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3162 free_send_packet(adapter, tcb);
3164 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3166 tcb = adapter->tx_ring.send_head;
3169 WARN_ON(freed == NUM_TCB);
3171 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3173 adapter->tx_ring.used = 0;
3176 /* et131x_handle_send_interrupt - Interrupt handler for sending processing
3178 * Re-claim the send resources, complete sends and get more to send from
3179 * the send wait queue.
3181 * Assumption - Send spinlock has been acquired
3183 static void et131x_handle_send_interrupt(struct et131x_adapter *adapter)
3185 unsigned long flags;
3190 serviced = readl(&adapter->regs->txdma.new_service_complete);
3191 index = INDEX10(serviced);
3193 /* Has the ring wrapped? Process any descriptors that do not have
3194 * the same "wrap" indicator as the current completion indicator
3196 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3198 tcb = adapter->tx_ring.send_head;
3201 ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
3202 index < INDEX10(tcb->index)) {
3203 adapter->tx_ring.used--;
3204 adapter->tx_ring.send_head = tcb->next;
3205 if (tcb->next == NULL)
3206 adapter->tx_ring.send_tail = NULL;
3208 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3209 free_send_packet(adapter, tcb);
3210 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3212 /* Goto the next packet */
3213 tcb = adapter->tx_ring.send_head;
3216 !((serviced ^ tcb->index) & ET_DMA10_WRAP)
3217 && index > (tcb->index & ET_DMA10_MASK)) {
3218 adapter->tx_ring.used--;
3219 adapter->tx_ring.send_head = tcb->next;
3220 if (tcb->next == NULL)
3221 adapter->tx_ring.send_tail = NULL;
3223 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3224 free_send_packet(adapter, tcb);
3225 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
3227 /* Goto the next packet */
3228 tcb = adapter->tx_ring.send_head;
3231 /* Wake up the queue when we hit a low-water mark */
3232 if (adapter->tx_ring.used <= NUM_TCB / 3)
3233 netif_wake_queue(adapter->netdev);
3235 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
3238 static int et131x_get_settings(struct net_device *netdev,
3239 struct ethtool_cmd *cmd)
3241 struct et131x_adapter *adapter = netdev_priv(netdev);
3243 return phy_ethtool_gset(adapter->phydev, cmd);
3246 static int et131x_set_settings(struct net_device *netdev,
3247 struct ethtool_cmd *cmd)
3249 struct et131x_adapter *adapter = netdev_priv(netdev);
3251 return phy_ethtool_sset(adapter->phydev, cmd);
3254 static int et131x_get_regs_len(struct net_device *netdev)
3256 #define ET131X_REGS_LEN 256
3257 return ET131X_REGS_LEN * sizeof(u32);
3260 static void et131x_get_regs(struct net_device *netdev,
3261 struct ethtool_regs *regs, void *regs_data)
3263 struct et131x_adapter *adapter = netdev_priv(netdev);
3264 struct address_map __iomem *aregs = adapter->regs;
3265 u32 *regs_buff = regs_data;
3269 memset(regs_data, 0, et131x_get_regs_len(netdev));
3271 regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
3272 adapter->pdev->device;
3275 et131x_mii_read(adapter, MII_BMCR, &tmp);
3276 regs_buff[num++] = tmp;
3277 et131x_mii_read(adapter, MII_BMSR, &tmp);
3278 regs_buff[num++] = tmp;
3279 et131x_mii_read(adapter, MII_PHYSID1, &tmp);
3280 regs_buff[num++] = tmp;
3281 et131x_mii_read(adapter, MII_PHYSID2, &tmp);
3282 regs_buff[num++] = tmp;
3283 et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
3284 regs_buff[num++] = tmp;
3285 et131x_mii_read(adapter, MII_LPA, &tmp);
3286 regs_buff[num++] = tmp;
3287 et131x_mii_read(adapter, MII_EXPANSION, &tmp);
3288 regs_buff[num++] = tmp;
3289 /* Autoneg next page transmit reg */
3290 et131x_mii_read(adapter, 0x07, &tmp);
3291 regs_buff[num++] = tmp;
3292 /* Link partner next page reg */
3293 et131x_mii_read(adapter, 0x08, &tmp);
3294 regs_buff[num++] = tmp;
3295 et131x_mii_read(adapter, MII_CTRL1000, &tmp);
3296 regs_buff[num++] = tmp;
3297 et131x_mii_read(adapter, MII_STAT1000, &tmp);
3298 regs_buff[num++] = tmp;
3299 et131x_mii_read(adapter, 0x0b, &tmp);
3300 regs_buff[num++] = tmp;
3301 et131x_mii_read(adapter, 0x0c, &tmp);
3302 regs_buff[num++] = tmp;
3303 et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
3304 regs_buff[num++] = tmp;
3305 et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
3306 regs_buff[num++] = tmp;
3307 et131x_mii_read(adapter, MII_ESTATUS, &tmp);
3308 regs_buff[num++] = tmp;
3310 et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
3311 regs_buff[num++] = tmp;
3312 et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
3313 regs_buff[num++] = tmp;
3314 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
3315 regs_buff[num++] = tmp;
3316 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
3317 regs_buff[num++] = tmp;
3318 et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
3319 regs_buff[num++] = tmp;
3321 et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
3322 regs_buff[num++] = tmp;
3323 et131x_mii_read(adapter, PHY_CONFIG, &tmp);
3324 regs_buff[num++] = tmp;
3325 et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
3326 regs_buff[num++] = tmp;
3327 et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
3328 regs_buff[num++] = tmp;
3329 et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
3330 regs_buff[num++] = tmp;
3331 et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
3332 regs_buff[num++] = tmp;
3333 et131x_mii_read(adapter, PHY_LED_1, &tmp);
3334 regs_buff[num++] = tmp;
3335 et131x_mii_read(adapter, PHY_LED_2, &tmp);
3336 regs_buff[num++] = tmp;
3339 regs_buff[num++] = readl(&aregs->global.txq_start_addr);
3340 regs_buff[num++] = readl(&aregs->global.txq_end_addr);
3341 regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
3342 regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
3343 regs_buff[num++] = readl(&aregs->global.pm_csr);
3344 regs_buff[num++] = adapter->stats.interrupt_status;
3345 regs_buff[num++] = readl(&aregs->global.int_mask);
3346 regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
3347 regs_buff[num++] = readl(&aregs->global.int_status_alias);
3348 regs_buff[num++] = readl(&aregs->global.sw_reset);
3349 regs_buff[num++] = readl(&aregs->global.slv_timer);
3350 regs_buff[num++] = readl(&aregs->global.msi_config);
3351 regs_buff[num++] = readl(&aregs->global.loopback);
3352 regs_buff[num++] = readl(&aregs->global.watchdog_timer);
3355 regs_buff[num++] = readl(&aregs->txdma.csr);
3356 regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
3357 regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
3358 regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
3359 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
3360 regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
3361 regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
3362 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
3363 regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
3364 regs_buff[num++] = readl(&aregs->txdma.service_request);
3365 regs_buff[num++] = readl(&aregs->txdma.service_complete);
3366 regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
3367 regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
3368 regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
3369 regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
3370 regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
3371 regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
3372 regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
3373 regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
3374 regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
3375 regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
3376 regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
3377 regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
3378 regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
3379 regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
3380 regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
3383 regs_buff[num++] = readl(&aregs->rxdma.csr);
3384 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
3385 regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
3386 regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
3387 regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
3388 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
3389 regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
3390 regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
3391 regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
3392 regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
3393 regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
3394 regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
3395 regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
3396 regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
3397 regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
3398 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
3399 regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
3400 regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
3401 regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
3402 regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
3403 regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
3404 regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
3405 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
3406 regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
3407 regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
3408 regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
3409 regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
3410 regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
3411 regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
3414 static void et131x_get_drvinfo(struct net_device *netdev,
3415 struct ethtool_drvinfo *info)
3417 struct et131x_adapter *adapter = netdev_priv(netdev);
3419 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
3420 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
3421 strlcpy(info->bus_info, pci_name(adapter->pdev),
3422 sizeof(info->bus_info));
3425 static struct ethtool_ops et131x_ethtool_ops = {
3426 .get_settings = et131x_get_settings,
3427 .set_settings = et131x_set_settings,
3428 .get_drvinfo = et131x_get_drvinfo,
3429 .get_regs_len = et131x_get_regs_len,
3430 .get_regs = et131x_get_regs,
3431 .get_link = ethtool_op_get_link,
3434 /* et131x_hwaddr_init - set up the MAC Address on the ET1310 */
3435 static void et131x_hwaddr_init(struct et131x_adapter *adapter)
3437 /* If have our default mac from init and no mac address from
3438 * EEPROM then we need to generate the last octet and set it on the
3441 if (is_zero_ether_addr(adapter->rom_addr)) {
3442 /* We need to randomly generate the last octet so we
3443 * decrease our chances of setting the mac address to
3444 * same as another one of our cards in the system
3446 get_random_bytes(&adapter->addr[5], 1);
3447 /* We have the default value in the register we are
3448 * working with so we need to copy the current
3449 * address into the permanent address
3451 memcpy(adapter->rom_addr,
3452 adapter->addr, ETH_ALEN);
3454 /* We do not have an override address, so set the
3455 * current address to the permanent address and add
3458 memcpy(adapter->addr,
3459 adapter->rom_addr, ETH_ALEN);
3463 /* et131x_pci_init - initial PCI setup
3465 * Perform the initial setup of PCI registers and if possible initialise
3466 * the MAC address. At this point the I/O registers have yet to be mapped
3468 static int et131x_pci_init(struct et131x_adapter *adapter,
3469 struct pci_dev *pdev)
3474 rc = et131x_init_eeprom(adapter);
3478 if (!pci_is_pcie(pdev)) {
3479 dev_err(&pdev->dev, "Missing PCIe capabilities\n");
3483 /* Let's set up the PORT LOGIC Register. */
3485 /* Program the Ack/Nak latency and replay timers */
3486 max_payload = pdev->pcie_mpss;
3488 if (max_payload < 2) {
3489 static const u16 acknak[2] = { 0x76, 0xD0 };
3490 static const u16 replay[2] = { 0x1E0, 0x2ED };
3492 if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
3493 acknak[max_payload])) {
3495 "Could not write PCI config space for ACK/NAK\n");
3498 if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
3499 replay[max_payload])) {
3501 "Could not write PCI config space for Replay Timer\n");
3506 /* l0s and l1 latency timers. We are using default values.
3507 * Representing 001 for L0s and 010 for L1
3509 if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
3511 "Could not write PCI config space for Latency Timers\n");
3515 /* Change the max read size to 2k */
3516 if (pcie_set_readrq(pdev, 2048)) {
3518 "Couldn't change PCI config space for Max read size\n");
3522 /* Get MAC address from config space if an eeprom exists, otherwise
3523 * the MAC address there will not be valid
3525 if (!adapter->has_eeprom) {
3526 et131x_hwaddr_init(adapter);
3530 for (i = 0; i < ETH_ALEN; i++) {
3531 if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
3532 adapter->rom_addr + i)) {
3533 dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
3537 memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
3545 /* et131x_error_timer_handler
3546 * @data: timer-specific variable; here a pointer to our adapter structure
3548 * The routine called when the error timer expires, to track the number of
3551 static void et131x_error_timer_handler(unsigned long data)
3553 struct et131x_adapter *adapter = (struct et131x_adapter *) data;
3554 struct phy_device *phydev = adapter->phydev;
3556 if (et1310_in_phy_coma(adapter)) {
3557 /* Bring the device immediately out of coma, to
3558 * prevent it from sleeping indefinitely, this
3559 * mechanism could be improved!
3561 et1310_disable_phy_coma(adapter);
3562 adapter->boot_coma = 20;
3564 et1310_update_macstat_host_counters(adapter);
3567 if (!phydev->link && adapter->boot_coma < 11)
3568 adapter->boot_coma++;
3570 if (adapter->boot_coma == 10) {
3571 if (!phydev->link) {
3572 if (!et1310_in_phy_coma(adapter)) {
3573 /* NOTE - This was originally a 'sync with
3574 * interrupt'. How to do that under Linux?
3576 et131x_enable_interrupts(adapter);
3577 et1310_enable_phy_coma(adapter);
3582 /* This is a periodic timer, so reschedule */
3583 mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000);
3586 /* et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx */
3587 static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
3589 et131x_tx_dma_memory_free(adapter);
3590 et131x_rx_dma_memory_free(adapter);
3593 /* et131x_adapter_memory_alloc
3594 * Allocate all the memory blocks for send, receive and others.
3596 static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
3600 /* Allocate memory for the Tx Ring */
3601 status = et131x_tx_dma_memory_alloc(adapter);
3603 dev_err(&adapter->pdev->dev,
3604 "et131x_tx_dma_memory_alloc FAILED\n");
3607 /* Receive buffer memory allocation */
3608 status = et131x_rx_dma_memory_alloc(adapter);
3610 dev_err(&adapter->pdev->dev,
3611 "et131x_rx_dma_memory_alloc FAILED\n");
3612 et131x_tx_dma_memory_free(adapter);
3616 /* Init receive data structures */
3617 status = et131x_init_recv(adapter);
3619 dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
3620 et131x_adapter_memory_free(adapter);
3625 static void et131x_adjust_link(struct net_device *netdev)
3627 struct et131x_adapter *adapter = netdev_priv(netdev);
3628 struct phy_device *phydev = adapter->phydev;
3632 if (phydev->link == adapter->link)
3635 /* Check to see if we are in coma mode and if
3636 * so, disable it because we will not be able
3637 * to read PHY values until we are out.
3639 if (et1310_in_phy_coma(adapter))
3640 et1310_disable_phy_coma(adapter);
3642 adapter->link = phydev->link;
3643 phy_print_status(phydev);
3646 adapter->boot_coma = 20;
3647 if (phydev->speed == SPEED_10) {
3650 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3652 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3654 et131x_mii_write(adapter, PHY_INDEX_REG,
3655 register18 | 0x8402);
3656 et131x_mii_write(adapter, PHY_DATA_REG,
3658 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3662 et1310_config_flow_control(adapter);
3664 if (phydev->speed == SPEED_1000 &&
3665 adapter->registry_jumbo_packet > 2048) {
3668 et131x_mii_read(adapter, PHY_CONFIG, ®);
3669 reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
3670 reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
3671 et131x_mii_write(adapter, PHY_CONFIG, reg);
3674 et131x_set_rx_dma_timer(adapter);
3675 et1310_config_mac_regs2(adapter);
3677 adapter->boot_coma = 0;
3679 if (phydev->speed == SPEED_10) {
3682 et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
3684 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3686 et131x_mii_write(adapter, PHY_INDEX_REG,
3687 register18 | 0x8402);
3688 et131x_mii_write(adapter, PHY_DATA_REG,
3690 et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG,
3694 /* Free the packets being actively sent & stopped */
3695 et131x_free_busy_send_packets(adapter);
3697 /* Re-initialize the send structures */
3698 et131x_init_send(adapter);
3700 /* Bring the device back to the state it was during
3701 * init prior to autonegotiation being complete. This
3702 * way, when we get the auto-neg complete interrupt,
3703 * we can complete init by calling config_mac_regs2.
3705 et131x_soft_reset(adapter);
3707 /* Setup ET1310 as per the documentation */
3708 et131x_adapter_setup(adapter);
3710 /* perform reset of tx/rx */
3711 et131x_disable_txrx(netdev);
3712 et131x_enable_txrx(netdev);
3716 static int et131x_mii_probe(struct net_device *netdev)
3718 struct et131x_adapter *adapter = netdev_priv(netdev);
3719 struct phy_device *phydev = NULL;
3721 phydev = phy_find_first(adapter->mii_bus);
3723 dev_err(&adapter->pdev->dev, "no PHY found\n");
3727 phydev = phy_connect(netdev, dev_name(&phydev->dev),
3728 &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
3730 if (IS_ERR(phydev)) {
3731 dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
3732 return PTR_ERR(phydev);
3735 phydev->supported &= (SUPPORTED_10baseT_Half
3736 | SUPPORTED_10baseT_Full
3737 | SUPPORTED_100baseT_Half
3738 | SUPPORTED_100baseT_Full
3743 if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
3744 phydev->supported |= SUPPORTED_1000baseT_Full;
3746 phydev->advertising = phydev->supported;
3747 adapter->phydev = phydev;
3749 dev_info(&adapter->pdev->dev,
3750 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
3751 phydev->drv->name, dev_name(&phydev->dev));
3756 /* et131x_adapter_init
3758 * Initialize the data structures for the et131x_adapter object and link
3759 * them together with the platform provided device structures.
3761 static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
3762 struct pci_dev *pdev)
3764 static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
3766 struct et131x_adapter *adapter;
3768 /* Allocate private adapter struct and copy in relevant information */
3769 adapter = netdev_priv(netdev);
3770 adapter->pdev = pci_dev_get(pdev);
3771 adapter->netdev = netdev;
3773 /* Initialize spinlocks here */
3774 spin_lock_init(&adapter->lock);
3775 spin_lock_init(&adapter->tcb_send_qlock);
3776 spin_lock_init(&adapter->tcb_ready_qlock);
3777 spin_lock_init(&adapter->send_hw_lock);
3778 spin_lock_init(&adapter->rcv_lock);
3779 spin_lock_init(&adapter->fbr_lock);
3781 adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
3783 /* Set the MAC address to a default */
3784 memcpy(adapter->addr, default_mac, ETH_ALEN);
3789 /* et131x_pci_remove
3791 * Registered in the pci_driver structure, this function is called when the
3792 * PCI subsystem detects that a PCI device which matches the information
3793 * contained in the pci_device_id table has been removed.
3795 static void et131x_pci_remove(struct pci_dev *pdev)
3797 struct net_device *netdev = pci_get_drvdata(pdev);
3798 struct et131x_adapter *adapter = netdev_priv(netdev);
3800 unregister_netdev(netdev);
3801 phy_disconnect(adapter->phydev);
3802 mdiobus_unregister(adapter->mii_bus);
3803 cancel_work_sync(&adapter->task);
3804 kfree(adapter->mii_bus->irq);
3805 mdiobus_free(adapter->mii_bus);
3807 et131x_adapter_memory_free(adapter);
3808 iounmap(adapter->regs);
3811 free_netdev(netdev);
3812 pci_release_regions(pdev);
3813 pci_disable_device(pdev);
3816 /* et131x_up - Bring up a device for use. */
3817 static void et131x_up(struct net_device *netdev)
3819 struct et131x_adapter *adapter = netdev_priv(netdev);
3821 et131x_enable_txrx(netdev);
3822 phy_start(adapter->phydev);
3825 /* et131x_down - Bring down the device */
3826 static void et131x_down(struct net_device *netdev)
3828 struct et131x_adapter *adapter = netdev_priv(netdev);
3830 /* Save the timestamp for the TX watchdog, prevent a timeout */
3831 netdev->trans_start = jiffies;
3833 phy_stop(adapter->phydev);
3834 et131x_disable_txrx(netdev);
3837 #ifdef CONFIG_PM_SLEEP
3838 static int et131x_suspend(struct device *dev)
3840 struct pci_dev *pdev = to_pci_dev(dev);
3841 struct net_device *netdev = pci_get_drvdata(pdev);
3843 if (netif_running(netdev)) {
3844 netif_device_detach(netdev);
3845 et131x_down(netdev);
3846 pci_save_state(pdev);
3852 static int et131x_resume(struct device *dev)
3854 struct pci_dev *pdev = to_pci_dev(dev);
3855 struct net_device *netdev = pci_get_drvdata(pdev);
3857 if (netif_running(netdev)) {
3858 pci_restore_state(pdev);
3860 netif_device_attach(netdev);
3866 static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
3867 #define ET131X_PM_OPS (&et131x_pm_ops)
3869 #define ET131X_PM_OPS NULL
3872 /* et131x_isr - The Interrupt Service Routine for the driver.
3873 * @irq: the IRQ on which the interrupt was received.
3874 * @dev_id: device-specific info (here a pointer to a net_device struct)
3876 * Returns a value indicating if the interrupt was handled.
3878 static irqreturn_t et131x_isr(int irq, void *dev_id)
3880 bool handled = true;
3881 struct net_device *netdev = (struct net_device *)dev_id;
3882 struct et131x_adapter *adapter = NULL;
3885 if (!netif_device_present(netdev)) {
3890 adapter = netdev_priv(netdev);
3892 /* If the adapter is in low power state, then it should not
3893 * recognize any interrupt
3896 /* Disable Device Interrupts */
3897 et131x_disable_interrupts(adapter);
3899 /* Get a copy of the value in the interrupt status register
3900 * so we can process the interrupting section
3902 status = readl(&adapter->regs->global.int_status);
3904 if (adapter->flowcontrol == FLOW_TXONLY ||
3905 adapter->flowcontrol == FLOW_BOTH) {
3906 status &= ~INT_MASK_ENABLE;
3908 status &= ~INT_MASK_ENABLE_NO_FLOW;
3911 /* Make sure this is our interrupt */
3914 et131x_enable_interrupts(adapter);
3918 /* This is our interrupt, so process accordingly */
3920 if (status & ET_INTR_WATCHDOG) {
3921 struct tcb *tcb = adapter->tx_ring.send_head;
3924 if (++tcb->stale > 1)
3925 status |= ET_INTR_TXDMA_ISR;
3927 if (adapter->rx_ring.unfinished_receives)
3928 status |= ET_INTR_RXDMA_XFR_DONE;
3929 else if (tcb == NULL)
3930 writel(0, &adapter->regs->global.watchdog_timer);
3932 status &= ~ET_INTR_WATCHDOG;
3936 /* This interrupt has in some way been "handled" by
3937 * the ISR. Either it was a spurious Rx interrupt, or
3938 * it was a Tx interrupt that has been filtered by
3941 et131x_enable_interrupts(adapter);
3945 /* We need to save the interrupt status value for use in our
3946 * DPC. We will clear the software copy of that in that
3949 adapter->stats.interrupt_status = status;
3951 /* Schedule the ISR handler as a bottom-half task in the
3952 * kernel's tq_immediate queue, and mark the queue for
3955 schedule_work(&adapter->task);
3957 return IRQ_RETVAL(handled);
3960 /* et131x_isr_handler - The ISR handler
3962 * scheduled to run in a deferred context by the ISR. This is where the ISR's
3963 * work actually gets done.
3965 static void et131x_isr_handler(struct work_struct *work)
3967 struct et131x_adapter *adapter =
3968 container_of(work, struct et131x_adapter, task);
3969 u32 status = adapter->stats.interrupt_status;
3970 struct address_map __iomem *iomem = adapter->regs;
3972 /* These first two are by far the most common. Once handled, we clear
3973 * their two bits in the status word. If the word is now zero, we
3976 /* Handle all the completed Transmit interrupts */
3977 if (status & ET_INTR_TXDMA_ISR)
3978 et131x_handle_send_interrupt(adapter);
3980 /* Handle all the completed Receives interrupts */
3981 if (status & ET_INTR_RXDMA_XFR_DONE)
3982 et131x_handle_recv_interrupt(adapter);
3984 status &= ~(ET_INTR_TXDMA_ERR | ET_INTR_RXDMA_XFR_DONE);
3989 /* Handle the TXDMA Error interrupt */
3990 if (status & ET_INTR_TXDMA_ERR) {
3991 /* Following read also clears the register (COR) */
3992 u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
3994 dev_warn(&adapter->pdev->dev,
3995 "TXDMA_ERR interrupt, error = %d\n",
3999 /* Handle Free Buffer Ring 0 and 1 Low interrupt */
4000 if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
4001 /* This indicates the number of unused buffers in RXDMA free
4002 * buffer ring 0 is <= the limit you programmed. Free buffer
4003 * resources need to be returned. Free buffers are consumed as
4004 * packets are passed from the network to the host. The host
4005 * becomes aware of the packets from the contents of the packet
4006 * status ring. This ring is queried when the packet done
4007 * interrupt occurs. Packets are then passed to the OS. When
4008 * the OS is done with the packets the resources can be
4009 * returned to the ET1310 for re-use. This interrupt is one
4010 * method of returning resources.
4013 /* If the user has flow control on, then we will
4014 * send a pause packet, otherwise just exit
4016 if (adapter->flowcontrol == FLOW_TXONLY ||
4017 adapter->flowcontrol == FLOW_BOTH) {
4020 /* Tell the device to send a pause packet via the back
4021 * pressure register (bp req and bp xon/xoff)
4023 pm_csr = readl(&iomem->global.pm_csr);
4024 if (!et1310_in_phy_coma(adapter))
4025 writel(3, &iomem->txmac.bp_ctrl);
4029 /* Handle Packet Status Ring Low Interrupt */
4030 if (status & ET_INTR_RXDMA_STAT_LOW) {
4031 /* Same idea as with the two Free Buffer Rings. Packets going
4032 * from the network to the host each consume a free buffer
4033 * resource and a packet status resource. These resoures are
4034 * passed to the OS. When the OS is done with the resources,
4035 * they need to be returned to the ET1310. This is one method
4036 * of returning the resources.
4040 /* Handle RXDMA Error Interrupt */
4041 if (status & ET_INTR_RXDMA_ERR) {
4042 /* The rxdma_error interrupt is sent when a time-out on a
4043 * request issued by the JAGCore has occurred or a completion is
4044 * returned with an un-successful status. In both cases the
4045 * request is considered complete. The JAGCore will
4046 * automatically re-try the request in question. Normally
4047 * information on events like these are sent to the host using
4048 * the "Advanced Error Reporting" capability. This interrupt is
4049 * another way of getting similar information. The only thing
4050 * required is to clear the interrupt by reading the ISR in the
4051 * global resources. The JAGCore will do a re-try on the
4052 * request. Normally you should never see this interrupt. If
4053 * you start to see this interrupt occurring frequently then
4054 * something bad has occurred. A reset might be the thing to do.
4058 dev_warn(&adapter->pdev->dev,
4059 "RxDMA_ERR interrupt, error %x\n",
4060 readl(&iomem->txmac.tx_test));
4063 /* Handle the Wake on LAN Event */
4064 if (status & ET_INTR_WOL) {
4065 /* This is a secondary interrupt for wake on LAN. The driver
4066 * should never see this, if it does, something serious is
4067 * wrong. We will TRAP the message when we are in DBG mode,
4068 * otherwise we will ignore it.
4070 dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
4073 /* Let's move on to the TxMac */
4074 if (status & ET_INTR_TXMAC) {
4075 u32 err = readl(&iomem->txmac.err);
4077 /* When any of the errors occur and TXMAC generates an
4078 * interrupt to report these errors, it usually means that
4079 * TXMAC has detected an error in the data stream retrieved
4080 * from the on-chip Tx Q. All of these errors are catastrophic
4081 * and TXMAC won't be able to recover data when these errors
4082 * occur. In a nutshell, the whole Tx path will have to be reset
4083 * and re-configured afterwards.
4085 dev_warn(&adapter->pdev->dev,
4086 "TXMAC interrupt, error 0x%08x\n",
4089 /* If we are debugging, we want to see this error, otherwise we
4090 * just want the device to be reset and continue
4094 /* Handle RXMAC Interrupt */
4095 if (status & ET_INTR_RXMAC) {
4096 /* These interrupts are catastrophic to the device, what we need
4097 * to do is disable the interrupts and set the flag to cause us
4098 * to reset so we can solve this issue.
4100 /* MP_SET_FLAG( adapter, FMP_ADAPTER_HARDWARE_ERROR); */
4102 dev_warn(&adapter->pdev->dev,
4103 "RXMAC interrupt, error 0x%08x. Requesting reset\n",
4104 readl(&iomem->rxmac.err_reg));
4106 dev_warn(&adapter->pdev->dev,
4107 "Enable 0x%08x, Diag 0x%08x\n",
4108 readl(&iomem->rxmac.ctrl),
4109 readl(&iomem->rxmac.rxq_diag));
4111 /* If we are debugging, we want to see this error, otherwise we
4112 * just want the device to be reset and continue
4116 /* Handle MAC_STAT Interrupt */
4117 if (status & ET_INTR_MAC_STAT) {
4118 /* This means at least one of the un-masked counters in the
4119 * MAC_STAT block has rolled over. Use this to maintain the top,
4120 * software managed bits of the counter(s).
4122 et1310_handle_macstat_interrupt(adapter);
4125 /* Handle SLV Timeout Interrupt */
4126 if (status & ET_INTR_SLV_TIMEOUT) {
4127 /* This means a timeout has occurred on a read or write request
4128 * to one of the JAGCore registers. The Global Resources block
4129 * has terminated the request and on a read request, returned a
4130 * "fake" value. The most likely reasons are: Bad Address or the
4131 * addressed module is in a power-down state and can't respond.
4135 et131x_enable_interrupts(adapter);
4138 /* et131x_stats - Return the current device statistics */
4139 static struct net_device_stats *et131x_stats(struct net_device *netdev)
4141 struct et131x_adapter *adapter = netdev_priv(netdev);
4142 struct net_device_stats *stats = &adapter->net_stats;
4143 struct ce_stats *devstat = &adapter->stats;
4145 stats->rx_errors = devstat->rx_length_errs +
4146 devstat->rx_align_errs +
4147 devstat->rx_crc_errs +
4148 devstat->rx_code_violations +
4149 devstat->rx_other_errs;
4150 stats->tx_errors = devstat->tx_max_pkt_errs;
4151 stats->multicast = devstat->multicast_pkts_rcvd;
4152 stats->collisions = devstat->tx_collisions;
4154 stats->rx_length_errors = devstat->rx_length_errs;
4155 stats->rx_over_errors = devstat->rx_overflows;
4156 stats->rx_crc_errors = devstat->rx_crc_errs;
4158 /* NOTE: These stats don't have corresponding values in CE_STATS,
4159 * so we're going to have to update these directly from within the
4162 /* stats->rx_bytes = 20; devstat->; */
4163 /* stats->tx_bytes = 20; devstat->; */
4164 /* stats->rx_dropped = devstat->; */
4165 /* stats->tx_dropped = devstat->; */
4167 /* NOTE: Not used, can't find analogous statistics */
4168 /* stats->rx_frame_errors = devstat->; */
4169 /* stats->rx_fifo_errors = devstat->; */
4170 /* stats->rx_missed_errors = devstat->; */
4172 /* stats->tx_aborted_errors = devstat->; */
4173 /* stats->tx_carrier_errors = devstat->; */
4174 /* stats->tx_fifo_errors = devstat->; */
4175 /* stats->tx_heartbeat_errors = devstat->; */
4176 /* stats->tx_window_errors = devstat->; */
4180 /* et131x_open - Open the device for use. */
4181 static int et131x_open(struct net_device *netdev)
4183 struct et131x_adapter *adapter = netdev_priv(netdev);
4184 struct pci_dev *pdev = adapter->pdev;
4185 unsigned int irq = pdev->irq;
4188 /* Start the timer to track NIC errors */
4189 init_timer(&adapter->error_timer);
4190 adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000;
4191 adapter->error_timer.function = et131x_error_timer_handler;
4192 adapter->error_timer.data = (unsigned long)adapter;
4193 add_timer(&adapter->error_timer);
4195 result = request_irq(irq, et131x_isr,
4196 IRQF_SHARED, netdev->name, netdev);
4198 dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
4202 adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
4209 /* et131x_close - Close the device */
4210 static int et131x_close(struct net_device *netdev)
4212 struct et131x_adapter *adapter = netdev_priv(netdev);
4214 et131x_down(netdev);
4216 adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
4217 free_irq(adapter->pdev->irq, netdev);
4219 /* Stop the error timer */
4220 return del_timer_sync(&adapter->error_timer);
4223 /* et131x_ioctl - The I/O Control handler for the driver
4224 * @netdev: device on which the control request is being made
4225 * @reqbuf: a pointer to the IOCTL request buffer
4226 * @cmd: the IOCTL command code
4228 static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf,
4231 struct et131x_adapter *adapter = netdev_priv(netdev);
4233 if (!adapter->phydev)
4236 return phy_mii_ioctl(adapter->phydev, reqbuf, cmd);
4239 /* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
4240 * @adapter: pointer to our private adapter structure
4242 * FIXME: lot of dups with MAC code
4244 static int et131x_set_packet_filter(struct et131x_adapter *adapter)
4246 int filter = adapter->packet_filter;
4251 ctrl = readl(&adapter->regs->rxmac.ctrl);
4252 pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
4254 /* Default to disabled packet filtering. Enable it in the individual
4255 * case statements that require the device to filter something
4259 /* Set us to be in promiscuous mode so we receive everything, this
4260 * is also true when we get a packet filter of 0
4262 if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
4263 pf_ctrl &= ~7; /* Clear filter bits */
4265 /* Set us up with Multicast packet filtering. Three cases are
4266 * possible - (1) we have a multi-cast list, (2) we receive ALL
4267 * multicast entries or (3) we receive none.
4269 if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
4270 pf_ctrl &= ~2; /* Multicast filter bit */
4272 et1310_setup_device_for_multicast(adapter);
4277 /* Set us up with Unicast packet filtering */
4278 if (filter & ET131X_PACKET_TYPE_DIRECTED) {
4279 et1310_setup_device_for_unicast(adapter);
4284 /* Set us up with Broadcast packet filtering */
4285 if (filter & ET131X_PACKET_TYPE_BROADCAST) {
4286 pf_ctrl |= 1; /* Broadcast filter bit */
4291 /* Setup the receive mac configuration registers - Packet
4292 * Filter control + the enable / disable for packet filter
4293 * in the control reg.
4295 writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
4296 writel(ctrl, &adapter->regs->rxmac.ctrl);
4301 /* et131x_multicast - The handler to configure multicasting on the interface */
4302 static void et131x_multicast(struct net_device *netdev)
4304 struct et131x_adapter *adapter = netdev_priv(netdev);
4306 unsigned long flags;
4307 struct netdev_hw_addr *ha;
4310 spin_lock_irqsave(&adapter->lock, flags);
4312 /* Before we modify the platform-independent filter flags, store them
4313 * locally. This allows us to determine if anything's changed and if
4314 * we even need to bother the hardware
4316 packet_filter = adapter->packet_filter;
4318 /* Clear the 'multicast' flag locally; because we only have a single
4319 * flag to check multicast, and multiple multicast addresses can be
4320 * set, this is the easiest way to determine if more than one
4321 * multicast address is being set.
4323 packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4325 /* Check the net_device flags and set the device independent flags
4329 if (netdev->flags & IFF_PROMISC)
4330 adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
4332 adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
4334 if (netdev->flags & IFF_ALLMULTI)
4335 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4337 if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST)
4338 adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
4340 if (netdev_mc_count(netdev) < 1) {
4341 adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
4342 adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
4344 adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
4346 /* Set values in the private adapter struct */
4348 netdev_for_each_mc_addr(ha, netdev) {
4349 if (i == NIC_MAX_MCAST_LIST)
4351 memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN);
4353 adapter->multicast_addr_count = i;
4355 /* Are the new flags different from the previous ones? If not, then no
4356 * action is required
4358 * NOTE - This block will always update the multicast_list with the
4359 * hardware, even if the addresses aren't the same.
4361 if (packet_filter != adapter->packet_filter)
4362 et131x_set_packet_filter(adapter);
4364 spin_unlock_irqrestore(&adapter->lock, flags);
4367 /* et131x_tx - The handler to tx a packet on the device */
4368 static int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
4371 struct et131x_adapter *adapter = netdev_priv(netdev);
4373 /* stop the queue if it's getting full */
4374 if (adapter->tx_ring.used >= NUM_TCB - 1 &&
4375 !netif_queue_stopped(netdev))
4376 netif_stop_queue(netdev);
4378 /* Save the timestamp for the TX timeout watchdog */
4379 netdev->trans_start = jiffies;
4381 /* Call the device-specific data Tx routine */
4382 status = et131x_send_packets(skb, netdev);
4384 /* Check status and manage the netif queue if necessary */
4386 if (status == -ENOMEM)
4387 status = NETDEV_TX_BUSY;
4389 status = NETDEV_TX_OK;
4394 /* et131x_tx_timeout - Timeout handler
4396 * The handler called when a Tx request times out. The timeout period is
4397 * specified by the 'tx_timeo" element in the net_device structure (see
4398 * et131x_alloc_device() to see how this value is set).
4400 static void et131x_tx_timeout(struct net_device *netdev)
4402 struct et131x_adapter *adapter = netdev_priv(netdev);
4404 unsigned long flags;
4406 /* If the device is closed, ignore the timeout */
4407 if (~(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
4410 /* Any nonrecoverable hardware error?
4411 * Checks adapter->flags for any failure in phy reading
4413 if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
4416 /* Hardware failure? */
4417 if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
4418 dev_err(&adapter->pdev->dev, "hardware error - reset\n");
4422 /* Is send stuck? */
4423 spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
4425 tcb = adapter->tx_ring.send_head;
4430 if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
4431 spin_unlock_irqrestore(&adapter->tcb_send_qlock,
4434 dev_warn(&adapter->pdev->dev,
4435 "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n",
4439 adapter->net_stats.tx_errors++;
4441 /* perform reset of tx/rx */
4442 et131x_disable_txrx(netdev);
4443 et131x_enable_txrx(netdev);
4448 spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
4451 /* et131x_change_mtu - The handler called to change the MTU for the device */
4452 static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
4455 struct et131x_adapter *adapter = netdev_priv(netdev);
4457 /* Make sure the requested MTU is valid */
4458 if (new_mtu < 64 || new_mtu > 9216)
4461 et131x_disable_txrx(netdev);
4462 et131x_handle_send_interrupt(adapter);
4463 et131x_handle_recv_interrupt(adapter);
4465 /* Set the new MTU */
4466 netdev->mtu = new_mtu;
4468 /* Free Rx DMA memory */
4469 et131x_adapter_memory_free(adapter);
4471 /* Set the config parameter for Jumbo Packet support */
4472 adapter->registry_jumbo_packet = new_mtu + 14;
4473 et131x_soft_reset(adapter);
4475 /* Alloc and init Rx DMA memory */
4476 result = et131x_adapter_memory_alloc(adapter);
4478 dev_warn(&adapter->pdev->dev,
4479 "Change MTU failed; couldn't re-alloc DMA memory\n");
4483 et131x_init_send(adapter);
4485 et131x_hwaddr_init(adapter);
4486 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4488 /* Init the device with the new settings */
4489 et131x_adapter_setup(adapter);
4491 et131x_enable_txrx(netdev);
4496 /* et131x_set_mac_addr - handler to change the MAC address for the device */
4497 static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
4500 struct et131x_adapter *adapter = netdev_priv(netdev);
4501 struct sockaddr *address = new_mac;
4503 if (adapter == NULL)
4506 /* Make sure the requested MAC is valid */
4507 if (!is_valid_ether_addr(address->sa_data))
4508 return -EADDRNOTAVAIL;
4510 et131x_disable_txrx(netdev);
4511 et131x_handle_send_interrupt(adapter);
4512 et131x_handle_recv_interrupt(adapter);
4514 /* Set the new MAC */
4515 /* netdev->set_mac_address = &new_mac; */
4517 memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
4519 netdev_info(netdev, "Setting MAC address to %pM\n",
4522 /* Free Rx DMA memory */
4523 et131x_adapter_memory_free(adapter);
4525 et131x_soft_reset(adapter);
4527 /* Alloc and init Rx DMA memory */
4528 result = et131x_adapter_memory_alloc(adapter);
4530 dev_err(&adapter->pdev->dev,
4531 "Change MAC failed; couldn't re-alloc DMA memory\n");
4535 et131x_init_send(adapter);
4537 et131x_hwaddr_init(adapter);
4539 /* Init the device with the new settings */
4540 et131x_adapter_setup(adapter);
4542 et131x_enable_txrx(netdev);
4547 static const struct net_device_ops et131x_netdev_ops = {
4548 .ndo_open = et131x_open,
4549 .ndo_stop = et131x_close,
4550 .ndo_start_xmit = et131x_tx,
4551 .ndo_set_rx_mode = et131x_multicast,
4552 .ndo_tx_timeout = et131x_tx_timeout,
4553 .ndo_change_mtu = et131x_change_mtu,
4554 .ndo_set_mac_address = et131x_set_mac_addr,
4555 .ndo_validate_addr = eth_validate_addr,
4556 .ndo_get_stats = et131x_stats,
4557 .ndo_do_ioctl = et131x_ioctl,
4560 /* et131x_pci_setup - Perform device initialization
4561 * @pdev: a pointer to the device's pci_dev structure
4562 * @ent: this device's entry in the pci_device_id table
4564 * Registered in the pci_driver structure, this function is called when the
4565 * PCI subsystem finds a new PCI device which matches the information
4566 * contained in the pci_device_id table. This routine is the equivalent to
4567 * a device insertion routine.
4569 static int et131x_pci_setup(struct pci_dev *pdev,
4570 const struct pci_device_id *ent)
4572 struct net_device *netdev;
4573 struct et131x_adapter *adapter;
4577 rc = pci_enable_device(pdev);
4579 dev_err(&pdev->dev, "pci_enable_device() failed\n");
4583 /* Perform some basic PCI checks */
4584 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
4585 dev_err(&pdev->dev, "Can't find PCI device's base address\n");
4590 rc = pci_request_regions(pdev, DRIVER_NAME);
4592 dev_err(&pdev->dev, "Can't get PCI resources\n");
4596 pci_set_master(pdev);
4598 /* Check the DMA addressing support of this device */
4599 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
4600 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
4601 dev_err(&pdev->dev, "No usable DMA addressing method\n");
4603 goto err_release_res;
4606 /* Allocate netdev and private adapter structs */
4607 netdev = alloc_etherdev(sizeof(struct et131x_adapter));
4609 dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
4611 goto err_release_res;
4614 netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
4615 netdev->netdev_ops = &et131x_netdev_ops;
4617 SET_NETDEV_DEV(netdev, &pdev->dev);
4618 SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops);
4620 adapter = et131x_adapter_init(netdev, pdev);
4622 rc = et131x_pci_init(adapter, pdev);
4626 /* Map the bus-relative registers to system virtual memory */
4627 adapter->regs = pci_ioremap_bar(pdev, 0);
4628 if (!adapter->regs) {
4629 dev_err(&pdev->dev, "Cannot map device registers\n");
4634 /* If Phy COMA mode was enabled when we went down, disable it here. */
4635 writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
4637 /* Issue a global reset to the et1310 */
4638 et131x_soft_reset(adapter);
4640 /* Disable all interrupts (paranoid) */
4641 et131x_disable_interrupts(adapter);
4643 /* Allocate DMA memory */
4644 rc = et131x_adapter_memory_alloc(adapter);
4646 dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n");
4650 /* Init send data structures */
4651 et131x_init_send(adapter);
4653 /* Set up the task structure for the ISR's deferred handler */
4654 INIT_WORK(&adapter->task, et131x_isr_handler);
4656 /* Copy address into the net_device struct */
4657 memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
4659 /* Init variable for counting how long we do not have link status */
4660 adapter->boot_coma = 0;
4661 et1310_disable_phy_coma(adapter);
4665 /* Setup the mii_bus struct */
4666 adapter->mii_bus = mdiobus_alloc();
4667 if (!adapter->mii_bus) {
4668 dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
4672 adapter->mii_bus->name = "et131x_eth_mii";
4673 snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
4674 (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
4675 adapter->mii_bus->priv = netdev;
4676 adapter->mii_bus->read = et131x_mdio_read;
4677 adapter->mii_bus->write = et131x_mdio_write;
4678 adapter->mii_bus->reset = et131x_mdio_reset;
4679 adapter->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int),
4681 if (!adapter->mii_bus->irq)
4684 for (ii = 0; ii < PHY_MAX_ADDR; ii++)
4685 adapter->mii_bus->irq[ii] = PHY_POLL;
4687 rc = mdiobus_register(adapter->mii_bus);
4689 dev_err(&pdev->dev, "failed to register MII bus\n");
4690 goto err_mdio_free_irq;
4693 rc = et131x_mii_probe(netdev);
4695 dev_err(&pdev->dev, "failed to probe MII bus\n");
4696 goto err_mdio_unregister;
4699 /* Setup et1310 as per the documentation */
4700 et131x_adapter_setup(adapter);
4702 /* We can enable interrupts now
4704 * NOTE - Because registration of interrupt handler is done in the
4705 * device's open(), defer enabling device interrupts to that
4709 /* Register the net_device struct with the Linux network layer */
4710 rc = register_netdev(netdev);
4712 dev_err(&pdev->dev, "register_netdev() failed\n");
4713 goto err_phy_disconnect;
4716 /* Register the net_device struct with the PCI subsystem. Save a copy
4717 * of the PCI config space for this device now that the device has
4718 * been initialized, just in case it needs to be quickly restored.
4720 pci_set_drvdata(pdev, netdev);
4725 phy_disconnect(adapter->phydev);
4726 err_mdio_unregister:
4727 mdiobus_unregister(adapter->mii_bus);
4729 kfree(adapter->mii_bus->irq);
4731 mdiobus_free(adapter->mii_bus);
4733 et131x_adapter_memory_free(adapter);
4735 iounmap(adapter->regs);
4738 free_netdev(netdev);
4740 pci_release_regions(pdev);
4742 pci_disable_device(pdev);
4746 static const struct pci_device_id et131x_pci_table[] = {
4747 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
4748 { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
4751 MODULE_DEVICE_TABLE(pci, et131x_pci_table);
4753 static struct pci_driver et131x_driver = {
4754 .name = DRIVER_NAME,
4755 .id_table = et131x_pci_table,
4756 .probe = et131x_pci_setup,
4757 .remove = et131x_pci_remove,
4758 .driver.pm = ET131X_PM_OPS,
4761 module_pci_driver(et131x_driver);