2 * FB driver for the uPD161704 LCD Controller
4 * Copyright (C) 2014 Seong-Woo Kim
6 * Based on fb_ili9325.c by Noralf Tronnes
7 * Based on ili9325.c by Jeroen Domburg
8 * Init code from UTFT library by Henning Karlsen
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/gpio.h>
29 #include <linux/delay.h>
33 #define DRVNAME "fb_upd161704"
38 static int init_display(struct fbtft_par *par)
40 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
42 par->fbtftops.reset(par);
44 if (par->gpio.cs != -1)
45 gpio_set_value(par->gpio.cs, 0); /* Activate chip */
47 /* Initialization sequence from Lib_UTFT */
50 write_reg(par, 0x0003,0x0001); /* Soft reset */
52 /* oscillator start */
53 write_reg(par, 0x003A,0x0001); /*Oscillator 0: stop, 1: operation */
57 write_reg(par, 0x0024,0x007B); /* amplitude setting */
59 write_reg(par, 0x0025,0x003B); /* amplitude setting */
60 write_reg(par, 0x0026,0x0034); /* amplitude setting */
62 write_reg(par, 0x0027,0x0004); /* amplitude setting */
63 write_reg(par, 0x0052,0x0025); /* circuit setting 1 */
65 write_reg(par, 0x0053,0x0033); /* circuit setting 2 */
66 write_reg(par, 0x0061,0x001C); /* adjustment V10 positive polarity */
68 write_reg(par, 0x0062,0x002C); /* adjustment V9 negative polarity */
69 write_reg(par, 0x0063,0x0022); /* adjustment V34 positive polarity */
71 write_reg(par, 0x0064,0x0027); /* adjustment V31 negative polarity */
73 write_reg(par, 0x0065,0x0014); /* adjustment V61 negative polarity */
75 write_reg(par, 0x0066,0x0010); /* adjustment V61 negative polarity */
77 /* Basical clock for 1 line (BASECOUNT[7:0]) number specified */
78 write_reg(par, 0x002E,0x002D);
80 /* Power supply setting */
81 write_reg(par, 0x0019,0x0000); /* DC/DC output setting */
83 write_reg(par, 0x001A,0x1000); /* DC/DC frequency setting */
84 write_reg(par, 0x001B,0x0023); /* DC/DC rising setting */
85 write_reg(par, 0x001C,0x0C01); /* Regulator voltage setting */
86 write_reg(par, 0x001D,0x0000); /* Regulator current setting */
87 write_reg(par, 0x001E,0x0009); /* VCOM output setting */
88 write_reg(par, 0x001F,0x0035); /* VCOM amplitude setting */
89 write_reg(par, 0x0020,0x0015); /* VCOMM cencter setting */
90 write_reg(par, 0x0018,0x1E7B); /* DC/DC operation setting */
93 write_reg(par, 0x0008,0x0000); /* Minimum X address */
94 write_reg(par, 0x0009,0x00EF); /* Maximum X address */
95 write_reg(par, 0x000a,0x0000); /* Minimum Y address */
96 write_reg(par, 0x000b,0x013F); /* Maximum Y address */
98 /* LCD display area setting */
99 write_reg(par, 0x0029,0x0000); /* [LCDSIZE] X MIN. size set */
100 write_reg(par, 0x002A,0x0000); /* [LCDSIZE] Y MIN. size set */
101 write_reg(par, 0x002B,0x00EF); /* [LCDSIZE] X MAX. size set */
102 write_reg(par, 0x002C,0x013F); /* [LCDSIZE] Y MAX. size set */
104 /* Gate scan setting */
105 write_reg(par, 0x0032,0x0002);
107 /* n line inversion line number */
108 write_reg(par, 0x0033,0x0000);
110 /* Line inversion/frame inversion/interlace setting */
111 write_reg(par, 0x0037,0x0000);
113 /* Gate scan operation setting register */
114 write_reg(par, 0x003B,0x0001);
117 /*GS = 0: 260-k color (64 gray scale), GS = 1: 8 color (2 gray scale) */
118 write_reg(par, 0x0004,0x0000);
120 /* RAM control register */
121 write_reg(par, 0x0005,0x0000); /*Window access 00:Normal, 10:Window */
123 /* Display setting register 2 */
124 write_reg(par, 0x0001,0x0000);
126 /* display setting */
127 write_reg(par, 0x0000,0x0000); /* display on */
132 static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
134 fbtft_par_dbg(DEBUG_SET_ADDR_WIN, par,
135 "%s(xs=%d, ys=%d, xe=%d, ye=%d)\n", __func__, xs, ys, xe, ye);
136 switch (par->info->var.rotate) {
137 /* R20h = Horizontal GRAM Start Address */
138 /* R21h = Vertical GRAM Start Address */
140 write_reg(par, 0x0006, xs);
141 write_reg(par, 0x0007, ys);
144 write_reg(par, 0x0006, WIDTH - 1 - xs);
145 write_reg(par, 0x0007, HEIGHT - 1 - ys);
148 write_reg(par, 0x0006, WIDTH - 1 - ys);
149 write_reg(par, 0x0007, xs);
152 write_reg(par, 0x0006, ys);
153 write_reg(par, 0x0007, HEIGHT - 1 - xs);
157 write_reg(par, 0x0e); /* Write Data to GRAM */
160 static int set_var(struct fbtft_par *par)
162 fbtft_par_dbg(DEBUG_INIT_DISPLAY, par, "%s()\n", __func__);
164 switch (par->info->var.rotate) {
165 /* AM: GRAM update direction */
167 write_reg(par, 0x01, 0x0000);
168 write_reg(par, 0x05, 0x0000);
171 write_reg(par, 0x01, 0x00C0);
172 write_reg(par, 0x05, 0x0000);
175 write_reg(par, 0x01, 0x0080);
176 write_reg(par, 0x05, 0x0001);
179 write_reg(par, 0x01, 0x0040);
180 write_reg(par, 0x05, 0x0001);
187 static struct fbtft_display display = {
192 .init_display = init_display,
193 .set_addr_win = set_addr_win,
197 FBTFT_REGISTER_DRIVER(DRVNAME, "nec,upd161704", &display);
199 MODULE_ALIAS("spi:" DRVNAME);
200 MODULE_ALIAS("platform:" DRVNAME);
201 MODULE_ALIAS("spi:upd161704");
202 MODULE_ALIAS("platform:upd161704");
204 MODULE_DESCRIPTION("FB driver for the uPD161704 LCD Controller");
205 MODULE_AUTHOR("Seong-Woo Kim");
206 MODULE_LICENSE("GPL");