1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
4 * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 **************************************************************************/
25 #if defined(__linux__) && !defined(__KERNEL__)
27 #include <linux/types.h>
31 #include "psb_ttm_fence_user.h"
32 #include "psb_ttm_placement_user.h"
34 #define DRM_PSB_SAREA_MAJOR 0
35 #define DRM_PSB_SAREA_MINOR 2
36 #define PSB_FIXED_SHIFT 16
38 #define PSB_NUM_PIPE 3
41 * Public memory types.
44 #define DRM_PSB_MEM_MMU TTM_PL_PRIV1
45 #define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1
47 #define TTM_PL_CI TTM_PL_PRIV0
48 #define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0
50 #define TTM_PL_RAR TTM_PL_PRIV2
51 #define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2
53 typedef s32 psb_fixed;
54 typedef u32 psb_ufixed;
56 static inline s32 psb_int_to_fixed(int a)
58 return a * (1 << PSB_FIXED_SHIFT);
61 static inline u32 psb_unsigned_to_ufixed(unsigned int a)
63 return a << PSB_FIXED_SHIFT;
66 /*Status of the command sent to the gfx device.*/
73 struct drm_psb_scanout {
74 u32 buffer_id; /* DRM buffer object ID */
75 u32 rotation; /* Rotation as in RR_rotation definitions */
76 u32 stride; /* Buffer stride in bytes */
77 u32 depth; /* Buffer depth in bits (NOT) bpp */
78 u32 width; /* Buffer width in pixels */
79 u32 height; /* Buffer height in lines */
80 s32 transform[3][3]; /* Buffer composite transform */
81 /* (scaling, rot, reflect) */
84 #define DRM_PSB_SAREA_OWNERS 16
85 #define DRM_PSB_SAREA_OWNER_2D 0
86 #define DRM_PSB_SAREA_OWNER_3D 1
88 #define DRM_PSB_SAREA_SCANOUTS 3
90 struct drm_psb_sarea {
91 /* Track changes of this data structure */
96 /* Last context to touch part of hw */
97 u32 ctx_owners[DRM_PSB_SAREA_OWNERS];
99 /* Definition of front- and rotated buffers */
101 struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
111 /* Number of active scanouts */
112 u32 num_active_scanouts;
115 #define PSB_RELOC_MAGIC 0x67676767
116 #define PSB_RELOC_SHIFT_MASK 0x0000FFFF
117 #define PSB_RELOC_SHIFT_SHIFT 0
118 #define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
119 #define PSB_RELOC_ALSHIFT_SHIFT 16
121 #define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
125 struct drm_psb_reloc {
127 u32 where; /* offset in destination buffer */
128 u32 buffer; /* Buffer reloc applies to */
129 u32 mask; /* Destination format: */
130 u32 shift; /* Destination format: */
131 u32 pre_add; /* Destination format: */
132 u32 background; /* Destination add */
133 u32 dst_buffer; /* Destination buffer. Index into buffer_list */
134 u32 arg0; /* Reloc-op dependant */
139 #define PSB_GPU_ACCESS_READ (1ULL << 32)
140 #define PSB_GPU_ACCESS_WRITE (1ULL << 33)
141 #define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
143 #define PSB_BO_FLAG_COMMAND (1ULL << 52)
145 #define PSB_ENGINE_2D 0
146 #define PSB_ENGINE_VIDEO 1
147 #define LNC_ENGINE_ENCODE 5
150 * For this fence class we have a couple of
154 #define _PSB_FENCE_EXE_SHIFT 0
155 #define _PSB_FENCE_FEEDBACK_SHIFT 4
157 #define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT)
158 #define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
160 #define PSB_NUM_ENGINES 6
163 #define PSB_FEEDBACK_OP_VISTEST (1 << 0)
165 struct drm_psb_extension_rep {
167 u32 driver_ioctl_offset;
174 #define DRM_PSB_EXT_NAME_LEN 128
176 union drm_psb_extension_arg {
177 char extension[DRM_PSB_EXT_NAME_LEN];
178 struct drm_psb_extension_rep rep;
181 struct psb_validate_req {
185 u64 presumed_gpu_offset;
192 struct psb_validate_rep {
198 #define PSB_USE_PRESUMED (1 << 0)
200 struct psb_validate_arg {
204 struct psb_validate_req req;
205 struct psb_validate_rep rep;
210 #define DRM_PSB_FENCE_NO_USER (1 << 0)
212 struct psb_ttm_fence_rep {
221 * Feedback components:
224 struct drm_psb_sizes_arg {
233 struct drm_psb_dpst_lut_arg {
238 #define PSB_DC_CRTC_SAVE 0x01
239 #define PSB_DC_CRTC_RESTORE 0x02
240 #define PSB_DC_OUTPUT_SAVE 0x04
241 #define PSB_DC_OUTPUT_RESTORE 0x08
242 #define PSB_DC_CRTC_MASK 0x03
243 #define PSB_DC_OUTPUT_MASK 0x0C
245 struct drm_psb_dc_state_arg {
250 struct drm_psb_mode_operation_arg {
253 struct drm_mode_modeinfo mode;
257 struct drm_psb_stolen_memory_arg {
262 /*Display Register Bits*/
263 #define REGRWBITS_PFIT_CONTROLS (1 << 0)
264 #define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
265 #define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
266 #define REGRWBITS_PIPEASRC (1 << 3)
267 #define REGRWBITS_PIPEBSRC (1 << 4)
268 #define REGRWBITS_VTOTAL_A (1 << 5)
269 #define REGRWBITS_VTOTAL_B (1 << 6)
270 #define REGRWBITS_DSPACNTR (1 << 8)
271 #define REGRWBITS_DSPBCNTR (1 << 9)
272 #define REGRWBITS_DSPCCNTR (1 << 10)
274 /*Overlay Register Bits*/
275 #define OV_REGRWBITS_OVADD (1 << 0)
276 #define OV_REGRWBITS_OGAM_ALL (1 << 1)
278 #define OVC_REGRWBITS_OVADD (1 << 2)
279 #define OVC_REGRWBITS_OGAM_ALL (1 << 3)
281 struct drm_psb_register_rw_arg {
284 u32 display_read_mask;
285 u32 display_write_mask;
289 u32 pfit_autoscale_ratios;
290 u32 pfit_programmed_scale_ratios;
297 u32 overlay_read_mask;
298 u32 overlay_write_mask;
310 u32 IEP_BSSCC_CONTROL;
314 u32 sprite_enable_mask;
315 u32 sprite_disable_mask;
324 u32 dspc_linear_offset;
329 u32 subpicture_enable_mask;
330 u32 subpicture_disable_mask;
333 struct psb_gtt_mapping_arg {
334 void *hKernelMemInfo;
338 struct drm_psb_getpageaddrs_arg {
340 unsigned long *page_addrs;
341 unsigned long gtt_offset;
344 /* Controlling the kernel modesetting buffers */
346 #define DRM_PSB_KMS_OFF 0x00
347 #define DRM_PSB_KMS_ON 0x01
348 #define DRM_PSB_VT_LEAVE 0x02
349 #define DRM_PSB_VT_ENTER 0x03
350 #define DRM_PSB_EXTENSION 0x06
351 #define DRM_PSB_SIZES 0x07
352 #define DRM_PSB_FUSE_REG 0x08
353 #define DRM_PSB_VBT 0x09
354 #define DRM_PSB_DC_STATE 0x0A
355 #define DRM_PSB_ADB 0x0B
356 #define DRM_PSB_MODE_OPERATION 0x0C
357 #define DRM_PSB_STOLEN_MEMORY 0x0D
358 #define DRM_PSB_REGISTER_RW 0x0E
359 #define DRM_PSB_GTT_MAP 0x0F
360 #define DRM_PSB_GTT_UNMAP 0x10
361 #define DRM_PSB_GETPAGEADDRS 0x11
363 * NOTE: Add new commands here, but increment
364 * the values below and increment their
365 * corresponding defines where they're
368 #define DRM_PVR_RESERVED1 0x12
369 #define DRM_PVR_RESERVED2 0x13
370 #define DRM_PVR_RESERVED3 0x14
371 #define DRM_PVR_RESERVED4 0x15
372 #define DRM_PVR_RESERVED5 0x16
374 #define DRM_PSB_HIST_ENABLE 0x17
375 #define DRM_PSB_HIST_STATUS 0x18
376 #define DRM_PSB_UPDATE_GUARD 0x19
377 #define DRM_PSB_INIT_COMM 0x1A
378 #define DRM_PSB_DPST 0x1B
379 #define DRM_PSB_GAMMA 0x1C
380 #define DRM_PSB_DPST_BL 0x1D
382 #define DRM_PVR_RESERVED6 0x1E
384 #define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
386 #define PSB_MODE_OPERATION_MODE_VALID 0x01
387 #define PSB_MODE_OPERATION_SET_DC_BASE 0x02
389 struct drm_psb_get_pipe_from_crtc_id_arg {
390 /** ID of CRTC being requested **/
393 /** pipe of requested CRTC **/