4 * Copyright 2016 Google Inc.
5 * Copyright 2016 Linaro Ltd.
7 * Released under the GPLv2 only.
9 * This code reads directly from an ARMv7 memory-mapped timer that lives in
10 * MMIO space. Since this counter lives inside of MMIO space its shared between
11 * cores and that means we don't have to worry about issues like TSC on x86
12 * where each time-stamp-counter (TSC) is local to a particular core.
14 * Register-level access code is based on
15 * drivers/clocksource/arm_arch_timer.c
17 #include <linux/cpufreq.h>
18 #include <linux/of_platform.h>
21 #include "arche_platform.h"
23 #define DEFAULT_FRAMETIME_CLOCK_HZ 19200000
25 static u32 gb_timesync_clock_frequency;
26 int (*arche_platform_change_state_cb)(enum arche_platform_state state,
27 struct gb_timesync_svc *pdata);
28 EXPORT_SYMBOL_GPL(arche_platform_change_state_cb);
30 u64 gb_timesync_platform_get_counter(void)
32 return (u64)get_cycles();
35 u32 gb_timesync_platform_get_clock_rate(void)
37 if (unlikely(!gb_timesync_clock_frequency)) {
38 gb_timesync_clock_frequency = cpufreq_get(0);
39 if (!gb_timesync_clock_frequency)
40 gb_timesync_clock_frequency = DEFAULT_FRAMETIME_CLOCK_HZ;
43 return gb_timesync_clock_frequency;
46 int gb_timesync_platform_lock_bus(struct gb_timesync_svc *pdata)
48 return arche_platform_change_state_cb(ARCHE_PLATFORM_STATE_TIME_SYNC,
52 void gb_timesync_platform_unlock_bus(void)
54 arche_platform_change_state_cb(ARCHE_PLATFORM_STATE_ACTIVE, NULL);
57 static const struct of_device_id arch_timer_of_match[] = {
58 { .compatible = "google,greybus-frame-time-counter", },
62 int __init gb_timesync_platform_init(void)
64 struct device_node *np;
66 np = of_find_matching_node(NULL, arch_timer_of_match);
68 /* Tolerate not finding to allow BBB etc to continue */
69 pr_warn("Unable to find a compatible ARMv7 timer\n");
73 if (of_property_read_u32(np, "clock-frequency",
74 &gb_timesync_clock_frequency)) {
75 pr_err("Unable to find timer clock-frequency\n");
82 void gb_timesync_platform_exit(void) {}