drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24
  25 #include "../iio.h"
  26 #include "../sysfs.h"
  27 #include "../ring_generic.h"
  28 #include "../ring_sw.h"
  29
  30 #include "accel.h"
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38 /* direct copy of the irq_default_primary_handler */
  39 #ifndef CONFIG_IIO_RING_BUFFER
  40 static irqreturn_t lis3l02dq_noring(int irq, void *private)
  41 {
  42         return IRQ_WAKE_THREAD;
  43 }
  44 #endif
  45
  46 /**
  47  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  48  * @indio_dev: iio_dev for this actual device
  49  * @reg_address: the address of the register to be read
  50  * @val: pass back the resulting value
  51  **/
  52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  53                              u8 reg_address, u8 *val)
  54 {
  55         struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
  56         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  57         struct spi_message msg;
  58         int ret;
  59         struct spi_transfer xfer = {
  60                 .tx_buf = st->tx,
  61                 .rx_buf = st->rx,
  62                 .bits_per_word = 8,
  63                 .len = 2,
  64         };
  65
  66         mutex_lock(&st->buf_lock);
  67         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  68         st->tx[1] = 0;
  69
  70         spi_message_init(&msg);
  71         spi_message_add_tail(&xfer, &msg);
  72         ret = spi_sync(st->us, &msg);
  73         *val = st->rx[1];
  74         mutex_unlock(&st->buf_lock);
  75
  76         return ret;
  77 }
  78
  79 /**
  80  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  81  * @indio_dev: iio_dev for this device
  82  * @reg_address: the address of the register to be written
  83  * @val: the value to write
  84  **/
  85 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  86                               u8 reg_address,
  87                               u8 *val)
  88 {
  89         int ret;
  90         struct iio_sw_ring_helper_state *h
  91                 = iio_dev_get_devdata(indio_dev);
  92         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  93
  94         mutex_lock(&st->buf_lock);
  95         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  96         st->tx[1] = *val;
  97         ret = spi_write(st->us, st->tx, 2);
  98         mutex_unlock(&st->buf_lock);
  99
 100         return ret;
 101 }
 102
 103 /**
 104  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
 105  * @indio_dev: iio_dev for this device
 106  * @lower_reg_address: the address of the lower of the two registers.
 107  *               Second register is assumed to have address one greater.
 108  * @value: value to be written
 109  **/
 110 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 111                                        u8 lower_reg_address,
 112                                        s16 value)
 113 {
 114         int ret;
 115         struct spi_message msg;
 116         struct iio_sw_ring_helper_state *h
 117                 = iio_dev_get_devdata(indio_dev);
 118         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 119         struct spi_transfer xfers[] = { {
 120                         .tx_buf = st->tx,
 121                         .bits_per_word = 8,
 122                         .len = 2,
 123                         .cs_change = 1,
 124                 }, {
 125                         .tx_buf = st->tx + 2,
 126                         .bits_per_word = 8,
 127                         .len = 2,
 128                 },
 129         };
 130
 131         mutex_lock(&st->buf_lock);
 132         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 133         st->tx[1] = value & 0xFF;
 134         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 135         st->tx[3] = (value >> 8) & 0xFF;
 136
 137         spi_message_init(&msg);
 138         spi_message_add_tail(&xfers[0], &msg);
 139         spi_message_add_tail(&xfers[1], &msg);
 140         ret = spi_sync(st->us, &msg);
 141         mutex_unlock(&st->buf_lock);
 142
 143         return ret;
 144 }
 145
 146 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 147                                   u8 lower_reg_address,
 148                                   int *val)
 149 {
 150         struct iio_sw_ring_helper_state *h
 151                 = iio_dev_get_devdata(indio_dev);
 152         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 153
 154         struct spi_message msg;
 155         int ret;
 156         s16 tempval;
 157         struct spi_transfer xfers[] = { {
 158                         .tx_buf = st->tx,
 159                         .rx_buf = st->rx,
 160                         .bits_per_word = 8,
 161                         .len = 2,
 162                         .cs_change = 1,
 163                 }, {
 164                         .tx_buf = st->tx + 2,
 165                         .rx_buf = st->rx + 2,
 166                         .bits_per_word = 8,
 167                         .len = 2,
 168                 },
 169         };
 170
 171         mutex_lock(&st->buf_lock);
 172         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 173         st->tx[1] = 0;
 174         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 175         st->tx[3] = 0;
 176
 177         spi_message_init(&msg);
 178         spi_message_add_tail(&xfers[0], &msg);
 179         spi_message_add_tail(&xfers[1], &msg);
 180         ret = spi_sync(st->us, &msg);
 181         if (ret) {
 182                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 183                 goto error_ret;
 184         }
 185         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 186
 187         *val = tempval;
 188 error_ret:
 189         mutex_unlock(&st->buf_lock);
 190         return ret;
 191 }
 192
 193 enum lis3l02dq_rm_ind {
 194         LIS3L02DQ_ACCEL,
 195         LIS3L02DQ_GAIN,
 196         LIS3L02DQ_BIAS,
 197 };
 198
 199 static u8 lis3l02dq_axis_map[3][3] = {
 200         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 201                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 202                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 203         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 204                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 205                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 206         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 207                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 208                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 209 };
 210
 211 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 212                                  int e,
 213                                  int *val)
 214 {
 215         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 216 }
 217
 218 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 219                                   int event_code,
 220                                   int val)
 221 {
 222         u16 value = val;
 223         return lis3l02dq_spi_write_reg_s16(indio_dev,
 224                                            LIS3L02DQ_REG_THS_L_ADDR,
 225                                            value);
 226 }
 227
 228 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 229                                struct iio_chan_spec const *chan,
 230                                int val,
 231                                int val2,
 232                                long mask)
 233 {
 234         int ret = -EINVAL, reg;
 235         u8 uval;
 236         s8 sval;
 237         switch (mask) {
 238         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 239                 if (val > 255 || val < -256)
 240                         return -EINVAL;
 241                 sval = val;
 242                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 243                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, (u8 *)&sval);
 244                 break;
 245         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 246                 if (val & ~0xFF)
 247                         return -EINVAL;
 248                 uval = val;
 249                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 250                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, &uval);
 251                 break;
 252         }
 253         return ret;
 254 }
 255
 256 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 257                               struct iio_chan_spec const *chan,
 258                               int *val,
 259                               int *val2,
 260                               long mask)
 261 {
 262         u8 utemp;
 263         s8 stemp;
 264         ssize_t ret = 0;
 265         u8 reg;
 266
 267         switch (mask) {
 268         case 0:
 269                 /* Take the iio_dev status lock */
 270                 mutex_lock(&indio_dev->mlock);
 271                 if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 272                         ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
 273                                                              chan->scan_index,
 274                                                              val);
 275                 else {
 276                         reg = lis3l02dq_axis_map
 277                                 [LIS3L02DQ_ACCEL][chan->address];
 278                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 279                 }
 280                 mutex_unlock(&indio_dev->mlock);
 281                 return IIO_VAL_INT;
 282         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 283                 *val = 0;
 284                 *val2 = 9580;
 285                 return IIO_VAL_INT_PLUS_MICRO;
 286         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 287                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 288                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 289                 if (ret)
 290                         goto error_ret;
 291                 /* to match with what previous code does */
 292                 *val = utemp;
 293                 return IIO_VAL_INT;
 294
 295         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 296                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 297                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 298                 /* to match with what previous code does */
 299                 *val = stemp;
 300                 return IIO_VAL_INT;
 301         }
 302 error_ret:
 303         return ret;
 304 }
 305
 306 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 307                                         struct device_attribute *attr,
 308                                         char *buf)
 309 {
 310         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 311         int ret, len = 0;
 312         s8 t;
 313         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 314                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 315                                        (u8 *)&t);
 316         if (ret)
 317                 return ret;
 318         t &= LIS3L02DQ_DEC_MASK;
 319         switch (t) {
 320         case LIS3L02DQ_REG_CTRL_1_DF_128:
 321                 len = sprintf(buf, "280\n");
 322                 break;
 323         case LIS3L02DQ_REG_CTRL_1_DF_64:
 324                 len = sprintf(buf, "560\n");
 325                 break;
 326         case LIS3L02DQ_REG_CTRL_1_DF_32:
 327                 len = sprintf(buf, "1120\n");
 328                 break;
 329         case LIS3L02DQ_REG_CTRL_1_DF_8:
 330                 len = sprintf(buf, "4480\n");
 331                 break;
 332         }
 333         return len;
 334 }
 335
 336 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 337                                          struct device_attribute *attr,
 338                                          const char *buf,
 339                                          size_t len)
 340 {
 341         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 342         long val;
 343         int ret;
 344         u8 t;
 345
 346         ret = strict_strtol(buf, 10, &val);
 347         if (ret)
 348                 return ret;
 349
 350         mutex_lock(&indio_dev->mlock);
 351         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 352                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 353                                        &t);
 354         if (ret)
 355                 goto error_ret_mutex;
 356         /* Wipe the bits clean */
 357         t &= ~LIS3L02DQ_DEC_MASK;
 358         switch (val) {
 359         case 280:
 360                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 361                 break;
 362         case 560:
 363                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 364                 break;
 365         case 1120:
 366                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 367                 break;
 368         case 4480:
 369                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 370                 break;
 371         default:
 372                 ret = -EINVAL;
 373                 goto error_ret_mutex;
 374         }
 375
 376         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 377                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 378                                         &t);
 379
 380 error_ret_mutex:
 381         mutex_unlock(&indio_dev->mlock);
 382
 383         return ret ? ret : len;
 384 }
 385
 386 static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
 387 {
 388         int ret;
 389         u8 val, valtest;
 390
 391         st->us->mode = SPI_MODE_3;
 392
 393         spi_setup(st->us);
 394
 395         val = LIS3L02DQ_DEFAULT_CTRL1;
 396         /* Write suitable defaults to ctrl1 */
 397         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 398                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 399                                         &val);
 400         if (ret) {
 401                 dev_err(&st->us->dev, "problem with setup control register 1");
 402                 goto err_ret;
 403         }
 404         /* Repeat as sometimes doesn't work first time?*/
 405         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 406                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 407                                         &val);
 408         if (ret) {
 409                 dev_err(&st->us->dev, "problem with setup control register 1");
 410                 goto err_ret;
 411         }
 412
 413         /* Read back to check this has worked acts as loose test of correct
 414          * chip */
 415         ret = lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 416                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 417                                        &valtest);
 418         if (ret || (valtest != val)) {
 419                 dev_err(&st->help.indio_dev->dev,
 420                         "device not playing ball %d %d\n", valtest, val);
 421                 ret = -EINVAL;
 422                 goto err_ret;
 423         }
 424
 425         val = LIS3L02DQ_DEFAULT_CTRL2;
 426         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 427                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 428                                         &val);
 429         if (ret) {
 430                 dev_err(&st->us->dev, "problem with setup control register 2");
 431                 goto err_ret;
 432         }
 433
 434         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 435         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 436                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 437                                         &val);
 438         if (ret)
 439                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 440 err_ret:
 441
 442         return ret;
 443 }
 444
 445 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 446                               lis3l02dq_read_frequency,
 447                               lis3l02dq_write_frequency);
 448
 449 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 450
 451 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 452 {
 453         struct iio_dev *indio_dev = private;
 454         struct iio_sw_ring_helper_state *h
 455                 = iio_dev_get_devdata(indio_dev);
 456         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 457         u8 t;
 458
 459         s64 timestamp = iio_get_time_ns();
 460
 461         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 462                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 463                                  &t);
 464
 465         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 466                 iio_push_event(st->help.indio_dev, 0,
 467                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 468                                                   0,
 469                                                   IIO_EV_MOD_Z,
 470                                                   IIO_EV_TYPE_THRESH,
 471                                                   IIO_EV_DIR_RISING),
 472                                timestamp);
 473
 474         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 475                 iio_push_event(st->help.indio_dev, 0,
 476                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 477                                                   0,
 478                                                   IIO_EV_MOD_Z,
 479                                                   IIO_EV_TYPE_THRESH,
 480                                                   IIO_EV_DIR_FALLING),
 481                                timestamp);
 482
 483         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 484                 iio_push_event(st->help.indio_dev, 0,
 485                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 486                                                   0,
 487                                                   IIO_EV_MOD_Y,
 488                                                   IIO_EV_TYPE_THRESH,
 489                                                   IIO_EV_DIR_RISING),
 490                                timestamp);
 491
 492         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 493                 iio_push_event(st->help.indio_dev, 0,
 494                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 495                                                   0,
 496                                                   IIO_EV_MOD_Y,
 497                                                   IIO_EV_TYPE_THRESH,
 498                                                   IIO_EV_DIR_FALLING),
 499                                timestamp);
 500
 501         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 502                 iio_push_event(st->help.indio_dev, 0,
 503                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 504                                                   0,
 505                                                   IIO_EV_MOD_X,
 506                                                   IIO_EV_TYPE_THRESH,
 507                                                   IIO_EV_DIR_RISING),
 508                                timestamp);
 509
 510         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 511                 iio_push_event(st->help.indio_dev, 0,
 512                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 513                                                   0,
 514                                                   IIO_EV_MOD_X,
 515                                                   IIO_EV_TYPE_THRESH,
 516                                                   IIO_EV_DIR_FALLING),
 517                                timestamp);
 518
 519         /* Ack and allow for new interrupts */
 520         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 521                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 522                                  &t);
 523
 524         return IRQ_HANDLED;
 525 }
 526
 527 #define LIS3L02DQ_INFO_MASK                             \
 528         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 529          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 530          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 531
 532 #define LIS3L02DQ_EVENT_MASK                                    \
 533         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 534          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 535
 536 static struct iio_chan_spec lis3l02dq_channels[] = {
 537         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 538                  0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 539         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 540                  1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 541         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 542                  2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 543         IIO_CHAN_SOFT_TIMESTAMP(3)
 544 };
 545
 546
 547 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 548                                            int event_code)
 549 {
 550
 551         u8 val;
 552         int ret;
 553         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 554                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 555                           IIO_EV_DIR_RISING)));
 556         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 557                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 558                                        &val);
 559         if (ret < 0)
 560                 return ret;
 561
 562         return !!(val & mask);
 563 }
 564
 565 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 566 {
 567         int ret;
 568         u8 control, val;
 569
 570         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 571                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 572                                        &control);
 573
 574         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 575         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 576                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 577                                         &control);
 578         if (ret)
 579                 goto error_ret;
 580         /* Also for consistency clear the mask */
 581         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 582                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 583                                        &val);
 584         if (ret)
 585                 goto error_ret;
 586         val &= ~0x3f;
 587
 588         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 589                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 590                                         &val);
 591         if (ret)
 592                 goto error_ret;
 593
 594         ret = control;
 595 error_ret:
 596         return ret;
 597 }
 598
 599 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 600                                         int event_code,
 601                                         int state)
 602 {
 603         int ret = 0;
 604         u8 val, control;
 605         u8 currentlyset;
 606         bool changed = false;
 607         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 608                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 609                           IIO_EV_DIR_RISING)));
 610
 611         mutex_lock(&indio_dev->mlock);
 612         /* read current control */
 613         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 614                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 615                                        &control);
 616         if (ret)
 617                 goto error_ret;
 618         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 619                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 620                                        &val);
 621         if (ret < 0)
 622                 goto error_ret;
 623         currentlyset = val & mask;
 624
 625         if (!currentlyset && state) {
 626                 changed = true;
 627                 val |= mask;
 628         } else if (currentlyset && !state) {
 629                 changed = true;
 630                 val &= ~mask;
 631         }
 632
 633         if (changed) {
 634                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 635                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 636                                                 &val);
 637                 if (ret)
 638                         goto error_ret;
 639                 control = val & 0x3f ?
 640                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 641                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 642                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 643                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 644                                                &control);
 645                 if (ret)
 646                         goto error_ret;
 647         }
 648
 649 error_ret:
 650         mutex_unlock(&indio_dev->mlock);
 651         return ret;
 652 }
 653
 654 static struct attribute *lis3l02dq_attributes[] = {
 655         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 656         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 657         NULL
 658 };
 659
 660 static const struct attribute_group lis3l02dq_attribute_group = {
 661         .attrs = lis3l02dq_attributes,
 662 };
 663
 664 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 665 {
 666         int ret, regdone = 0;
 667         struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
 668         if (!st) {
 669                 ret =  -ENOMEM;
 670                 goto error_ret;
 671         }
 672
 673         /* this is only used tor removal purposes */
 674         spi_set_drvdata(spi, st);
 675
 676         /* Allocate the comms buffers */
 677         st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
 678         if (st->rx == NULL) {
 679                 ret = -ENOMEM;
 680                 goto error_free_st;
 681         }
 682         st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
 683         if (st->tx == NULL) {
 684                 ret = -ENOMEM;
 685                 goto error_free_rx;
 686         }
 687         st->us = spi;
 688         mutex_init(&st->buf_lock);
 689         /* setup the industrialio driver allocated elements */
 690         st->help.indio_dev = iio_allocate_device(0);
 691         if (st->help.indio_dev == NULL) {
 692                 ret = -ENOMEM;
 693                 goto error_free_tx;
 694         }
 695
 696         st->help.indio_dev->name = spi->dev.driver->name;
 697         st->help.indio_dev->dev.parent = &spi->dev;
 698         st->help.indio_dev->num_interrupt_lines = 1;
 699         st->help.indio_dev->channels = lis3l02dq_channels;
 700         st->help.indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 701         st->help.indio_dev->read_raw = &lis3l02dq_read_raw;
 702         st->help.indio_dev->write_raw = &lis3l02dq_write_raw;
 703         st->help.indio_dev->read_event_value = &lis3l02dq_read_thresh;
 704         st->help.indio_dev->write_event_value = &lis3l02dq_write_thresh;
 705         st->help.indio_dev->write_event_config = &lis3l02dq_write_event_config;
 706         st->help.indio_dev->read_event_config = &lis3l02dq_read_event_config;
 707         st->help.indio_dev->attrs = &lis3l02dq_attribute_group;
 708         st->help.indio_dev->dev_data = (void *)(&st->help);
 709         st->help.indio_dev->driver_module = THIS_MODULE;
 710         st->help.indio_dev->modes = INDIO_DIRECT_MODE;
 711
 712         ret = lis3l02dq_configure_ring(st->help.indio_dev);
 713         if (ret)
 714                 goto error_free_dev;
 715
 716         ret = iio_device_register(st->help.indio_dev);
 717         if (ret)
 718                 goto error_unreg_ring_funcs;
 719         regdone = 1;
 720
 721         ret = iio_ring_buffer_register_ex(st->help.indio_dev->ring, 0,
 722                                           lis3l02dq_channels,
 723                                           ARRAY_SIZE(lis3l02dq_channels));
 724         if (ret) {
 725                 printk(KERN_ERR "failed to initialize the ring\n");
 726                 goto error_unreg_ring_funcs;
 727         }
 728
 729         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 730                 ret = request_threaded_irq(st->us->irq,
 731                                            &lis3l02dq_th,
 732                                            &lis3l02dq_event_handler,
 733                                            IRQF_TRIGGER_RISING,
 734                                            "lis3l02dq",
 735                                            st->help.indio_dev);
 736                 if (ret)
 737                         goto error_uninitialize_ring;
 738
 739                 ret = lis3l02dq_probe_trigger(st->help.indio_dev);
 740                 if (ret)
 741                         goto error_free_interrupt;
 742         }
 743
 744         /* Get the device into a sane initial state */
 745         ret = lis3l02dq_initial_setup(st);
 746         if (ret)
 747                 goto error_remove_trigger;
 748         return 0;
 749
 750 error_remove_trigger:
 751         if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
 752                 lis3l02dq_remove_trigger(st->help.indio_dev);
 753 error_free_interrupt:
 754         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 755                 free_irq(st->us->irq, st->help.indio_dev);
 756 error_uninitialize_ring:
 757         iio_ring_buffer_unregister(st->help.indio_dev->ring);
 758 error_unreg_ring_funcs:
 759         lis3l02dq_unconfigure_ring(st->help.indio_dev);
 760 error_free_dev:
 761         if (regdone)
 762                 iio_device_unregister(st->help.indio_dev);
 763         else
 764                 iio_free_device(st->help.indio_dev);
 765 error_free_tx:
 766         kfree(st->tx);
 767 error_free_rx:
 768         kfree(st->rx);
 769 error_free_st:
 770         kfree(st);
 771 error_ret:
 772         return ret;
 773 }
 774
 775 /* Power down the device */
 776 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 777 {
 778         int ret;
 779         struct iio_sw_ring_helper_state *h
 780                 = iio_dev_get_devdata(indio_dev);
 781         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 782         u8 val = 0;
 783
 784         mutex_lock(&indio_dev->mlock);
 785         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 786                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 787                                         &val);
 788         if (ret) {
 789                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 790                 goto err_ret;
 791         }
 792
 793         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 794                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 795                                         &val);
 796         if (ret)
 797                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 798 err_ret:
 799         mutex_unlock(&indio_dev->mlock);
 800         return ret;
 801 }
 802
 803 /* fixme, confirm ordering in this function */
 804 static int lis3l02dq_remove(struct spi_device *spi)
 805 {
 806         int ret;
 807         struct lis3l02dq_state *st = spi_get_drvdata(spi);
 808         struct iio_dev *indio_dev = st->help.indio_dev;
 809         ret = lis3l02dq_disable_all_events(indio_dev);
 810         if (ret)
 811                 goto err_ret;
 812
 813         ret = lis3l02dq_stop_device(indio_dev);
 814         if (ret)
 815                 goto err_ret;
 816
 817         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
 818                 free_irq(st->us->irq, indio_dev);
 819
 820         lis3l02dq_remove_trigger(indio_dev);
 821         iio_ring_buffer_unregister(indio_dev->ring);
 822         lis3l02dq_unconfigure_ring(indio_dev);
 823         iio_device_unregister(indio_dev);
 824         kfree(st->tx);
 825         kfree(st->rx);
 826         kfree(st);
 827
 828         return 0;
 829
 830 err_ret:
 831         return ret;
 832 }
 833
 834 static struct spi_driver lis3l02dq_driver = {
 835         .driver = {
 836                 .name = "lis3l02dq",
 837                 .owner = THIS_MODULE,
 838         },
 839         .probe = lis3l02dq_probe,
 840         .remove = __devexit_p(lis3l02dq_remove),
 841 };
 842
 843 static __init int lis3l02dq_init(void)
 844 {
 845         return spi_register_driver(&lis3l02dq_driver);
 846 }
 847 module_init(lis3l02dq_init);
 848
 849 static __exit void lis3l02dq_exit(void)
 850 {
 851         spi_unregister_driver(&lis3l02dq_driver);
 852 }
 853 module_exit(lis3l02dq_exit);
 854
 855 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 856 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 857 MODULE_LICENSE("GPL v2");