drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@cam.ac.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/mutex.h>
  19 #include <linux/device.h>
  20 #include <linux/kernel.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/slab.h>
  23 #include <linux/sysfs.h>
  24
  25 #include "../iio.h"
  26 #include "../sysfs.h"
  27 #include "../ring_generic.h"
  28 #include "../ring_sw.h"
  29
  30 #include "accel.h"
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38
  39 /**
  40  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  41  * @indio_dev: iio_dev for this actual device
  42  * @reg_address: the address of the register to be read
  43  * @val: pass back the resulting value
  44  **/
  45 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  46                              u8 reg_address, u8 *val)
  47 {
  48         struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
  49         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  50         struct spi_message msg;
  51         int ret;
  52         struct spi_transfer xfer = {
  53                 .tx_buf = st->tx,
  54                 .rx_buf = st->rx,
  55                 .bits_per_word = 8,
  56                 .len = 2,
  57         };
  58
  59         mutex_lock(&st->buf_lock);
  60         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  61         st->tx[1] = 0;
  62
  63         spi_message_init(&msg);
  64         spi_message_add_tail(&xfer, &msg);
  65         ret = spi_sync(st->us, &msg);
  66         *val = st->rx[1];
  67         mutex_unlock(&st->buf_lock);
  68
  69         return ret;
  70 }
  71
  72 /**
  73  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  74  * @indio_dev: iio_dev for this device
  75  * @reg_address: the address of the register to be written
  76  * @val: the value to write
  77  **/
  78 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  79                               u8 reg_address,
  80                               u8 *val)
  81 {
  82         int ret;
  83         struct iio_sw_ring_helper_state *h
  84                 = iio_dev_get_devdata(indio_dev);
  85         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
  86
  87         mutex_lock(&st->buf_lock);
  88         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  89         st->tx[1] = *val;
  90         ret = spi_write(st->us, st->tx, 2);
  91         mutex_unlock(&st->buf_lock);
  92
  93         return ret;
  94 }
  95
  96 /**
  97  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
  98  * @indio_dev: iio_dev for this device
  99  * @lower_reg_address: the address of the lower of the two registers.
 100  *               Second register is assumed to have address one greater.
 101  * @value: value to be written
 102  **/
 103 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 104                                        u8 lower_reg_address,
 105                                        s16 value)
 106 {
 107         int ret;
 108         struct spi_message msg;
 109         struct iio_sw_ring_helper_state *h
 110                 = iio_dev_get_devdata(indio_dev);
 111         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 112         struct spi_transfer xfers[] = { {
 113                         .tx_buf = st->tx,
 114                         .bits_per_word = 8,
 115                         .len = 2,
 116                         .cs_change = 1,
 117                 }, {
 118                         .tx_buf = st->tx + 2,
 119                         .bits_per_word = 8,
 120                         .len = 2,
 121                 },
 122         };
 123
 124         mutex_lock(&st->buf_lock);
 125         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 126         st->tx[1] = value & 0xFF;
 127         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 128         st->tx[3] = (value >> 8) & 0xFF;
 129
 130         spi_message_init(&msg);
 131         spi_message_add_tail(&xfers[0], &msg);
 132         spi_message_add_tail(&xfers[1], &msg);
 133         ret = spi_sync(st->us, &msg);
 134         mutex_unlock(&st->buf_lock);
 135
 136         return ret;
 137 }
 138
 139 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 140                                   u8 lower_reg_address,
 141                                   int *val)
 142 {
 143         struct iio_sw_ring_helper_state *h
 144                 = iio_dev_get_devdata(indio_dev);
 145         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 146
 147         struct spi_message msg;
 148         int ret;
 149         s16 tempval;
 150         struct spi_transfer xfers[] = { {
 151                         .tx_buf = st->tx,
 152                         .rx_buf = st->rx,
 153                         .bits_per_word = 8,
 154                         .len = 2,
 155                         .cs_change = 1,
 156                 }, {
 157                         .tx_buf = st->tx + 2,
 158                         .rx_buf = st->rx + 2,
 159                         .bits_per_word = 8,
 160                         .len = 2,
 161                 },
 162         };
 163
 164         mutex_lock(&st->buf_lock);
 165         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 166         st->tx[1] = 0;
 167         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 168         st->tx[3] = 0;
 169
 170         spi_message_init(&msg);
 171         spi_message_add_tail(&xfers[0], &msg);
 172         spi_message_add_tail(&xfers[1], &msg);
 173         ret = spi_sync(st->us, &msg);
 174         if (ret) {
 175                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 176                 goto error_ret;
 177         }
 178         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 179
 180         *val = tempval;
 181 error_ret:
 182         mutex_unlock(&st->buf_lock);
 183         return ret;
 184 }
 185
 186 enum lis3l02dq_rm_ind {
 187         LIS3L02DQ_ACCEL,
 188         LIS3L02DQ_GAIN,
 189         LIS3L02DQ_BIAS,
 190 };
 191
 192 static u8 lis3l02dq_axis_map[3][3] = {
 193         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 194                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 195                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 196         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 197                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 198                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 199         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 200                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 201                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 202 };
 203
 204 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 205                                  int e,
 206                                  int *val)
 207 {
 208         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 209 }
 210
 211 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 212                                   int event_code,
 213                                   int val)
 214 {
 215         u16 value = val;
 216         return lis3l02dq_spi_write_reg_s16(indio_dev,
 217                                            LIS3L02DQ_REG_THS_L_ADDR,
 218                                            value);
 219 }
 220
 221 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 222                                struct iio_chan_spec const *chan,
 223                                int val,
 224                                int val2,
 225                                long mask)
 226 {
 227         int ret = -EINVAL, reg;
 228         u8 uval;
 229         s8 sval;
 230         switch (mask) {
 231         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 232                 if (val > 255 || val < -256)
 233                         return -EINVAL;
 234                 sval = val;
 235                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 236                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, (u8 *)&sval);
 237                 break;
 238         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 239                 if (val & ~0xFF)
 240                         return -EINVAL;
 241                 uval = val;
 242                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 243                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, &uval);
 244                 break;
 245         }
 246         return ret;
 247 }
 248
 249 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 250                               struct iio_chan_spec const *chan,
 251                               int *val,
 252                               int *val2,
 253                               long mask)
 254 {
 255         u8 utemp;
 256         s8 stemp;
 257         ssize_t ret = 0;
 258         u8 reg;
 259
 260         switch (mask) {
 261         case 0:
 262                 /* Take the iio_dev status lock */
 263                 mutex_lock(&indio_dev->mlock);
 264                 if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
 265                         ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
 266                                                              chan->scan_index,
 267                                                              val);
 268                 else {
 269                         reg = lis3l02dq_axis_map
 270                                 [LIS3L02DQ_ACCEL][chan->address];
 271                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 272                 }
 273                 mutex_unlock(&indio_dev->mlock);
 274                 return IIO_VAL_INT;
 275         case (1 << IIO_CHAN_INFO_SCALE_SHARED):
 276                 *val = 0;
 277                 *val2 = 9580;
 278                 return IIO_VAL_INT_PLUS_MICRO;
 279         case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
 280                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 281                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 282                 if (ret)
 283                         goto error_ret;
 284                 /* to match with what previous code does */
 285                 *val = utemp;
 286                 return IIO_VAL_INT;
 287
 288         case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
 289                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 290                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 291                 /* to match with what previous code does */
 292                 *val = stemp;
 293                 return IIO_VAL_INT;
 294         }
 295 error_ret:
 296         return ret;
 297 }
 298
 299 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 300                                         struct device_attribute *attr,
 301                                         char *buf)
 302 {
 303         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 304         int ret, len = 0;
 305         s8 t;
 306         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 307                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 308                                        (u8 *)&t);
 309         if (ret)
 310                 return ret;
 311         t &= LIS3L02DQ_DEC_MASK;
 312         switch (t) {
 313         case LIS3L02DQ_REG_CTRL_1_DF_128:
 314                 len = sprintf(buf, "280\n");
 315                 break;
 316         case LIS3L02DQ_REG_CTRL_1_DF_64:
 317                 len = sprintf(buf, "560\n");
 318                 break;
 319         case LIS3L02DQ_REG_CTRL_1_DF_32:
 320                 len = sprintf(buf, "1120\n");
 321                 break;
 322         case LIS3L02DQ_REG_CTRL_1_DF_8:
 323                 len = sprintf(buf, "4480\n");
 324                 break;
 325         }
 326         return len;
 327 }
 328
 329 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 330                                          struct device_attribute *attr,
 331                                          const char *buf,
 332                                          size_t len)
 333 {
 334         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 335         long val;
 336         int ret;
 337         u8 t;
 338
 339         ret = strict_strtol(buf, 10, &val);
 340         if (ret)
 341                 return ret;
 342
 343         mutex_lock(&indio_dev->mlock);
 344         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 345                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 346                                        &t);
 347         if (ret)
 348                 goto error_ret_mutex;
 349         /* Wipe the bits clean */
 350         t &= ~LIS3L02DQ_DEC_MASK;
 351         switch (val) {
 352         case 280:
 353                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 354                 break;
 355         case 560:
 356                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 357                 break;
 358         case 1120:
 359                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 360                 break;
 361         case 4480:
 362                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 363                 break;
 364         default:
 365                 ret = -EINVAL;
 366                 goto error_ret_mutex;
 367         }
 368
 369         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 370                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 371                                         &t);
 372
 373 error_ret_mutex:
 374         mutex_unlock(&indio_dev->mlock);
 375
 376         return ret ? ret : len;
 377 }
 378
 379 static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
 380 {
 381         int ret;
 382         u8 val, valtest;
 383
 384         st->us->mode = SPI_MODE_3;
 385
 386         spi_setup(st->us);
 387
 388         val = LIS3L02DQ_DEFAULT_CTRL1;
 389         /* Write suitable defaults to ctrl1 */
 390         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 391                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 392                                         &val);
 393         if (ret) {
 394                 dev_err(&st->us->dev, "problem with setup control register 1");
 395                 goto err_ret;
 396         }
 397         /* Repeat as sometimes doesn't work first time?*/
 398         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 399                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 400                                         &val);
 401         if (ret) {
 402                 dev_err(&st->us->dev, "problem with setup control register 1");
 403                 goto err_ret;
 404         }
 405
 406         /* Read back to check this has worked acts as loose test of correct
 407          * chip */
 408         ret = lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 409                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 410                                        &valtest);
 411         if (ret || (valtest != val)) {
 412                 dev_err(&st->help.indio_dev->dev,
 413                         "device not playing ball %d %d\n", valtest, val);
 414                 ret = -EINVAL;
 415                 goto err_ret;
 416         }
 417
 418         val = LIS3L02DQ_DEFAULT_CTRL2;
 419         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 420                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 421                                         &val);
 422         if (ret) {
 423                 dev_err(&st->us->dev, "problem with setup control register 2");
 424                 goto err_ret;
 425         }
 426
 427         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 428         ret = lis3l02dq_spi_write_reg_8(st->help.indio_dev,
 429                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 430                                         &val);
 431         if (ret)
 432                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 433 err_ret:
 434
 435         return ret;
 436 }
 437
 438 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 439                               lis3l02dq_read_frequency,
 440                               lis3l02dq_write_frequency);
 441
 442 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 443
 444 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 445 {
 446         struct iio_dev *indio_dev = private;
 447         struct iio_sw_ring_helper_state *h
 448                 = iio_dev_get_devdata(indio_dev);
 449         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 450         u8 t;
 451
 452         s64 timestamp = iio_get_time_ns();
 453
 454         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 455                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 456                                  &t);
 457
 458         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 459                 iio_push_event(st->help.indio_dev, 0,
 460                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 461                                                   0,
 462                                                   IIO_EV_MOD_Z,
 463                                                   IIO_EV_TYPE_THRESH,
 464                                                   IIO_EV_DIR_RISING),
 465                                timestamp);
 466
 467         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 468                 iio_push_event(st->help.indio_dev, 0,
 469                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 470                                                   0,
 471                                                   IIO_EV_MOD_Z,
 472                                                   IIO_EV_TYPE_THRESH,
 473                                                   IIO_EV_DIR_FALLING),
 474                                timestamp);
 475
 476         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 477                 iio_push_event(st->help.indio_dev, 0,
 478                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 479                                                   0,
 480                                                   IIO_EV_MOD_Y,
 481                                                   IIO_EV_TYPE_THRESH,
 482                                                   IIO_EV_DIR_RISING),
 483                                timestamp);
 484
 485         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 486                 iio_push_event(st->help.indio_dev, 0,
 487                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 488                                                   0,
 489                                                   IIO_EV_MOD_Y,
 490                                                   IIO_EV_TYPE_THRESH,
 491                                                   IIO_EV_DIR_FALLING),
 492                                timestamp);
 493
 494         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 495                 iio_push_event(st->help.indio_dev, 0,
 496                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 497                                                   0,
 498                                                   IIO_EV_MOD_X,
 499                                                   IIO_EV_TYPE_THRESH,
 500                                                   IIO_EV_DIR_RISING),
 501                                timestamp);
 502
 503         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 504                 iio_push_event(st->help.indio_dev, 0,
 505                                IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
 506                                                   0,
 507                                                   IIO_EV_MOD_X,
 508                                                   IIO_EV_TYPE_THRESH,
 509                                                   IIO_EV_DIR_FALLING),
 510                                timestamp);
 511
 512         /* Ack and allow for new interrupts */
 513         lis3l02dq_spi_read_reg_8(st->help.indio_dev,
 514                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 515                                  &t);
 516
 517         return IRQ_HANDLED;
 518 }
 519
 520 #define LIS3L02DQ_INFO_MASK                             \
 521         ((1 << IIO_CHAN_INFO_SCALE_SHARED) |            \
 522          (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) |     \
 523          (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
 524
 525 #define LIS3L02DQ_EVENT_MASK                                    \
 526         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 527          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 528
 529 static struct iio_chan_spec lis3l02dq_channels[] = {
 530         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
 531                  0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 532         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
 533                  1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 534         IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
 535                  2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
 536         IIO_CHAN_SOFT_TIMESTAMP(3)
 537 };
 538
 539
 540 static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 541                                            int event_code)
 542 {
 543
 544         u8 val;
 545         int ret;
 546         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 547                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 548                           IIO_EV_DIR_RISING)));
 549         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 550                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 551                                        &val);
 552         if (ret < 0)
 553                 return ret;
 554
 555         return !!(val & mask);
 556 }
 557
 558 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 559 {
 560         struct iio_sw_ring_helper_state *h
 561                 = iio_dev_get_devdata(indio_dev);
 562         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 563         int ret;
 564         u8 control, val;
 565         bool irqtofree;
 566
 567         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 568                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 569                                        &control);
 570
 571         irqtofree = !!(control & LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 572
 573         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 574         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 575                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 576                                         &control);
 577         if (ret)
 578                 goto error_ret;
 579         /* Also for consistency clear the mask */
 580         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 581                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 582                                        &val);
 583         if (ret)
 584                 goto error_ret;
 585         val &= ~0x3f;
 586
 587         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 588                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 589                                         &val);
 590         if (ret)
 591                 goto error_ret;
 592
 593         if (irqtofree)
 594                 free_irq(st->us->irq, indio_dev);
 595
 596         ret = control;
 597 error_ret:
 598         return ret;
 599 }
 600
 601 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 602                                         int event_code,
 603                                         int state)
 604 {
 605         struct iio_sw_ring_helper_state *h
 606                 = iio_dev_get_devdata(indio_dev);
 607         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 608         int ret = 0;
 609         u8 val, control;
 610         u8 currentlyset;
 611         bool changed = false;
 612         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 613                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 614                           IIO_EV_DIR_RISING)));
 615
 616         mutex_lock(&indio_dev->mlock);
 617         /* read current control */
 618         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 619                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 620                                        &control);
 621         if (ret)
 622                 goto error_ret;
 623         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 624                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 625                                        &val);
 626         if (ret < 0)
 627                 goto error_ret;
 628         currentlyset = val & mask;
 629
 630         if (!currentlyset && state) {
 631                 changed = true;
 632                 val |= mask;
 633         } else if (currentlyset && !state) {
 634                 changed = true;
 635                 val &= ~mask;
 636         }
 637
 638         if (changed) {
 639                 if (!(control & LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT)) {
 640                         ret = request_threaded_irq(st->us->irq,
 641                                                    NULL,
 642                                                    &lis3l02dq_event_handler,
 643                                                    IRQF_TRIGGER_RISING |
 644                                                    IRQF_ONESHOT,
 645                                                    "lis3l02dq_event",
 646                                                    indio_dev);
 647                         if (ret)
 648                                 goto error_ret;
 649                 }
 650
 651                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 652                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 653                                                 &val);
 654                 if (ret)
 655                         goto error_ret;
 656                 control = val & 0x3f ?
 657                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 658                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 659                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 660                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 661                                                &control);
 662                 if (ret)
 663                         goto error_ret;
 664
 665                 /* remove interrupt handler if nothing is still on */
 666                 if (!(val & 0x3f))
 667                         free_irq(st->us->irq, indio_dev);
 668         }
 669
 670 error_ret:
 671         mutex_unlock(&indio_dev->mlock);
 672         return ret;
 673 }
 674
 675 static struct attribute *lis3l02dq_attributes[] = {
 676         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 677         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 678         NULL
 679 };
 680
 681 static const struct attribute_group lis3l02dq_attribute_group = {
 682         .attrs = lis3l02dq_attributes,
 683 };
 684
 685 static int __devinit lis3l02dq_probe(struct spi_device *spi)
 686 {
 687         int ret, regdone = 0;
 688         struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
 689         if (!st) {
 690                 ret =  -ENOMEM;
 691                 goto error_ret;
 692         }
 693
 694         /* this is only used tor removal purposes */
 695         spi_set_drvdata(spi, st);
 696
 697         /* Allocate the comms buffers */
 698         st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
 699         if (st->rx == NULL) {
 700                 ret = -ENOMEM;
 701                 goto error_free_st;
 702         }
 703         st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
 704         if (st->tx == NULL) {
 705                 ret = -ENOMEM;
 706                 goto error_free_rx;
 707         }
 708         st->us = spi;
 709         mutex_init(&st->buf_lock);
 710         /* setup the industrialio driver allocated elements */
 711         st->help.indio_dev = iio_allocate_device(0);
 712         if (st->help.indio_dev == NULL) {
 713                 ret = -ENOMEM;
 714                 goto error_free_tx;
 715         }
 716
 717         st->help.indio_dev->name = spi->dev.driver->name;
 718         st->help.indio_dev->dev.parent = &spi->dev;
 719         st->help.indio_dev->num_interrupt_lines = 1;
 720         st->help.indio_dev->channels = lis3l02dq_channels;
 721         st->help.indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 722         st->help.indio_dev->read_raw = &lis3l02dq_read_raw;
 723         st->help.indio_dev->write_raw = &lis3l02dq_write_raw;
 724         st->help.indio_dev->read_event_value = &lis3l02dq_read_thresh;
 725         st->help.indio_dev->write_event_value = &lis3l02dq_write_thresh;
 726         st->help.indio_dev->write_event_config = &lis3l02dq_write_event_config;
 727         st->help.indio_dev->read_event_config = &lis3l02dq_read_event_config;
 728         st->help.indio_dev->attrs = &lis3l02dq_attribute_group;
 729         st->help.indio_dev->dev_data = (void *)(&st->help);
 730         st->help.indio_dev->driver_module = THIS_MODULE;
 731         st->help.indio_dev->modes = INDIO_DIRECT_MODE;
 732
 733         ret = lis3l02dq_configure_ring(st->help.indio_dev);
 734         if (ret)
 735                 goto error_free_dev;
 736
 737         ret = iio_device_register(st->help.indio_dev);
 738         if (ret)
 739                 goto error_unreg_ring_funcs;
 740         regdone = 1;
 741
 742         ret = iio_ring_buffer_register_ex(st->help.indio_dev->ring, 0,
 743                                           lis3l02dq_channels,
 744                                           ARRAY_SIZE(lis3l02dq_channels));
 745         if (ret) {
 746                 printk(KERN_ERR "failed to initialize the ring\n");
 747                 goto error_unreg_ring_funcs;
 748         }
 749
 750         if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
 751                 ret = lis3l02dq_probe_trigger(st->help.indio_dev);
 752                 if (ret)
 753                         goto error_uninitialize_ring;
 754         }
 755
 756         /* Get the device into a sane initial state */
 757         ret = lis3l02dq_initial_setup(st);
 758         if (ret)
 759                 goto error_remove_trigger;
 760         return 0;
 761
 762 error_remove_trigger:
 763         if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
 764                 lis3l02dq_remove_trigger(st->help.indio_dev);
 765 error_uninitialize_ring:
 766         iio_ring_buffer_unregister(st->help.indio_dev->ring);
 767 error_unreg_ring_funcs:
 768         lis3l02dq_unconfigure_ring(st->help.indio_dev);
 769 error_free_dev:
 770         if (regdone)
 771                 iio_device_unregister(st->help.indio_dev);
 772         else
 773                 iio_free_device(st->help.indio_dev);
 774 error_free_tx:
 775         kfree(st->tx);
 776 error_free_rx:
 777         kfree(st->rx);
 778 error_free_st:
 779         kfree(st);
 780 error_ret:
 781         return ret;
 782 }
 783
 784 /* Power down the device */
 785 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 786 {
 787         int ret;
 788         struct iio_sw_ring_helper_state *h
 789                 = iio_dev_get_devdata(indio_dev);
 790         struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
 791         u8 val = 0;
 792
 793         mutex_lock(&indio_dev->mlock);
 794         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 795                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 796                                         &val);
 797         if (ret) {
 798                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 799                 goto err_ret;
 800         }
 801
 802         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 803                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 804                                         &val);
 805         if (ret)
 806                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 807 err_ret:
 808         mutex_unlock(&indio_dev->mlock);
 809         return ret;
 810 }
 811
 812 /* fixme, confirm ordering in this function */
 813 static int lis3l02dq_remove(struct spi_device *spi)
 814 {
 815         int ret;
 816         struct lis3l02dq_state *st = spi_get_drvdata(spi);
 817         struct iio_dev *indio_dev = st->help.indio_dev;
 818         ret = lis3l02dq_disable_all_events(indio_dev);
 819         if (ret)
 820                 goto err_ret;
 821
 822         ret = lis3l02dq_stop_device(indio_dev);
 823         if (ret)
 824                 goto err_ret;
 825
 826         lis3l02dq_remove_trigger(indio_dev);
 827         iio_ring_buffer_unregister(indio_dev->ring);
 828         lis3l02dq_unconfigure_ring(indio_dev);
 829         iio_device_unregister(indio_dev);
 830         kfree(st->tx);
 831         kfree(st->rx);
 832         kfree(st);
 833
 834         return 0;
 835
 836 err_ret:
 837         return ret;
 838 }
 839
 840 static struct spi_driver lis3l02dq_driver = {
 841         .driver = {
 842                 .name = "lis3l02dq",
 843                 .owner = THIS_MODULE,
 844         },
 845         .probe = lis3l02dq_probe,
 846         .remove = __devexit_p(lis3l02dq_remove),
 847 };
 848
 849 static __init int lis3l02dq_init(void)
 850 {
 851         return spi_register_driver(&lis3l02dq_driver);
 852 }
 853 module_init(lis3l02dq_init);
 854
 855 static __exit void lis3l02dq_exit(void)
 856 {
 857         spi_unregister_driver(&lis3l02dq_driver);
 858 }
 859 module_exit(lis3l02dq_exit);
 860
 861 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
 862 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 863 MODULE_LICENSE("GPL v2");