2 * lis3l02dq.c support STMicroelectronics LISD02DQ
3 * 3d 2g Linear Accelerometers via SPI
5 * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 * 16 bit left justified mode used.
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/gpio.h>
18 #include <linux/of_gpio.h>
19 #include <linux/mutex.h>
20 #include <linux/device.h>
21 #include <linux/kernel.h>
22 #include <linux/spi/spi.h>
23 #include <linux/slab.h>
24 #include <linux/sysfs.h>
25 #include <linux/module.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/sysfs.h>
29 #include <linux/iio/events.h>
30 #include <linux/iio/buffer.h>
32 #include "lis3l02dq.h"
34 /* At the moment the spi framework doesn't allow global setting of cs_change.
35 * It's in the likely to be added comment at the top of spi.h.
36 * This means that use cannot be made of spi_write etc.
38 /* direct copy of the irq_default_primary_handler */
39 #ifndef CONFIG_IIO_BUFFER
40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
42 return IRQ_WAKE_THREAD;
47 * lis3l02dq_spi_read_reg_8() - read single byte from a single register
48 * @indio_dev: iio_dev for this actual device
49 * @reg_address: the address of the register to be read
50 * @val: pass back the resulting value
52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
53 u8 reg_address, u8 *val)
55 struct lis3l02dq_state *st = iio_priv(indio_dev);
57 struct spi_transfer xfer = {
64 mutex_lock(&st->buf_lock);
65 st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
68 ret = spi_sync_transfer(st->us, &xfer, 1);
70 mutex_unlock(&st->buf_lock);
76 * lis3l02dq_spi_write_reg_8() - write single byte to a register
77 * @indio_dev: iio_dev for this device
78 * @reg_address: the address of the register to be written
79 * @val: the value to write
81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
86 struct lis3l02dq_state *st = iio_priv(indio_dev);
88 mutex_lock(&st->buf_lock);
89 st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
91 ret = spi_write(st->us, st->tx, 2);
92 mutex_unlock(&st->buf_lock);
98 * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
99 * @indio_dev: iio_dev for this device
100 * @lower_reg_address: the address of the lower of the two registers.
101 * Second register is assumed to have address one greater.
102 * @value: value to be written
104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
105 u8 lower_reg_address,
109 struct lis3l02dq_state *st = iio_priv(indio_dev);
110 struct spi_transfer xfers[] = { {
116 .tx_buf = st->tx + 2,
122 mutex_lock(&st->buf_lock);
123 st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
124 st->tx[1] = value & 0xFF;
125 st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
126 st->tx[3] = (value >> 8) & 0xFF;
128 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
129 mutex_unlock(&st->buf_lock);
134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
135 u8 lower_reg_address,
138 struct lis3l02dq_state *st = iio_priv(indio_dev);
141 struct spi_transfer xfers[] = { {
148 .tx_buf = st->tx + 2,
149 .rx_buf = st->rx + 2,
155 mutex_lock(&st->buf_lock);
156 st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
158 st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
161 ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
163 dev_err(&st->us->dev, "problem when reading 16 bit register");
166 tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
170 mutex_unlock(&st->buf_lock);
174 enum lis3l02dq_rm_ind {
180 static u8 lis3l02dq_axis_map[3][3] = {
181 [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
182 LIS3L02DQ_REG_OUT_Y_L_ADDR,
183 LIS3L02DQ_REG_OUT_Z_L_ADDR },
184 [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
185 LIS3L02DQ_REG_GAIN_Y_ADDR,
186 LIS3L02DQ_REG_GAIN_Z_ADDR },
187 [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
188 LIS3L02DQ_REG_OFFSET_Y_ADDR,
189 LIS3L02DQ_REG_OFFSET_Z_ADDR }
192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
193 const struct iio_chan_spec *chan,
194 enum iio_event_type type,
195 enum iio_event_direction dir,
196 enum iio_event_info info,
201 ret = lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
207 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
208 const struct iio_chan_spec *chan,
209 enum iio_event_type type,
210 enum iio_event_direction dir,
211 enum iio_event_info info,
215 return lis3l02dq_spi_write_reg_s16(indio_dev,
216 LIS3L02DQ_REG_THS_L_ADDR,
220 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
221 struct iio_chan_spec const *chan,
226 int ret = -EINVAL, reg;
230 case IIO_CHAN_INFO_CALIBBIAS:
231 if (val > 255 || val < -256)
234 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
235 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
237 case IIO_CHAN_INFO_CALIBSCALE:
241 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
242 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
248 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
249 struct iio_chan_spec const *chan,
260 case IIO_CHAN_INFO_RAW:
261 /* Take the iio_dev status lock */
262 mutex_lock(&indio_dev->mlock);
263 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
266 reg = lis3l02dq_axis_map
267 [LIS3L02DQ_ACCEL][chan->address];
268 ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
270 mutex_unlock(&indio_dev->mlock);
274 case IIO_CHAN_INFO_SCALE:
277 return IIO_VAL_INT_PLUS_MICRO;
278 case IIO_CHAN_INFO_CALIBSCALE:
279 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
280 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
283 /* to match with what previous code does */
287 case IIO_CHAN_INFO_CALIBBIAS:
288 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
289 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
290 /* to match with what previous code does */
298 static ssize_t lis3l02dq_read_frequency(struct device *dev,
299 struct device_attribute *attr,
302 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
305 ret = lis3l02dq_spi_read_reg_8(indio_dev,
306 LIS3L02DQ_REG_CTRL_1_ADDR,
310 t &= LIS3L02DQ_DEC_MASK;
312 case LIS3L02DQ_REG_CTRL_1_DF_128:
313 len = sprintf(buf, "280\n");
315 case LIS3L02DQ_REG_CTRL_1_DF_64:
316 len = sprintf(buf, "560\n");
318 case LIS3L02DQ_REG_CTRL_1_DF_32:
319 len = sprintf(buf, "1120\n");
321 case LIS3L02DQ_REG_CTRL_1_DF_8:
322 len = sprintf(buf, "4480\n");
328 static ssize_t lis3l02dq_write_frequency(struct device *dev,
329 struct device_attribute *attr,
333 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
338 ret = kstrtoul(buf, 10, &val);
342 mutex_lock(&indio_dev->mlock);
343 ret = lis3l02dq_spi_read_reg_8(indio_dev,
344 LIS3L02DQ_REG_CTRL_1_ADDR,
347 goto error_ret_mutex;
348 /* Wipe the bits clean */
349 t &= ~LIS3L02DQ_DEC_MASK;
352 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
355 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
358 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
361 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
365 goto error_ret_mutex;
368 ret = lis3l02dq_spi_write_reg_8(indio_dev,
369 LIS3L02DQ_REG_CTRL_1_ADDR,
373 mutex_unlock(&indio_dev->mlock);
375 return ret ? ret : len;
378 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
380 struct lis3l02dq_state *st = iio_priv(indio_dev);
384 st->us->mode = SPI_MODE_3;
388 val = LIS3L02DQ_DEFAULT_CTRL1;
389 /* Write suitable defaults to ctrl1 */
390 ret = lis3l02dq_spi_write_reg_8(indio_dev,
391 LIS3L02DQ_REG_CTRL_1_ADDR,
394 dev_err(&st->us->dev, "problem with setup control register 1");
397 /* Repeat as sometimes doesn't work first time? */
398 ret = lis3l02dq_spi_write_reg_8(indio_dev,
399 LIS3L02DQ_REG_CTRL_1_ADDR,
402 dev_err(&st->us->dev, "problem with setup control register 1");
406 /* Read back to check this has worked acts as loose test of correct
408 ret = lis3l02dq_spi_read_reg_8(indio_dev,
409 LIS3L02DQ_REG_CTRL_1_ADDR,
411 if (ret || (valtest != val)) {
412 dev_err(&indio_dev->dev,
413 "device not playing ball %d %d\n", valtest, val);
418 val = LIS3L02DQ_DEFAULT_CTRL2;
419 ret = lis3l02dq_spi_write_reg_8(indio_dev,
420 LIS3L02DQ_REG_CTRL_2_ADDR,
423 dev_err(&st->us->dev, "problem with setup control register 2");
427 val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
428 ret = lis3l02dq_spi_write_reg_8(indio_dev,
429 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
432 dev_err(&st->us->dev, "problem with interrupt cfg register");
438 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
439 lis3l02dq_read_frequency,
440 lis3l02dq_write_frequency);
442 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
444 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
446 struct iio_dev *indio_dev = private;
449 s64 timestamp = iio_get_time_ns();
451 lis3l02dq_spi_read_reg_8(indio_dev,
452 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
455 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
456 iio_push_event(indio_dev,
457 IIO_MOD_EVENT_CODE(IIO_ACCEL,
464 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
465 iio_push_event(indio_dev,
466 IIO_MOD_EVENT_CODE(IIO_ACCEL,
473 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
474 iio_push_event(indio_dev,
475 IIO_MOD_EVENT_CODE(IIO_ACCEL,
482 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
483 iio_push_event(indio_dev,
484 IIO_MOD_EVENT_CODE(IIO_ACCEL,
491 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
492 iio_push_event(indio_dev,
493 IIO_MOD_EVENT_CODE(IIO_ACCEL,
500 if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
501 iio_push_event(indio_dev,
502 IIO_MOD_EVENT_CODE(IIO_ACCEL,
509 /* Ack and allow for new interrupts */
510 lis3l02dq_spi_read_reg_8(indio_dev,
511 LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
517 static const struct iio_event_spec lis3l02dq_event[] = {
519 .type = IIO_EV_TYPE_THRESH,
520 .dir = IIO_EV_DIR_RISING,
521 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
522 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
524 .type = IIO_EV_TYPE_THRESH,
525 .dir = IIO_EV_DIR_FALLING,
526 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
527 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
531 #define LIS3L02DQ_CHAN(index, mod) \
536 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
537 BIT(IIO_CHAN_INFO_CALIBSCALE) | \
538 BIT(IIO_CHAN_INFO_CALIBBIAS), \
539 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
541 .scan_index = index, \
547 .event_spec = lis3l02dq_event, \
548 .num_event_specs = ARRAY_SIZE(lis3l02dq_event), \
551 static const struct iio_chan_spec lis3l02dq_channels[] = {
552 LIS3L02DQ_CHAN(0, IIO_MOD_X),
553 LIS3L02DQ_CHAN(1, IIO_MOD_Y),
554 LIS3L02DQ_CHAN(2, IIO_MOD_Z),
555 IIO_CHAN_SOFT_TIMESTAMP(3)
559 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
560 const struct iio_chan_spec *chan,
561 enum iio_event_type type,
562 enum iio_event_direction dir)
567 u8 mask = (1 << (chan->channel2*2 + (dir == IIO_EV_DIR_RISING)));
568 ret = lis3l02dq_spi_read_reg_8(indio_dev,
569 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
574 return !!(val & mask);
577 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
582 ret = lis3l02dq_spi_read_reg_8(indio_dev,
583 LIS3L02DQ_REG_CTRL_2_ADDR,
586 control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
587 ret = lis3l02dq_spi_write_reg_8(indio_dev,
588 LIS3L02DQ_REG_CTRL_2_ADDR,
592 /* Also for consistency clear the mask */
593 ret = lis3l02dq_spi_read_reg_8(indio_dev,
594 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
600 ret = lis3l02dq_spi_write_reg_8(indio_dev,
601 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
611 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
612 const struct iio_chan_spec *chan,
613 enum iio_event_type type,
614 enum iio_event_direction dir,
620 bool changed = false;
621 u8 mask = (1 << (chan->channel2*2 + (dir == IIO_EV_DIR_RISING)));
623 mutex_lock(&indio_dev->mlock);
624 /* read current control */
625 ret = lis3l02dq_spi_read_reg_8(indio_dev,
626 LIS3L02DQ_REG_CTRL_2_ADDR,
630 ret = lis3l02dq_spi_read_reg_8(indio_dev,
631 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
635 currentlyset = val & mask;
637 if (!currentlyset && state) {
640 } else if (currentlyset && !state) {
646 ret = lis3l02dq_spi_write_reg_8(indio_dev,
647 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
651 control = val & 0x3f ?
652 (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
653 (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
654 ret = lis3l02dq_spi_write_reg_8(indio_dev,
655 LIS3L02DQ_REG_CTRL_2_ADDR,
662 mutex_unlock(&indio_dev->mlock);
666 static struct attribute *lis3l02dq_attributes[] = {
667 &iio_dev_attr_sampling_frequency.dev_attr.attr,
668 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
672 static const struct attribute_group lis3l02dq_attribute_group = {
673 .attrs = lis3l02dq_attributes,
676 static const struct iio_info lis3l02dq_info = {
677 .read_raw = &lis3l02dq_read_raw,
678 .write_raw = &lis3l02dq_write_raw,
679 .read_event_value = &lis3l02dq_read_thresh,
680 .write_event_value = &lis3l02dq_write_thresh,
681 .write_event_config = &lis3l02dq_write_event_config,
682 .read_event_config = &lis3l02dq_read_event_config,
683 .driver_module = THIS_MODULE,
684 .attrs = &lis3l02dq_attribute_group,
687 static int lis3l02dq_probe(struct spi_device *spi)
690 struct lis3l02dq_state *st;
691 struct iio_dev *indio_dev;
693 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
696 st = iio_priv(indio_dev);
697 /* this is only used for removal purposes */
698 spi_set_drvdata(spi, indio_dev);
701 st->gpio = of_get_gpio(spi->dev.of_node, 0);
702 mutex_init(&st->buf_lock);
703 indio_dev->name = spi->dev.driver->name;
704 indio_dev->dev.parent = &spi->dev;
705 indio_dev->info = &lis3l02dq_info;
706 indio_dev->channels = lis3l02dq_channels;
707 indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
709 indio_dev->modes = INDIO_DIRECT_MODE;
711 ret = lis3l02dq_configure_buffer(indio_dev);
715 ret = iio_buffer_register(indio_dev,
717 ARRAY_SIZE(lis3l02dq_channels));
719 dev_err(&spi->dev, "failed to initialize the buffer\n");
720 goto error_unreg_buffer_funcs;
724 ret = request_threaded_irq(st->us->irq,
726 &lis3l02dq_event_handler,
731 goto error_uninitialize_buffer;
733 ret = lis3l02dq_probe_trigger(indio_dev);
735 goto error_free_interrupt;
738 /* Get the device into a sane initial state */
739 ret = lis3l02dq_initial_setup(indio_dev);
741 goto error_remove_trigger;
743 ret = iio_device_register(indio_dev);
745 goto error_remove_trigger;
749 error_remove_trigger:
751 lis3l02dq_remove_trigger(indio_dev);
752 error_free_interrupt:
754 free_irq(st->us->irq, indio_dev);
755 error_uninitialize_buffer:
756 iio_buffer_unregister(indio_dev);
757 error_unreg_buffer_funcs:
758 lis3l02dq_unconfigure_buffer(indio_dev);
762 /* Power down the device */
763 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
766 struct lis3l02dq_state *st = iio_priv(indio_dev);
769 mutex_lock(&indio_dev->mlock);
770 ret = lis3l02dq_spi_write_reg_8(indio_dev,
771 LIS3L02DQ_REG_CTRL_1_ADDR,
774 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
778 ret = lis3l02dq_spi_write_reg_8(indio_dev,
779 LIS3L02DQ_REG_CTRL_2_ADDR,
782 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
784 mutex_unlock(&indio_dev->mlock);
788 /* fixme, confirm ordering in this function */
789 static int lis3l02dq_remove(struct spi_device *spi)
791 struct iio_dev *indio_dev = spi_get_drvdata(spi);
792 struct lis3l02dq_state *st = iio_priv(indio_dev);
794 iio_device_unregister(indio_dev);
796 lis3l02dq_disable_all_events(indio_dev);
797 lis3l02dq_stop_device(indio_dev);
800 free_irq(st->us->irq, indio_dev);
802 lis3l02dq_remove_trigger(indio_dev);
803 iio_buffer_unregister(indio_dev);
804 lis3l02dq_unconfigure_buffer(indio_dev);
809 static struct spi_driver lis3l02dq_driver = {
812 .owner = THIS_MODULE,
814 .probe = lis3l02dq_probe,
815 .remove = lis3l02dq_remove,
817 module_spi_driver(lis3l02dq_driver);
819 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
820 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
821 MODULE_LICENSE("GPL v2");
822 MODULE_ALIAS("spi:lis3l02dq");