1 #include <linux/interrupt.h>
2 #include <linux/gpio.h>
3 #include <linux/mutex.h>
4 #include <linux/kernel.h>
5 #include <linux/spi/spi.h>
6 #include <linux/slab.h>
7 #include <linux/export.h>
9 #include <linux/iio/iio.h>
10 #include "../ring_sw.h"
11 #include <linux/iio/kfifo_buf.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/iio/trigger_consumer.h>
14 #include "lis3l02dq.h"
17 * combine_8_to_16() utility function to munge to u8s into u16
19 static inline u16 combine_8_to_16(u8 lower, u8 upper)
23 return _lower | (_upper << 8);
27 * lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
29 irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
31 struct iio_dev *indio_dev = private;
32 struct lis3l02dq_state *st = iio_priv(indio_dev);
35 iio_trigger_poll(st->trig, iio_get_time_ns());
38 return IRQ_WAKE_THREAD;
41 static const u8 read_all_tx_array[] = {
42 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_L_ADDR), 0,
43 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_X_H_ADDR), 0,
44 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_L_ADDR), 0,
45 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Y_H_ADDR), 0,
46 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_L_ADDR), 0,
47 LIS3L02DQ_READ_REG(LIS3L02DQ_REG_OUT_Z_H_ADDR), 0,
51 * lis3l02dq_read_all() Reads all channels currently selected
52 * @st: device specific state
53 * @rx_array: (dma capable) receive array, must be at least
54 * 4*number of channels
56 static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
58 struct lis3l02dq_state *st = iio_priv(indio_dev);
59 struct spi_transfer *xfers;
60 struct spi_message msg;
63 xfers = kcalloc(bitmap_weight(indio_dev->active_scan_mask,
64 indio_dev->masklength) * 2,
65 sizeof(*xfers), GFP_KERNEL);
69 mutex_lock(&st->buf_lock);
71 for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
72 if (test_bit(i, indio_dev->active_scan_mask)) {
74 xfers[j].tx_buf = st->tx + 2*j;
75 st->tx[2*j] = read_all_tx_array[i*4];
78 xfers[j].rx_buf = rx_array + j*2;
79 xfers[j].bits_per_word = 8;
81 xfers[j].cs_change = 1;
85 xfers[j].tx_buf = st->tx + 2*j;
86 st->tx[2*j] = read_all_tx_array[i*4 + 2];
89 xfers[j].rx_buf = rx_array + j*2;
90 xfers[j].bits_per_word = 8;
92 xfers[j].cs_change = 1;
96 /* After these are transmitted, the rx_buff should have
97 * values in alternate bytes
99 spi_message_init(&msg);
100 for (j = 0; j < bitmap_weight(indio_dev->active_scan_mask,
101 indio_dev->masklength) * 2; j++)
102 spi_message_add_tail(&xfers[j], &msg);
104 ret = spi_sync(st->us, &msg);
105 mutex_unlock(&st->buf_lock);
111 static int lis3l02dq_get_buffer_element(struct iio_dev *indio_dev,
116 s16 *data = (s16 *)buf;
117 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
118 indio_dev->masklength);
120 rx_array = kzalloc(4 * scan_count, GFP_KERNEL);
121 if (rx_array == NULL)
123 ret = lis3l02dq_read_all(indio_dev, rx_array);
126 for (i = 0; i < scan_count; i++)
127 data[i] = combine_8_to_16(rx_array[i*4+1],
131 return i*sizeof(data[0]);
134 static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
136 struct iio_poll_func *pf = p;
137 struct iio_dev *indio_dev = pf->indio_dev;
138 struct iio_buffer *buffer = indio_dev->buffer;
142 data = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
144 dev_err(indio_dev->dev.parent,
145 "memory alloc failed in buffer bh");
149 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
150 len = lis3l02dq_get_buffer_element(indio_dev, data);
152 /* Guaranteed to be aligned with 8 byte boundary */
153 if (indio_dev->scan_timestamp)
154 *(s64 *)((u8 *)data + ALIGN(len, sizeof(s64)))
156 buffer->access->store_to(buffer, (u8 *)data, pf->timestamp);
160 iio_trigger_notify_done(indio_dev->trig);
164 /* Caller responsible for locking as necessary. */
166 __lis3l02dq_write_data_ready_config(struct iio_dev *indio_dev, bool state)
171 struct lis3l02dq_state *st = iio_priv(indio_dev);
173 /* Get the current event mask register */
174 ret = lis3l02dq_spi_read_reg_8(indio_dev,
175 LIS3L02DQ_REG_CTRL_2_ADDR,
179 /* Find out if data ready is already on */
181 = valold & LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
183 /* Disable requested */
184 if (!state && currentlyset) {
185 /* disable the data ready signal */
186 valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
188 /* The double write is to overcome a hardware bug?*/
189 ret = lis3l02dq_spi_write_reg_8(indio_dev,
190 LIS3L02DQ_REG_CTRL_2_ADDR,
194 ret = lis3l02dq_spi_write_reg_8(indio_dev,
195 LIS3L02DQ_REG_CTRL_2_ADDR,
199 st->trigger_on = false;
200 /* Enable requested */
201 } else if (state && !currentlyset) {
202 /* if not set, enable requested */
203 /* first disable all events */
204 ret = lis3l02dq_disable_all_events(indio_dev);
209 LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
211 st->trigger_on = true;
212 ret = lis3l02dq_spi_write_reg_8(indio_dev,
213 LIS3L02DQ_REG_CTRL_2_ADDR,
225 * lis3l02dq_data_rdy_trigger_set_state() set datardy interrupt state
227 * If disabling the interrupt also does a final read to ensure it is clear.
228 * This is only important in some cases where the scan enable elements are
229 * switched before the buffer is reenabled.
231 static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
234 struct iio_dev *indio_dev = trig->private_data;
238 __lis3l02dq_write_data_ready_config(indio_dev, state);
239 if (state == false) {
241 * A possible quirk with the handler is currently worked around
242 * by ensuring outstanding read events are cleared.
244 ret = lis3l02dq_read_all(indio_dev, NULL);
246 lis3l02dq_spi_read_reg_8(indio_dev,
247 LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
253 * lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
254 * @trig: the datardy trigger
256 static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
258 struct iio_dev *indio_dev = trig->private_data;
259 struct lis3l02dq_state *st = iio_priv(indio_dev);
262 /* If gpio still high (or high again) */
263 /* In theory possible we will need to do this several times */
264 for (i = 0; i < 5; i++)
265 if (gpio_get_value(irq_to_gpio(st->us->irq)))
266 lis3l02dq_read_all(indio_dev, NULL);
271 "Failed to clear the interrupt for lis3l02dq\n");
273 /* irq reenabled so success! */
277 static const struct iio_trigger_ops lis3l02dq_trigger_ops = {
278 .owner = THIS_MODULE,
279 .set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state,
280 .try_reenable = &lis3l02dq_trig_try_reen,
283 int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
286 struct lis3l02dq_state *st = iio_priv(indio_dev);
288 st->trig = iio_trigger_alloc("lis3l02dq-dev%d", indio_dev->id);
294 st->trig->dev.parent = &st->us->dev;
295 st->trig->ops = &lis3l02dq_trigger_ops;
296 st->trig->private_data = indio_dev;
297 ret = iio_trigger_register(st->trig);
299 goto error_free_trig;
304 iio_trigger_free(st->trig);
309 void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
311 struct lis3l02dq_state *st = iio_priv(indio_dev);
313 iio_trigger_unregister(st->trig);
314 iio_trigger_free(st->trig);
317 void lis3l02dq_unconfigure_buffer(struct iio_dev *indio_dev)
319 iio_dealloc_pollfunc(indio_dev->pollfunc);
320 lis3l02dq_free_buf(indio_dev->buffer);
323 static int lis3l02dq_buffer_postenable(struct iio_dev *indio_dev)
325 /* Disable unwanted channels otherwise the interrupt will not clear */
328 bool oneenabled = false;
330 ret = lis3l02dq_spi_read_reg_8(indio_dev,
331 LIS3L02DQ_REG_CTRL_1_ADDR,
336 if (test_bit(0, indio_dev->active_scan_mask)) {
337 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
340 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
341 if (test_bit(1, indio_dev->active_scan_mask)) {
342 t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
345 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
346 if (test_bit(2, indio_dev->active_scan_mask)) {
347 t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
350 t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
352 if (!oneenabled) /* what happens in this case is unknown */
354 ret = lis3l02dq_spi_write_reg_8(indio_dev,
355 LIS3L02DQ_REG_CTRL_1_ADDR,
360 return iio_triggered_buffer_postenable(indio_dev);
365 /* Turn all channels on again */
366 static int lis3l02dq_buffer_predisable(struct iio_dev *indio_dev)
371 ret = iio_triggered_buffer_predisable(indio_dev);
375 ret = lis3l02dq_spi_read_reg_8(indio_dev,
376 LIS3L02DQ_REG_CTRL_1_ADDR,
380 t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
381 LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
382 LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
384 ret = lis3l02dq_spi_write_reg_8(indio_dev,
385 LIS3L02DQ_REG_CTRL_1_ADDR,
392 static const struct iio_buffer_setup_ops lis3l02dq_buffer_setup_ops = {
393 .preenable = &iio_sw_buffer_preenable,
394 .postenable = &lis3l02dq_buffer_postenable,
395 .predisable = &lis3l02dq_buffer_predisable,
398 int lis3l02dq_configure_buffer(struct iio_dev *indio_dev)
401 struct iio_buffer *buffer;
403 buffer = lis3l02dq_alloc_buf(indio_dev);
407 indio_dev->buffer = buffer;
409 buffer->scan_timestamp = true;
410 indio_dev->setup_ops = &lis3l02dq_buffer_setup_ops;
412 /* Functions are NULL as we set handler below */
413 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
414 &lis3l02dq_trigger_handler,
417 "lis3l02dq_consumer%d",
420 if (indio_dev->pollfunc == NULL) {
422 goto error_iio_sw_rb_free;
425 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
428 error_iio_sw_rb_free:
429 lis3l02dq_free_buf(indio_dev->buffer);