2 * AD7152 capacitive sensor driver supporting AD7152/3
4 * Copyright 2010-2011a Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
22 * TODO: Check compliance of calibbias with abi (units)
25 * AD7152 registers definition
28 #define AD7152_REG_STATUS 0
29 #define AD7152_REG_CH1_DATA_HIGH 1
30 #define AD7152_REG_CH2_DATA_HIGH 3
31 #define AD7152_REG_CH1_OFFS_HIGH 5
32 #define AD7152_REG_CH2_OFFS_HIGH 7
33 #define AD7152_REG_CH1_GAIN_HIGH 9
34 #define AD7152_REG_CH1_SETUP 11
35 #define AD7152_REG_CH2_GAIN_HIGH 12
36 #define AD7152_REG_CH2_SETUP 14
37 #define AD7152_REG_CFG 15
38 #define AD7152_REG_RESEVERD 16
39 #define AD7152_REG_CAPDAC_POS 17
40 #define AD7152_REG_CAPDAC_NEG 18
41 #define AD7152_REG_CFG2 26
43 /* Status Register Bit Designations (AD7152_REG_STATUS) */
44 #define AD7152_STATUS_RDY1 BIT(0)
45 #define AD7152_STATUS_RDY2 BIT(1)
46 #define AD7152_STATUS_C1C2 BIT(2)
47 #define AD7152_STATUS_PWDN BIT(7)
49 /* Setup Register Bit Designations (AD7152_REG_CHx_SETUP) */
50 #define AD7152_SETUP_CAPDIFF (1 << 5)
51 #define AD7152_SETUP_RANGE_2pF (0 << 6)
52 #define AD7152_SETUP_RANGE_0_5pF (1 << 6)
53 #define AD7152_SETUP_RANGE_1pF (2 << 6)
54 #define AD7152_SETUP_RANGE_4pF (3 << 6)
55 #define AD7152_SETUP_RANGE(x) ((x) << 6)
57 /* Config Register Bit Designations (AD7152_REG_CFG) */
58 #define AD7152_CONF_CH2EN (1 << 3)
59 #define AD7152_CONF_CH1EN (1 << 4)
60 #define AD7152_CONF_MODE_IDLE (0 << 0)
61 #define AD7152_CONF_MODE_CONT_CONV (1 << 0)
62 #define AD7152_CONF_MODE_SINGLE_CONV (2 << 0)
63 #define AD7152_CONF_MODE_OFFS_CAL (5 << 0)
64 #define AD7152_CONF_MODE_GAIN_CAL (6 << 0)
66 /* Capdac Register Bit Designations (AD7152_REG_CAPDAC_XXX) */
67 #define AD7152_CAPDAC_DACEN (1 << 7)
68 #define AD7152_CAPDAC_DACP(x) ((x) & 0x1F)
70 /* CFG2 Register Bit Designations (AD7152_REG_CFG2) */
71 #define AD7152_CFG2_OSR(x) (((x) & 0x3) << 4)
81 * struct ad7152_chip_info - chip specific information
84 struct ad7152_chip_info {
85 struct i2c_client *client;
87 * Capacitive channel digital filter setup;
88 * conversion time/update rate setup per channel
92 struct mutex state_lock; /* protect hardware state */
95 static inline ssize_t ad7152_start_calib(struct device *dev,
96 struct device_attribute *attr,
101 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
102 struct ad7152_chip_info *chip = iio_priv(indio_dev);
103 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
105 int ret, timeout = 10;
107 ret = strtobool(buf, &doit);
114 if (this_attr->address == 0)
115 regval |= AD7152_CONF_CH1EN;
117 regval |= AD7152_CONF_CH2EN;
119 mutex_lock(&chip->state_lock);
120 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG, regval);
122 mutex_unlock(&chip->state_lock);
128 ret = i2c_smbus_read_byte_data(chip->client, AD7152_REG_CFG);
130 mutex_unlock(&chip->state_lock);
133 } while ((ret == regval) && timeout--);
135 mutex_unlock(&chip->state_lock);
139 static ssize_t ad7152_start_offset_calib(struct device *dev,
140 struct device_attribute *attr,
144 return ad7152_start_calib(dev, attr, buf, len,
145 AD7152_CONF_MODE_OFFS_CAL);
148 static ssize_t ad7152_start_gain_calib(struct device *dev,
149 struct device_attribute *attr,
153 return ad7152_start_calib(dev, attr, buf, len,
154 AD7152_CONF_MODE_GAIN_CAL);
157 static IIO_DEVICE_ATTR(in_capacitance0_calibbias_calibration,
158 0200, NULL, ad7152_start_offset_calib, 0);
159 static IIO_DEVICE_ATTR(in_capacitance1_calibbias_calibration,
160 0200, NULL, ad7152_start_offset_calib, 1);
161 static IIO_DEVICE_ATTR(in_capacitance0_calibscale_calibration,
162 0200, NULL, ad7152_start_gain_calib, 0);
163 static IIO_DEVICE_ATTR(in_capacitance1_calibscale_calibration,
164 0200, NULL, ad7152_start_gain_calib, 1);
166 /* Values are Update Rate (Hz), Conversion Time (ms) + 1*/
167 static const unsigned char ad7152_filter_rate_table[][2] = {
168 {200, 5 + 1}, {50, 20 + 1}, {20, 50 + 1}, {17, 60 + 1},
171 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("200 50 20 17");
173 static IIO_CONST_ATTR(in_capacitance_scale_available,
174 "0.000061050 0.000030525 0.000015263 0.000007631");
176 static struct attribute *ad7152_attributes[] = {
177 &iio_dev_attr_in_capacitance0_calibbias_calibration.dev_attr.attr,
178 &iio_dev_attr_in_capacitance1_calibbias_calibration.dev_attr.attr,
179 &iio_dev_attr_in_capacitance0_calibscale_calibration.dev_attr.attr,
180 &iio_dev_attr_in_capacitance1_calibscale_calibration.dev_attr.attr,
181 &iio_const_attr_in_capacitance_scale_available.dev_attr.attr,
182 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
186 static const struct attribute_group ad7152_attribute_group = {
187 .attrs = ad7152_attributes,
190 static const u8 ad7152_addresses[][4] = {
191 { AD7152_REG_CH1_DATA_HIGH, AD7152_REG_CH1_OFFS_HIGH,
192 AD7152_REG_CH1_GAIN_HIGH, AD7152_REG_CH1_SETUP },
193 { AD7152_REG_CH2_DATA_HIGH, AD7152_REG_CH2_OFFS_HIGH,
194 AD7152_REG_CH2_GAIN_HIGH, AD7152_REG_CH2_SETUP },
197 /* Values are nano relative to pf base. */
198 static const int ad7152_scale_table[] = {
199 30525, 7631, 15263, 61050
203 * read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
207 static int ad7152_read_raw_samp_freq(struct device *dev, int *val)
209 struct ad7152_chip_info *chip = iio_priv(dev_to_iio_dev(dev));
211 *val = ad7152_filter_rate_table[chip->filter_rate_setup][0];
217 * write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
221 static int ad7152_write_raw_samp_freq(struct device *dev, int val)
223 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
224 struct ad7152_chip_info *chip = iio_priv(indio_dev);
227 for (i = 0; i < ARRAY_SIZE(ad7152_filter_rate_table); i++)
228 if (val >= ad7152_filter_rate_table[i][0])
231 if (i >= ARRAY_SIZE(ad7152_filter_rate_table))
232 i = ARRAY_SIZE(ad7152_filter_rate_table) - 1;
234 mutex_lock(&chip->state_lock);
235 ret = i2c_smbus_write_byte_data(chip->client,
236 AD7152_REG_CFG2, AD7152_CFG2_OSR(i));
238 mutex_unlock(&chip->state_lock);
242 chip->filter_rate_setup = i;
243 mutex_unlock(&chip->state_lock);
248 static int ad7152_write_raw(struct iio_dev *indio_dev,
249 struct iio_chan_spec const *chan,
254 struct ad7152_chip_info *chip = iio_priv(indio_dev);
257 mutex_lock(&chip->state_lock);
260 case IIO_CHAN_INFO_CALIBSCALE:
266 val = (val2 * 1024) / 15625;
268 ret = i2c_smbus_write_word_data(chip->client,
269 ad7152_addresses[chan->channel][AD7152_GAIN],
277 case IIO_CHAN_INFO_CALIBBIAS:
278 if ((val < 0) | (val > 0xFFFF)) {
282 ret = i2c_smbus_write_word_data(chip->client,
283 ad7152_addresses[chan->channel][AD7152_OFFS],
290 case IIO_CHAN_INFO_SCALE:
295 for (i = 0; i < ARRAY_SIZE(ad7152_scale_table); i++)
296 if (val2 == ad7152_scale_table[i])
299 chip->setup[chan->channel] &= ~AD7152_SETUP_RANGE_4pF;
300 chip->setup[chan->channel] |= AD7152_SETUP_RANGE(i);
302 ret = i2c_smbus_write_byte_data(chip->client,
303 ad7152_addresses[chan->channel][AD7152_SETUP],
304 chip->setup[chan->channel]);
310 case IIO_CHAN_INFO_SAMP_FREQ:
315 ret = ad7152_write_raw_samp_freq(&indio_dev->dev, val);
326 mutex_unlock(&chip->state_lock);
330 static int ad7152_read_raw(struct iio_dev *indio_dev,
331 struct iio_chan_spec const *chan,
335 struct ad7152_chip_info *chip = iio_priv(indio_dev);
339 mutex_lock(&chip->state_lock);
342 case IIO_CHAN_INFO_RAW:
343 /* First set whether in differential mode */
345 regval = chip->setup[chan->channel];
347 if (chan->differential)
348 chip->setup[chan->channel] |= AD7152_SETUP_CAPDIFF;
350 chip->setup[chan->channel] &= ~AD7152_SETUP_CAPDIFF;
352 if (regval != chip->setup[chan->channel]) {
353 ret = i2c_smbus_write_byte_data(chip->client,
354 ad7152_addresses[chan->channel][AD7152_SETUP],
355 chip->setup[chan->channel]);
359 /* Make sure the channel is enabled */
360 if (chan->channel == 0)
361 regval = AD7152_CONF_CH1EN;
363 regval = AD7152_CONF_CH2EN;
365 /* Trigger a single read */
366 regval |= AD7152_CONF_MODE_SINGLE_CONV;
367 ret = i2c_smbus_write_byte_data(chip->client, AD7152_REG_CFG,
372 msleep(ad7152_filter_rate_table[chip->filter_rate_setup][1]);
373 /* Now read the actual register */
374 ret = i2c_smbus_read_word_data(chip->client,
375 ad7152_addresses[chan->channel][AD7152_DATA]);
380 if (chan->differential)
385 case IIO_CHAN_INFO_CALIBSCALE:
387 ret = i2c_smbus_read_word_data(chip->client,
388 ad7152_addresses[chan->channel][AD7152_GAIN]);
391 /* 1 + gain_val / 2^16 */
393 *val2 = (15625 * swab16(ret)) / 1024;
395 ret = IIO_VAL_INT_PLUS_MICRO;
397 case IIO_CHAN_INFO_CALIBBIAS:
398 ret = i2c_smbus_read_word_data(chip->client,
399 ad7152_addresses[chan->channel][AD7152_OFFS]);
406 case IIO_CHAN_INFO_SCALE:
407 ret = i2c_smbus_read_byte_data(chip->client,
408 ad7152_addresses[chan->channel][AD7152_SETUP]);
412 *val2 = ad7152_scale_table[ret >> 6];
414 ret = IIO_VAL_INT_PLUS_NANO;
416 case IIO_CHAN_INFO_SAMP_FREQ:
417 ret = ad7152_read_raw_samp_freq(&indio_dev->dev, val);
427 mutex_unlock(&chip->state_lock);
431 static int ad7152_write_raw_get_fmt(struct iio_dev *indio_dev,
432 struct iio_chan_spec const *chan,
436 case IIO_CHAN_INFO_SCALE:
437 return IIO_VAL_INT_PLUS_NANO;
439 return IIO_VAL_INT_PLUS_MICRO;
443 static const struct iio_info ad7152_info = {
444 .attrs = &ad7152_attribute_group,
445 .read_raw = ad7152_read_raw,
446 .write_raw = ad7152_write_raw,
447 .write_raw_get_fmt = ad7152_write_raw_get_fmt,
448 .driver_module = THIS_MODULE,
451 static const struct iio_chan_spec ad7152_channels[] = {
453 .type = IIO_CAPACITANCE,
456 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
457 BIT(IIO_CHAN_INFO_CALIBSCALE) |
458 BIT(IIO_CHAN_INFO_CALIBBIAS) |
459 BIT(IIO_CHAN_INFO_SCALE),
460 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
462 .type = IIO_CAPACITANCE,
467 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
468 BIT(IIO_CHAN_INFO_CALIBSCALE) |
469 BIT(IIO_CHAN_INFO_CALIBBIAS) |
470 BIT(IIO_CHAN_INFO_SCALE),
471 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
473 .type = IIO_CAPACITANCE,
476 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
477 BIT(IIO_CHAN_INFO_CALIBSCALE) |
478 BIT(IIO_CHAN_INFO_CALIBBIAS) |
479 BIT(IIO_CHAN_INFO_SCALE),
480 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
482 .type = IIO_CAPACITANCE,
487 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
488 BIT(IIO_CHAN_INFO_CALIBSCALE) |
489 BIT(IIO_CHAN_INFO_CALIBBIAS) |
490 BIT(IIO_CHAN_INFO_SCALE),
491 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
496 * device probe and remove
499 static int ad7152_probe(struct i2c_client *client,
500 const struct i2c_device_id *id)
503 struct ad7152_chip_info *chip;
504 struct iio_dev *indio_dev;
506 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
509 chip = iio_priv(indio_dev);
510 /* this is only used for device removal purposes */
511 i2c_set_clientdata(client, indio_dev);
513 chip->client = client;
514 mutex_init(&chip->state_lock);
516 /* Establish that the iio_dev is a child of the i2c device */
517 indio_dev->name = id->name;
518 indio_dev->dev.parent = &client->dev;
519 indio_dev->info = &ad7152_info;
520 indio_dev->channels = ad7152_channels;
521 if (id->driver_data == 0)
522 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
524 indio_dev->num_channels = 2;
525 indio_dev->num_channels = ARRAY_SIZE(ad7152_channels);
526 indio_dev->modes = INDIO_DIRECT_MODE;
528 ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev);
532 dev_err(&client->dev, "%s capacitive sensor registered\n", id->name);
537 static const struct i2c_device_id ad7152_id[] = {
543 MODULE_DEVICE_TABLE(i2c, ad7152_id);
545 static struct i2c_driver ad7152_driver = {
547 .name = KBUILD_MODNAME,
549 .probe = ad7152_probe,
550 .id_table = ad7152_id,
552 module_i2c_driver(ad7152_driver);
554 MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
555 MODULE_DESCRIPTION("Analog Devices AD7152/3 capacitive sensor driver");
556 MODULE_LICENSE("GPL v2");