2 * AD5933 AD5934 Impedance Converter, Network Analyzer
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/sysfs.h>
13 #include <linux/i2c.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <asm/div64.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/kfifo_buf.h>
29 /* AD5933/AD5934 Registers */
30 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
31 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
32 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
33 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
34 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
35 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
36 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
37 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
38 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
39 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
41 /* AD5933_REG_CONTROL_HB Bits */
42 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43 #define AD5933_CTRL_START_SWEEP (0x2 << 4)
44 #define AD5933_CTRL_INC_FREQ (0x3 << 4)
45 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47 #define AD5933_CTRL_POWER_DOWN (0xA << 4)
48 #define AD5933_CTRL_STANDBY (0xB << 4)
50 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54 #define AD5933_CTRL_RANGE(x) ((x) << 1)
56 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
59 /* AD5933_REG_CONTROL_LB Bits */
60 #define AD5933_CTRL_RESET (0x1 << 4)
61 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
64 /* AD5933_REG_STATUS Bits */
65 #define AD5933_STAT_TEMP_VALID (0x1 << 0)
66 #define AD5933_STAT_DATA_VALID (0x1 << 1)
67 #define AD5933_STAT_SWEEP_DONE (0x1 << 2)
69 /* I2C Block Commands */
70 #define AD5933_I2C_BLOCK_WRITE 0xA0
71 #define AD5933_I2C_BLOCK_READ 0xA1
72 #define AD5933_I2C_ADDR_POINTER 0xB0
75 #define AD5933_INT_OSC_FREQ_Hz 16776000
76 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77 #define AD5933_MAX_RETRIES 100
79 #define AD5933_OUT_RANGE 1
80 #define AD5933_OUT_RANGE_AVAIL 2
81 #define AD5933_OUT_SETTLING_CYCLES 3
82 #define AD5933_IN_PGA_GAIN 4
83 #define AD5933_IN_PGA_GAIN_AVAIL 5
84 #define AD5933_FREQ_POINTS 6
86 #define AD5933_POLL_TIME_ms 10
87 #define AD5933_INIT_EXCITATION_TIME_ms 100
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
104 unsigned poll_time_jiffies;
107 static struct ad5933_platform_data ad5933_default_pdata = {
111 static const struct iio_chan_spec ad5933_channels[] = {
116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
117 .address = AD5933_REG_TEMP_DATA,
123 }, { /* Ring Channels */
127 .extend_name = "real_raw",
128 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
129 BIT(IIO_CHAN_INFO_SCALE),
130 .address = AD5933_REG_REAL_DATA,
141 .extend_name = "imag_raw",
142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
143 BIT(IIO_CHAN_INFO_SCALE),
144 .address = AD5933_REG_IMAG_DATA,
154 static int ad5933_i2c_write(struct i2c_client *client,
155 u8 reg, u8 len, u8 *data)
160 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
162 dev_err(&client->dev, "I2C write error\n");
169 static int ad5933_i2c_read(struct i2c_client *client,
170 u8 reg, u8 len, u8 *data)
175 ret = i2c_smbus_read_byte_data(client, reg++);
177 dev_err(&client->dev, "I2C read error\n");
185 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
187 unsigned char dat = st->ctrl_hb | cmd;
189 return ad5933_i2c_write(st->client,
190 AD5933_REG_CONTROL_HB, 1, &dat);
193 static int ad5933_reset(struct ad5933_state *st)
195 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
196 return ad5933_i2c_write(st->client,
197 AD5933_REG_CONTROL_LB, 1, &dat);
200 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
202 unsigned char val, timeout = AD5933_MAX_RETRIES;
206 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
218 static int ad5933_set_freq(struct ad5933_state *st,
219 unsigned reg, unsigned long freq)
221 unsigned long long freqreg;
227 freqreg = (u64) freq * (u64) (1 << 27);
228 do_div(freqreg, st->mclk_hz / 4);
231 case AD5933_REG_FREQ_START:
232 st->freq_start = freq;
234 case AD5933_REG_FREQ_INC:
241 dat.d32 = cpu_to_be32(freqreg);
242 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
245 static int ad5933_setup(struct ad5933_state *st)
250 ret = ad5933_reset(st);
254 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
258 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
262 st->settling_cycles = 10;
263 dat = cpu_to_be16(st->settling_cycles);
265 ret = ad5933_i2c_write(st->client,
266 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
270 st->freq_points = 100;
271 dat = cpu_to_be16(st->freq_points);
273 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
276 static void ad5933_calc_out_ranges(struct ad5933_state *st)
279 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
281 for (i = 0; i < 4; i++)
282 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
287 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
290 static ssize_t ad5933_show_frequency(struct device *dev,
291 struct device_attribute *attr,
294 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
295 struct ad5933_state *st = iio_priv(indio_dev);
296 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
298 unsigned long long freqreg;
304 mutex_lock(&indio_dev->mlock);
305 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
306 mutex_unlock(&indio_dev->mlock);
310 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
312 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
313 do_div(freqreg, 1 << 27);
315 return sprintf(buf, "%d\n", (int) freqreg);
318 static ssize_t ad5933_store_frequency(struct device *dev,
319 struct device_attribute *attr,
323 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
324 struct ad5933_state *st = iio_priv(indio_dev);
325 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
329 ret = kstrtoul(buf, 10, &val);
333 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
336 mutex_lock(&indio_dev->mlock);
337 ret = ad5933_set_freq(st, this_attr->address, val);
338 mutex_unlock(&indio_dev->mlock);
340 return ret ? ret : len;
343 static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
344 ad5933_show_frequency,
345 ad5933_store_frequency,
346 AD5933_REG_FREQ_START);
348 static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
349 ad5933_show_frequency,
350 ad5933_store_frequency,
351 AD5933_REG_FREQ_INC);
353 static ssize_t ad5933_show(struct device *dev,
354 struct device_attribute *attr,
357 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
358 struct ad5933_state *st = iio_priv(indio_dev);
359 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
360 int ret = 0, len = 0;
362 mutex_lock(&indio_dev->mlock);
363 switch ((u32) this_attr->address) {
364 case AD5933_OUT_RANGE:
365 len = sprintf(buf, "%d\n",
366 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
368 case AD5933_OUT_RANGE_AVAIL:
369 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
370 st->range_avail[3], st->range_avail[2],
373 case AD5933_OUT_SETTLING_CYCLES:
374 len = sprintf(buf, "%d\n", st->settling_cycles);
376 case AD5933_IN_PGA_GAIN:
377 len = sprintf(buf, "%s\n",
378 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
381 case AD5933_IN_PGA_GAIN_AVAIL:
382 len = sprintf(buf, "1 0.2\n");
384 case AD5933_FREQ_POINTS:
385 len = sprintf(buf, "%d\n", st->freq_points);
391 mutex_unlock(&indio_dev->mlock);
392 return ret ? ret : len;
395 static ssize_t ad5933_store(struct device *dev,
396 struct device_attribute *attr,
400 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
401 struct ad5933_state *st = iio_priv(indio_dev);
402 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
407 if (this_attr->address != AD5933_IN_PGA_GAIN) {
408 ret = kstrtou16(buf, 10, &val);
413 mutex_lock(&indio_dev->mlock);
414 switch ((u32) this_attr->address) {
415 case AD5933_OUT_RANGE:
416 for (i = 0; i < 4; i++)
417 if (val == st->range_avail[i]) {
418 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
419 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
420 ret = ad5933_cmd(st, 0);
425 case AD5933_IN_PGA_GAIN:
426 if (sysfs_streq(buf, "1")) {
427 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
428 } else if (sysfs_streq(buf, "0.2")) {
429 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
434 ret = ad5933_cmd(st, 0);
436 case AD5933_OUT_SETTLING_CYCLES:
437 val = clamp(val, (u16)0, (u16)0x7FF);
438 st->settling_cycles = val;
440 /* 2x, 4x handling, see datasheet */
442 val = (val >> 1) | (1 << 9);
444 val = (val >> 2) | (3 << 9);
446 dat = cpu_to_be16(val);
447 ret = ad5933_i2c_write(st->client,
448 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
450 case AD5933_FREQ_POINTS:
451 val = clamp(val, (u16)0, (u16)511);
452 st->freq_points = val;
454 dat = cpu_to_be16(val);
455 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
462 mutex_unlock(&indio_dev->mlock);
463 return ret ? ret : len;
466 static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
471 static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
474 AD5933_OUT_RANGE_AVAIL);
476 static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
481 static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
484 AD5933_IN_PGA_GAIN_AVAIL);
486 static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
491 static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
494 AD5933_OUT_SETTLING_CYCLES);
497 * ideally we would handle the scale attributes via the iio_info
498 * (read|write)_raw methods, however this part is a untypical since we
499 * don't create dedicated sysfs channel attributes for out0 and in0.
501 static struct attribute *ad5933_attributes[] = {
502 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
503 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
504 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
505 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
506 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
507 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
508 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
509 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
513 static const struct attribute_group ad5933_attribute_group = {
514 .attrs = ad5933_attributes,
517 static int ad5933_read_raw(struct iio_dev *indio_dev,
518 struct iio_chan_spec const *chan,
523 struct ad5933_state *st = iio_priv(indio_dev);
527 mutex_lock(&indio_dev->mlock);
529 case IIO_CHAN_INFO_RAW:
530 case IIO_CHAN_INFO_PROCESSED:
531 if (iio_buffer_enabled(indio_dev)) {
535 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
538 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
542 ret = ad5933_i2c_read(st->client,
543 AD5933_REG_TEMP_DATA, 2,
547 mutex_unlock(&indio_dev->mlock);
548 ret = be16_to_cpu(dat);
549 /* Temp in Milli degrees Celsius */
551 *val = ret * 1000 / 32;
553 *val = (ret - 16384) * 1000 / 32;
559 mutex_unlock(&indio_dev->mlock);
563 static const struct iio_info ad5933_info = {
564 .read_raw = &ad5933_read_raw,
565 .attrs = &ad5933_attribute_group,
566 .driver_module = THIS_MODULE,
569 static int ad5933_ring_preenable(struct iio_dev *indio_dev)
571 struct ad5933_state *st = iio_priv(indio_dev);
574 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
577 ret = ad5933_reset(st);
581 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
585 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
589 st->state = AD5933_CTRL_INIT_START_FREQ;
594 static int ad5933_ring_postenable(struct iio_dev *indio_dev)
596 struct ad5933_state *st = iio_priv(indio_dev);
598 /* AD5933_CTRL_INIT_START_FREQ:
599 * High Q complex circuits require a long time to reach steady state.
600 * To facilitate the measurement of such impedances, this mode allows
601 * the user full control of the settling time requirement before
602 * entering start frequency sweep mode where the impedance measurement
603 * takes place. In this mode the impedance is excited with the
604 * programmed start frequency (ad5933_ring_preenable),
605 * but no measurement takes place.
608 schedule_delayed_work(&st->work,
609 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
613 static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
615 struct ad5933_state *st = iio_priv(indio_dev);
617 cancel_delayed_work_sync(&st->work);
618 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
621 static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
622 .preenable = &ad5933_ring_preenable,
623 .postenable = &ad5933_ring_postenable,
624 .postdisable = &ad5933_ring_postdisable,
627 static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
629 struct iio_buffer *buffer;
631 buffer = iio_kfifo_allocate(indio_dev);
635 iio_device_attach_buffer(indio_dev, buffer);
637 /* Ring buffer functions - here trigger setup related */
638 indio_dev->setup_ops = &ad5933_ring_setup_ops;
640 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
645 static void ad5933_work(struct work_struct *work)
647 struct ad5933_state *st = container_of(work,
648 struct ad5933_state, work.work);
649 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
651 unsigned char status;
653 mutex_lock(&indio_dev->mlock);
654 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
656 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
657 st->state = AD5933_CTRL_START_SWEEP;
658 schedule_delayed_work(&st->work, st->poll_time_jiffies);
659 mutex_unlock(&indio_dev->mlock);
663 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
665 if (status & AD5933_STAT_DATA_VALID) {
666 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
667 indio_dev->masklength);
668 ad5933_i2c_read(st->client,
669 test_bit(1, indio_dev->active_scan_mask) ?
670 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
671 scan_count * 2, (u8 *)buf);
673 if (scan_count == 2) {
674 buf[0] = be16_to_cpu(buf[0]);
675 buf[1] = be16_to_cpu(buf[1]);
677 buf[0] = be16_to_cpu(buf[0]);
679 iio_push_to_buffers(indio_dev, buf);
681 /* no data available - try again later */
682 schedule_delayed_work(&st->work, st->poll_time_jiffies);
683 mutex_unlock(&indio_dev->mlock);
687 if (status & AD5933_STAT_SWEEP_DONE) {
688 /* last sample received - power down do nothing until
689 * the ring enable is toggled */
690 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
692 /* we just received a valid datum, move on to the next */
693 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
694 schedule_delayed_work(&st->work, st->poll_time_jiffies);
697 mutex_unlock(&indio_dev->mlock);
700 static int ad5933_probe(struct i2c_client *client,
701 const struct i2c_device_id *id)
703 int ret, voltage_uv = 0;
704 struct ad5933_platform_data *pdata = client->dev.platform_data;
705 struct ad5933_state *st;
706 struct iio_dev *indio_dev;
708 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
709 if (indio_dev == NULL)
712 st = iio_priv(indio_dev);
713 i2c_set_clientdata(client, indio_dev);
717 st->pdata = &ad5933_default_pdata;
721 st->reg = devm_regulator_get(&client->dev, "vcc");
722 if (!IS_ERR(st->reg)) {
723 ret = regulator_enable(st->reg);
726 voltage_uv = regulator_get_voltage(st->reg);
730 st->vref_mv = voltage_uv / 1000;
732 st->vref_mv = st->pdata->vref_mv;
734 if (st->pdata->ext_clk_Hz) {
735 st->mclk_hz = st->pdata->ext_clk_Hz;
736 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
738 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
739 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
742 ad5933_calc_out_ranges(st);
743 INIT_DELAYED_WORK(&st->work, ad5933_work);
744 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
746 indio_dev->dev.parent = &client->dev;
747 indio_dev->info = &ad5933_info;
748 indio_dev->name = id->name;
749 indio_dev->modes = INDIO_DIRECT_MODE;
750 indio_dev->channels = ad5933_channels;
751 indio_dev->num_channels = 1; /* only register temp0_input */
753 ret = ad5933_register_ring_funcs_and_init(indio_dev);
755 goto error_disable_reg;
757 /* skip temp0_input, register in0_(real|imag)_raw */
758 ret = iio_buffer_register(indio_dev, &ad5933_channels[1], 2);
760 goto error_unreg_ring;
762 /* enable both REAL and IMAG channels by default */
763 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
764 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
766 ret = ad5933_setup(st);
768 goto error_uninitialize_ring;
770 ret = iio_device_register(indio_dev);
772 goto error_uninitialize_ring;
776 error_uninitialize_ring:
777 iio_buffer_unregister(indio_dev);
779 iio_kfifo_free(indio_dev->buffer);
781 if (!IS_ERR(st->reg))
782 regulator_disable(st->reg);
787 static int ad5933_remove(struct i2c_client *client)
789 struct iio_dev *indio_dev = i2c_get_clientdata(client);
790 struct ad5933_state *st = iio_priv(indio_dev);
792 iio_device_unregister(indio_dev);
793 iio_buffer_unregister(indio_dev);
794 iio_kfifo_free(indio_dev->buffer);
795 if (!IS_ERR(st->reg))
796 regulator_disable(st->reg);
801 static const struct i2c_device_id ad5933_id[] = {
807 MODULE_DEVICE_TABLE(i2c, ad5933_id);
809 static struct i2c_driver ad5933_driver = {
813 .probe = ad5933_probe,
814 .remove = ad5933_remove,
815 .id_table = ad5933_id,
817 module_i2c_driver(ad5933_driver);
819 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
820 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
821 MODULE_LICENSE("GPL v2");