2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
15 #include <linux/types.h>
16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h>
28 #define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
31 * Bitfield of Display Interface signal polarities.
33 struct ipu_di_signal_cfg {
34 unsigned datamask_en:1;
35 unsigned interlaced:1;
36 unsigned odd_field_first:1;
38 unsigned clkidle_en:1;
39 unsigned data_pol:1; /* true = inverted */
40 unsigned clk_pol:1; /* true = rising edge */
41 unsigned enable_pol:1;
42 unsigned Hsync_pol:1; /* true = active high */
55 unsigned long pixelclock;
56 #define IPU_DI_CLKMODE_SYNC (1 << 0)
57 #define IPU_DI_CLKMODE_EXT (1 << 1)
58 unsigned long clkflags;
64 enum ipu_color_space {
67 IPUV3_COLORSPACE_UNKNOWN,
72 enum ipu_channel_irq {
75 IPU_IRQ_NFB4EOF = 128,
79 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
80 enum ipu_channel_irq irq);
82 #define IPU_IRQ_DP_SF_START (448 + 2)
83 #define IPU_IRQ_DP_SF_END (448 + 3)
84 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
85 #define IPU_IRQ_DC_FC_0 (448 + 8)
86 #define IPU_IRQ_DC_FC_1 (448 + 9)
87 #define IPU_IRQ_DC_FC_2 (448 + 10)
88 #define IPU_IRQ_DC_FC_3 (448 + 11)
89 #define IPU_IRQ_DC_FC_4 (448 + 12)
90 #define IPU_IRQ_DC_FC_6 (448 + 13)
91 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
92 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
95 * IPU Image DMA Controller (idmac) functions
97 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
98 void ipu_idmac_put(struct ipuv3_channel *);
100 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
101 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
102 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
104 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
106 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
109 * IPU Display Controller (dc) functions
113 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
114 void ipu_dc_put(struct ipu_dc *dc);
115 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
116 u32 pixel_fmt, u32 width);
117 void ipu_dc_enable_channel(struct ipu_dc *dc);
118 void ipu_dc_disable_channel(struct ipu_dc *dc);
121 * IPU Display Interface (di) functions
123 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
124 void ipu_di_put(struct ipu_di *);
125 int ipu_di_disable(struct ipu_di *);
126 int ipu_di_enable(struct ipu_di *);
127 int ipu_di_get_num(struct ipu_di *);
128 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
131 * IPU Display Multi FIFO Controller (dmfc) functions
134 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
135 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
136 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
137 unsigned long bandwidth_mbs, int burstsize);
138 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
139 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
140 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
141 void ipu_dmfc_put(struct dmfc_channel *dmfc);
144 * IPU Display Processor (dp) functions
146 #define IPU_DP_FLOW_SYNC_BG 0
147 #define IPU_DP_FLOW_SYNC_FG 1
148 #define IPU_DP_FLOW_ASYNC0_BG 2
149 #define IPU_DP_FLOW_ASYNC0_FG 3
150 #define IPU_DP_FLOW_ASYNC1_BG 4
151 #define IPU_DP_FLOW_ASYNC1_FG 5
153 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
154 void ipu_dp_put(struct ipu_dp *);
155 int ipu_dp_enable_channel(struct ipu_dp *dp);
156 void ipu_dp_disable_channel(struct ipu_dp *dp);
157 int ipu_dp_setup_channel(struct ipu_dp *dp,
158 enum ipu_color_space in, enum ipu_color_space out);
159 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
160 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
163 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
165 #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
166 #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
167 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
168 #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
169 #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
170 #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
171 #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
173 #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
174 #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
175 #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
176 #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
177 #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
178 #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
179 #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
180 #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
181 #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
182 #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
183 #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
184 #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
185 #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
186 #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
187 #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
188 #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
189 #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
190 #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
191 #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
192 #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
193 #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
194 #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
195 #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
196 #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
197 #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
198 #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
199 #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
200 #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
201 #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
202 #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
203 #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
204 #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
205 #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
206 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
207 #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
208 #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
209 #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
210 #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
211 #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
212 #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
213 #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
214 #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
215 #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
216 #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
217 #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
218 #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
219 #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
220 #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
221 #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
222 #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
224 struct ipu_cpmem_word {
229 struct ipu_ch_param {
230 struct ipu_cpmem_word word[2];
233 void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v);
234 u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs);
235 struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel);
236 void ipu_ch_param_dump(struct ipu_ch_param __iomem *p);
238 static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem *p)
241 void __iomem *base = p;
243 for (i = 0; i < sizeof(*p) / sizeof(u32); i++)
244 writel(0, base + i * sizeof(u32));
247 static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem *p,
248 int bufnum, dma_addr_t buf)
251 ipu_ch_param_write_field(p, IPU_FIELD_EBA1, buf >> 3);
253 ipu_ch_param_write_field(p, IPU_FIELD_EBA0, buf >> 3);
256 static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem *p,
259 ipu_ch_param_write_field(p, IPU_FIELD_FW, xres - 1);
260 ipu_ch_param_write_field(p, IPU_FIELD_FH, yres - 1);
263 static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem *p,
266 ipu_ch_param_write_field(p, IPU_FIELD_SLY, stride - 1);
269 void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel);
272 struct fb_bitfield red;
273 struct fb_bitfield green;
274 struct fb_bitfield blue;
275 struct fb_bitfield transp;
280 struct v4l2_pix_format pix;
281 struct v4l2_rect rect;
285 int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
288 int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *,
289 const struct ipu_rgb *rgb);
291 static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param *p,
294 ipu_ch_param_write_field(p, IPU_FIELD_SO, 1);
295 ipu_ch_param_write_field(p, IPU_FIELD_ILO, stride / 8);
296 ipu_ch_param_write_field(p, IPU_FIELD_SLY, (stride * 2) - 1);
299 void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
300 int stride, int height);
301 void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
303 void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
304 u32 pixel_format, int stride, int u_offset, int v_offset);
305 int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat);
306 int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
307 struct ipu_image *image);
309 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
310 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
312 static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem *p,
315 ipu_ch_param_write_field(p, IPU_FIELD_NPB, burstsize - 1);
318 struct ipu_client_platformdata {
326 #endif /* __DRM_IPU_H__ */