drivers/staging/imx-drm/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/reset.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/list.h>
  28 #include <linux/irq.h>
  29 #include <linux/irqchip/chained_irq.h>
  30 #include <linux/irqdomain.h>
  31 #include <linux/of_device.h>
  32
  33 #include "imx-ipu-v3.h"
  34 #include "ipu-prv.h"
  35
  36 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  37 {
  38         return readl(ipu->cm_reg + offset);
  39 }
  40
  41 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  42 {
  43         writel(value, ipu->cm_reg + offset);
  44 }
  45
  46 static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
  47 {
  48         return readl(ipu->idmac_reg + offset);
  49 }
  50
  51 static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
  52                 unsigned offset)
  53 {
  54         writel(value, ipu->idmac_reg + offset);
  55 }
  56
  57 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  58 {
  59         u32 val;
  60
  61         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  62         val |= 0x8;
  63         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  64 }
  65 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  66
  67 struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel)
  68 {
  69         struct ipu_soc *ipu = channel->ipu;
  70
  71         return ipu->cpmem_base + channel->num;
  72 }
  73 EXPORT_SYMBOL_GPL(ipu_get_cpmem);
  74
  75 void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel)
  76 {
  77         struct ipu_soc *ipu = channel->ipu;
  78         struct ipu_ch_param __iomem *p = ipu_get_cpmem(channel);
  79         u32 val;
  80
  81         if (ipu->ipu_type == IPUV3EX)
  82                 ipu_ch_param_write_field(p, IPU_FIELD_ID, 1);
  83
  84         val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(channel->num));
  85         val |= 1 << (channel->num % 32);
  86         ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(channel->num));
  87 };
  88 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
  89
  90 void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v)
  91 {
  92         u32 bit = (wbs >> 8) % 160;
  93         u32 size = wbs & 0xff;
  94         u32 word = (wbs >> 8) / 160;
  95         u32 i = bit / 32;
  96         u32 ofs = bit % 32;
  97         u32 mask = (1 << size) - 1;
  98         u32 val;
  99
 100         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 101
 102         val = readl(&base->word[word].data[i]);
 103         val &= ~(mask << ofs);
 104         val |= v << ofs;
 105         writel(val, &base->word[word].data[i]);
 106
 107         if ((bit + size - 1) / 32 > i) {
 108                 val = readl(&base->word[word].data[i + 1]);
 109                 val &= ~(mask >> (ofs ? (32 - ofs) : 0));
 110                 val |= v >> (ofs ? (32 - ofs) : 0);
 111                 writel(val, &base->word[word].data[i + 1]);
 112         }
 113 }
 114 EXPORT_SYMBOL_GPL(ipu_ch_param_write_field);
 115
 116 u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs)
 117 {
 118         u32 bit = (wbs >> 8) % 160;
 119         u32 size = wbs & 0xff;
 120         u32 word = (wbs >> 8) / 160;
 121         u32 i = bit / 32;
 122         u32 ofs = bit % 32;
 123         u32 mask = (1 << size) - 1;
 124         u32 val = 0;
 125
 126         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 127
 128         val = (readl(&base->word[word].data[i]) >> ofs) & mask;
 129
 130         if ((bit + size - 1) / 32 > i) {
 131                 u32 tmp;
 132                 tmp = readl(&base->word[word].data[i + 1]);
 133                 tmp &= mask >> (ofs ? (32 - ofs) : 0);
 134                 val |= tmp << (ofs ? (32 - ofs) : 0);
 135         }
 136
 137         return val;
 138 }
 139 EXPORT_SYMBOL_GPL(ipu_ch_param_read_field);
 140
 141 int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *p,
 142                 struct ipu_rgb *rgb)
 143 {
 144         int bpp = 0, npb = 0, ro, go, bo, to;
 145
 146         ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
 147         go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
 148         bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
 149         to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
 150
 151         ipu_ch_param_write_field(p, IPU_FIELD_WID0, rgb->red.length - 1);
 152         ipu_ch_param_write_field(p, IPU_FIELD_OFS0, ro);
 153         ipu_ch_param_write_field(p, IPU_FIELD_WID1, rgb->green.length - 1);
 154         ipu_ch_param_write_field(p, IPU_FIELD_OFS1, go);
 155         ipu_ch_param_write_field(p, IPU_FIELD_WID2, rgb->blue.length - 1);
 156         ipu_ch_param_write_field(p, IPU_FIELD_OFS2, bo);
 157
 158         if (rgb->transp.length) {
 159                 ipu_ch_param_write_field(p, IPU_FIELD_WID3,
 160                                 rgb->transp.length - 1);
 161                 ipu_ch_param_write_field(p, IPU_FIELD_OFS3, to);
 162         } else {
 163                 ipu_ch_param_write_field(p, IPU_FIELD_WID3, 7);
 164                 ipu_ch_param_write_field(p, IPU_FIELD_OFS3,
 165                                 rgb->bits_per_pixel);
 166         }
 167
 168         switch (rgb->bits_per_pixel) {
 169         case 32:
 170                 bpp = 0;
 171                 npb = 15;
 172                 break;
 173         case 24:
 174                 bpp = 1;
 175                 npb = 19;
 176                 break;
 177         case 16:
 178                 bpp = 3;
 179                 npb = 31;
 180                 break;
 181         case 8:
 182                 bpp = 5;
 183                 npb = 63;
 184                 break;
 185         default:
 186                 return -EINVAL;
 187         }
 188         ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
 189         ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
 190         ipu_ch_param_write_field(p, IPU_FIELD_PFS, 7); /* rgb mode */
 191
 192         return 0;
 193 }
 194 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
 195
 196 int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
 197                 int width)
 198 {
 199         int bpp = 0, npb = 0;
 200
 201         switch (width) {
 202         case 32:
 203                 bpp = 0;
 204                 npb = 15;
 205                 break;
 206         case 24:
 207                 bpp = 1;
 208                 npb = 19;
 209                 break;
 210         case 16:
 211                 bpp = 3;
 212                 npb = 31;
 213                 break;
 214         case 8:
 215                 bpp = 5;
 216                 npb = 63;
 217                 break;
 218         default:
 219                 return -EINVAL;
 220         }
 221
 222         ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
 223         ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
 224         ipu_ch_param_write_field(p, IPU_FIELD_PFS, 6); /* raw mode */
 225
 226         return 0;
 227 }
 228 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
 229
 230 void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
 231                                    u32 pixel_format)
 232 {
 233         switch (pixel_format) {
 234         case V4L2_PIX_FMT_UYVY:
 235                 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3);    /* bits/pixel */
 236                 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0xA);  /* pix format */
 237                 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31);   /* burst size */
 238                 break;
 239         case V4L2_PIX_FMT_YUYV:
 240                 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3);    /* bits/pixel */
 241                 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0x8);  /* pix format */
 242                 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31);   /* burst size */
 243                 break;
 244         }
 245 }
 246 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
 247
 248 void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
 249                 u32 pixel_format, int stride, int u_offset, int v_offset)
 250 {
 251         switch (pixel_format) {
 252         case V4L2_PIX_FMT_YUV420:
 253                 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
 254                 ipu_ch_param_write_field(p, IPU_FIELD_UBO, u_offset / 8);
 255                 ipu_ch_param_write_field(p, IPU_FIELD_VBO, v_offset / 8);
 256                 break;
 257         case V4L2_PIX_FMT_YVU420:
 258                 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
 259                 ipu_ch_param_write_field(p, IPU_FIELD_UBO, v_offset / 8);
 260                 ipu_ch_param_write_field(p, IPU_FIELD_VBO, u_offset / 8);
 261                 break;
 262         }
 263 }
 264 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
 265
 266 void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
 267                 int stride, int height)
 268 {
 269         int u_offset, v_offset;
 270         int uv_stride = 0;
 271
 272         switch (pixel_format) {
 273         case V4L2_PIX_FMT_YUV420:
 274         case V4L2_PIX_FMT_YVU420:
 275                 uv_stride = stride / 2;
 276                 u_offset = stride * height;
 277                 v_offset = u_offset + (uv_stride * height / 2);
 278                 ipu_cpmem_set_yuv_planar_full(p, pixel_format, stride,
 279                                 u_offset, v_offset);
 280                 break;
 281         }
 282 }
 283 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
 284
 285 static struct ipu_rgb def_rgb_32 = {
 286         .red    = { .offset = 16, .length = 8, },
 287         .green  = { .offset =  8, .length = 8, },
 288         .blue   = { .offset =  0, .length = 8, },
 289         .transp = { .offset = 24, .length = 8, },
 290         .bits_per_pixel = 32,
 291 };
 292
 293 static struct ipu_rgb def_bgr_32 = {
 294         .red    = { .offset = 16, .length = 8, },
 295         .green  = { .offset =  8, .length = 8, },
 296         .blue   = { .offset =  0, .length = 8, },
 297         .transp = { .offset = 24, .length = 8, },
 298         .bits_per_pixel = 32,
 299 };
 300
 301 static struct ipu_rgb def_rgb_24 = {
 302         .red    = { .offset =  0, .length = 8, },
 303         .green  = { .offset =  8, .length = 8, },
 304         .blue   = { .offset = 16, .length = 8, },
 305         .transp = { .offset =  0, .length = 0, },
 306         .bits_per_pixel = 24,
 307 };
 308
 309 static struct ipu_rgb def_bgr_24 = {
 310         .red    = { .offset = 16, .length = 8, },
 311         .green  = { .offset =  8, .length = 8, },
 312         .blue   = { .offset =  0, .length = 8, },
 313         .transp = { .offset =  0, .length = 0, },
 314         .bits_per_pixel = 24,
 315 };
 316
 317 static struct ipu_rgb def_rgb_16 = {
 318         .red    = { .offset = 11, .length = 5, },
 319         .green  = { .offset =  5, .length = 6, },
 320         .blue   = { .offset =  0, .length = 5, },
 321         .transp = { .offset =  0, .length = 0, },
 322         .bits_per_pixel = 16,
 323 };
 324
 325 #define Y_OFFSET(pix, x, y)     ((x) + pix->width * (y))
 326 #define U_OFFSET(pix, x, y)     ((pix->width * pix->height) + \
 327                                         (pix->width * (y) / 4) + (x) / 2)
 328 #define V_OFFSET(pix, x, y)     ((pix->width * pix->height) + \
 329                                         (pix->width * pix->height / 4) + \
 330                                         (pix->width * (y) / 4) + (x) / 2)
 331
 332 int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 pixelformat)
 333 {
 334         switch (pixelformat) {
 335         case V4L2_PIX_FMT_YUV420:
 336         case V4L2_PIX_FMT_YVU420:
 337                 /* pix format */
 338                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 2);
 339                 /* burst size */
 340                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 63);
 341                 break;
 342         case V4L2_PIX_FMT_UYVY:
 343                 /* bits/pixel */
 344                 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
 345                 /* pix format */
 346                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0xA);
 347                 /* burst size */
 348                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
 349                 break;
 350         case V4L2_PIX_FMT_YUYV:
 351                 /* bits/pixel */
 352                 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
 353                 /* pix format */
 354                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0x8);
 355                 /* burst size */
 356                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
 357                 break;
 358         case V4L2_PIX_FMT_RGB32:
 359                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32);
 360                 break;
 361         case V4L2_PIX_FMT_RGB565:
 362                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16);
 363                 break;
 364         case V4L2_PIX_FMT_BGR32:
 365                 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32);
 366                 break;
 367         case V4L2_PIX_FMT_RGB24:
 368                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_24);
 369                 break;
 370         case V4L2_PIX_FMT_BGR24:
 371                 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24);
 372                 break;
 373         default:
 374                 return -EINVAL;
 375         }
 376
 377         return 0;
 378 }
 379 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
 380
 381 int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
 382                 struct ipu_image *image)
 383 {
 384         struct v4l2_pix_format *pix = &image->pix;
 385         int y_offset, u_offset, v_offset;
 386
 387         pr_debug("%s: resolution: %dx%d stride: %d\n",
 388                         __func__, pix->width, pix->height,
 389                         pix->bytesperline);
 390
 391         ipu_cpmem_set_resolution(cpmem, image->rect.width,
 392                         image->rect.height);
 393         ipu_cpmem_set_stride(cpmem, pix->bytesperline);
 394
 395         ipu_cpmem_set_fmt(cpmem, pix->pixelformat);
 396
 397         switch (pix->pixelformat) {
 398         case V4L2_PIX_FMT_YUV420:
 399         case V4L2_PIX_FMT_YVU420:
 400                 y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 401                 u_offset = U_OFFSET(pix, image->rect.left,
 402                                 image->rect.top) - y_offset;
 403                 v_offset = V_OFFSET(pix, image->rect.left,
 404                                 image->rect.top) - y_offset;
 405
 406                 ipu_cpmem_set_yuv_planar_full(cpmem, pix->pixelformat,
 407                                 pix->bytesperline, u_offset, v_offset);
 408                 ipu_cpmem_set_buffer(cpmem, 0, image->phys + y_offset);
 409                 break;
 410         case V4L2_PIX_FMT_UYVY:
 411         case V4L2_PIX_FMT_YUYV:
 412                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 413                                 image->rect.left * 2 +
 414                                 image->rect.top * image->pix.bytesperline);
 415                 break;
 416         case V4L2_PIX_FMT_RGB32:
 417         case V4L2_PIX_FMT_BGR32:
 418                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 419                                 image->rect.left * 4 +
 420                                 image->rect.top * image->pix.bytesperline);
 421                 break;
 422         case V4L2_PIX_FMT_RGB565:
 423                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 424                                 image->rect.left * 2 +
 425                                 image->rect.top * image->pix.bytesperline);
 426                 break;
 427         case V4L2_PIX_FMT_RGB24:
 428         case V4L2_PIX_FMT_BGR24:
 429                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 430                                 image->rect.left * 3 +
 431                                 image->rect.top * image->pix.bytesperline);
 432                 break;
 433         default:
 434                 return -EINVAL;
 435         }
 436
 437         return 0;
 438 }
 439 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
 440
 441 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 442 {
 443         switch (pixelformat) {
 444         case V4L2_PIX_FMT_YUV420:
 445         case V4L2_PIX_FMT_YVU420:
 446         case V4L2_PIX_FMT_UYVY:
 447         case V4L2_PIX_FMT_YUYV:
 448                 return IPUV3_COLORSPACE_YUV;
 449         case V4L2_PIX_FMT_RGB32:
 450         case V4L2_PIX_FMT_BGR32:
 451         case V4L2_PIX_FMT_RGB24:
 452         case V4L2_PIX_FMT_BGR24:
 453         case V4L2_PIX_FMT_RGB565:
 454                 return IPUV3_COLORSPACE_RGB;
 455         default:
 456                 return IPUV3_COLORSPACE_UNKNOWN;
 457         }
 458 }
 459 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 460
 461 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 462 {
 463         struct ipuv3_channel *channel;
 464
 465         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 466
 467         if (num > 63)
 468                 return ERR_PTR(-ENODEV);
 469
 470         mutex_lock(&ipu->channel_lock);
 471
 472         channel = &ipu->channel[num];
 473
 474         if (channel->busy) {
 475                 channel = ERR_PTR(-EBUSY);
 476                 goto out;
 477         }
 478
 479         channel->busy = 1;
 480         channel->num = num;
 481
 482 out:
 483         mutex_unlock(&ipu->channel_lock);
 484
 485         return channel;
 486 }
 487 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 488
 489 void ipu_idmac_put(struct ipuv3_channel *channel)
 490 {
 491         struct ipu_soc *ipu = channel->ipu;
 492
 493         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 494
 495         mutex_lock(&ipu->channel_lock);
 496
 497         channel->busy = 0;
 498
 499         mutex_unlock(&ipu->channel_lock);
 500 }
 501 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 502
 503 #define idma_mask(ch)                   (1 << (ch & 0x1f))
 504
 505 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 506                 bool doublebuffer)
 507 {
 508         struct ipu_soc *ipu = channel->ipu;
 509         unsigned long flags;
 510         u32 reg;
 511
 512         spin_lock_irqsave(&ipu->lock, flags);
 513
 514         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 515         if (doublebuffer)
 516                 reg |= idma_mask(channel->num);
 517         else
 518                 reg &= ~idma_mask(channel->num);
 519         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 520
 521         spin_unlock_irqrestore(&ipu->lock, flags);
 522 }
 523 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 524
 525 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 526 {
 527         unsigned long lock_flags;
 528         u32 val;
 529
 530         spin_lock_irqsave(&ipu->lock, lock_flags);
 531
 532         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 533
 534         if (mask & IPU_CONF_DI0_EN)
 535                 val |= IPU_DI0_COUNTER_RELEASE;
 536         if (mask & IPU_CONF_DI1_EN)
 537                 val |= IPU_DI1_COUNTER_RELEASE;
 538
 539         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 540
 541         val = ipu_cm_read(ipu, IPU_CONF);
 542         val |= mask;
 543         ipu_cm_write(ipu, val, IPU_CONF);
 544
 545         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 546
 547         return 0;
 548 }
 549 EXPORT_SYMBOL_GPL(ipu_module_enable);
 550
 551 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 552 {
 553         unsigned long lock_flags;
 554         u32 val;
 555
 556         spin_lock_irqsave(&ipu->lock, lock_flags);
 557
 558         val = ipu_cm_read(ipu, IPU_CONF);
 559         val &= ~mask;
 560         ipu_cm_write(ipu, val, IPU_CONF);
 561
 562         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 563
 564         if (mask & IPU_CONF_DI0_EN)
 565                 val &= ~IPU_DI0_COUNTER_RELEASE;
 566         if (mask & IPU_CONF_DI1_EN)
 567                 val &= ~IPU_DI1_COUNTER_RELEASE;
 568
 569         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 570
 571         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 572
 573         return 0;
 574 }
 575 EXPORT_SYMBOL_GPL(ipu_module_disable);
 576
 577 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 578 {
 579         struct ipu_soc *ipu = channel->ipu;
 580         unsigned int chno = channel->num;
 581         unsigned long flags;
 582
 583         spin_lock_irqsave(&ipu->lock, flags);
 584
 585         /* Mark buffer as ready. */
 586         if (buf_num == 0)
 587                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 588         else
 589                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 590
 591         spin_unlock_irqrestore(&ipu->lock, flags);
 592 }
 593 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 594
 595 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 596 {
 597         struct ipu_soc *ipu = channel->ipu;
 598         u32 val;
 599         unsigned long flags;
 600
 601         spin_lock_irqsave(&ipu->lock, flags);
 602
 603         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 604         val |= idma_mask(channel->num);
 605         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 606
 607         spin_unlock_irqrestore(&ipu->lock, flags);
 608
 609         return 0;
 610 }
 611 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 612
 613 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 614 {
 615         struct ipu_soc *ipu = channel->ipu;
 616         u32 val;
 617         unsigned long flags;
 618         unsigned long timeout;
 619
 620         timeout = jiffies + msecs_to_jiffies(50);
 621         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 622                         idma_mask(channel->num)) {
 623                 if (time_after(jiffies, timeout)) {
 624                         dev_warn(ipu->dev, "disabling busy idmac channel %d\n",
 625                                         channel->num);
 626                         break;
 627                 }
 628                 cpu_relax();
 629         }
 630
 631         spin_lock_irqsave(&ipu->lock, flags);
 632
 633         /* Disable DMA channel(s) */
 634         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 635         val &= ~idma_mask(channel->num);
 636         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 637
 638         /* Set channel buffers NOT to be ready */
 639         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 640
 641         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 642                         idma_mask(channel->num)) {
 643                 ipu_cm_write(ipu, idma_mask(channel->num),
 644                              IPU_CHA_BUF0_RDY(channel->num));
 645         }
 646
 647         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 648                         idma_mask(channel->num)) {
 649                 ipu_cm_write(ipu, idma_mask(channel->num),
 650                              IPU_CHA_BUF1_RDY(channel->num));
 651         }
 652
 653         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 654
 655         /* Reset the double buffer */
 656         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 657         val &= ~idma_mask(channel->num);
 658         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 659
 660         spin_unlock_irqrestore(&ipu->lock, flags);
 661
 662         return 0;
 663 }
 664 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 665
 666 static int ipu_memory_reset(struct ipu_soc *ipu)
 667 {
 668         unsigned long timeout;
 669
 670         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 671
 672         timeout = jiffies + msecs_to_jiffies(1000);
 673         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 674                 if (time_after(jiffies, timeout))
 675                         return -ETIME;
 676                 cpu_relax();
 677         }
 678
 679         return 0;
 680 }
 681
 682 struct ipu_devtype {
 683         const char *name;
 684         unsigned long cm_ofs;
 685         unsigned long cpmem_ofs;
 686         unsigned long srm_ofs;
 687         unsigned long tpm_ofs;
 688         unsigned long disp0_ofs;
 689         unsigned long disp1_ofs;
 690         unsigned long dc_tmpl_ofs;
 691         unsigned long vdi_ofs;
 692         enum ipuv3_type type;
 693 };
 694
 695 static struct ipu_devtype ipu_type_imx51 = {
 696         .name = "IPUv3EX",
 697         .cm_ofs = 0x1e000000,
 698         .cpmem_ofs = 0x1f000000,
 699         .srm_ofs = 0x1f040000,
 700         .tpm_ofs = 0x1f060000,
 701         .disp0_ofs = 0x1e040000,
 702         .disp1_ofs = 0x1e048000,
 703         .dc_tmpl_ofs = 0x1f080000,
 704         .vdi_ofs = 0x1e068000,
 705         .type = IPUV3EX,
 706 };
 707
 708 static struct ipu_devtype ipu_type_imx53 = {
 709         .name = "IPUv3M",
 710         .cm_ofs = 0x06000000,
 711         .cpmem_ofs = 0x07000000,
 712         .srm_ofs = 0x07040000,
 713         .tpm_ofs = 0x07060000,
 714         .disp0_ofs = 0x06040000,
 715         .disp1_ofs = 0x06048000,
 716         .dc_tmpl_ofs = 0x07080000,
 717         .vdi_ofs = 0x06068000,
 718         .type = IPUV3M,
 719 };
 720
 721 static struct ipu_devtype ipu_type_imx6q = {
 722         .name = "IPUv3H",
 723         .cm_ofs = 0x00200000,
 724         .cpmem_ofs = 0x00300000,
 725         .srm_ofs = 0x00340000,
 726         .tpm_ofs = 0x00360000,
 727         .disp0_ofs = 0x00240000,
 728         .disp1_ofs = 0x00248000,
 729         .dc_tmpl_ofs = 0x00380000,
 730         .vdi_ofs = 0x00268000,
 731         .type = IPUV3H,
 732 };
 733
 734 static const struct of_device_id imx_ipu_dt_ids[] = {
 735         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 736         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 737         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 738         { /* sentinel */ }
 739 };
 740 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 741
 742 static int ipu_submodules_init(struct ipu_soc *ipu,
 743                 struct platform_device *pdev, unsigned long ipu_base,
 744                 struct clk *ipu_clk)
 745 {
 746         char *unit;
 747         int ret;
 748         struct device *dev = &pdev->dev;
 749         const struct ipu_devtype *devtype = ipu->devtype;
 750
 751         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 752                         IPU_CONF_DI0_EN, ipu_clk);
 753         if (ret) {
 754                 unit = "di0";
 755                 goto err_di_0;
 756         }
 757
 758         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 759                         IPU_CONF_DI1_EN, ipu_clk);
 760         if (ret) {
 761                 unit = "di1";
 762                 goto err_di_1;
 763         }
 764
 765         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
 766                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
 767         if (ret) {
 768                 unit = "dc_template";
 769                 goto err_dc;
 770         }
 771
 772         ret = ipu_dmfc_init(ipu, dev, ipu_base +
 773                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
 774         if (ret) {
 775                 unit = "dmfc";
 776                 goto err_dmfc;
 777         }
 778
 779         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
 780         if (ret) {
 781                 unit = "dp";
 782                 goto err_dp;
 783         }
 784
 785         return 0;
 786
 787 err_dp:
 788         ipu_dmfc_exit(ipu);
 789 err_dmfc:
 790         ipu_dc_exit(ipu);
 791 err_dc:
 792         ipu_di_exit(ipu, 1);
 793 err_di_1:
 794         ipu_di_exit(ipu, 0);
 795 err_di_0:
 796         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
 797         return ret;
 798 }
 799
 800 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
 801 {
 802         unsigned long status;
 803         int i, bit, irq;
 804
 805         for (i = 0; i < num_regs; i++) {
 806
 807                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
 808                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
 809
 810                 for_each_set_bit(bit, &status, 32) {
 811                         irq = irq_linear_revmap(ipu->domain, regs[i] * 32 + bit);
 812                         if (irq)
 813                                 generic_handle_irq(irq);
 814                 }
 815         }
 816 }
 817
 818 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 819 {
 820         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 821         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
 822         struct irq_chip *chip = irq_get_chip(irq);
 823
 824         chained_irq_enter(chip, desc);
 825
 826         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 827
 828         chained_irq_exit(chip, desc);
 829 }
 830
 831 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 832 {
 833         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 834         const int int_reg[] = { 4, 5, 8, 9};
 835         struct irq_chip *chip = irq_get_chip(irq);
 836
 837         chained_irq_enter(chip, desc);
 838
 839         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 840
 841         chained_irq_exit(chip, desc);
 842 }
 843
 844 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 845                 enum ipu_channel_irq irq_type)
 846 {
 847         int irq = irq_linear_revmap(ipu->domain, irq_type + channel->num);
 848
 849         if (!irq)
 850                 irq = irq_create_mapping(ipu->domain, irq_type + channel->num);
 851
 852         return irq;
 853 }
 854 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
 855
 856 static void ipu_submodules_exit(struct ipu_soc *ipu)
 857 {
 858         ipu_dp_exit(ipu);
 859         ipu_dmfc_exit(ipu);
 860         ipu_dc_exit(ipu);
 861         ipu_di_exit(ipu, 1);
 862         ipu_di_exit(ipu, 0);
 863 }
 864
 865 static int platform_remove_devices_fn(struct device *dev, void *unused)
 866 {
 867         struct platform_device *pdev = to_platform_device(dev);
 868
 869         platform_device_unregister(pdev);
 870
 871         return 0;
 872 }
 873
 874 static void platform_device_unregister_children(struct platform_device *pdev)
 875 {
 876         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
 877 }
 878
 879 struct ipu_platform_reg {
 880         struct ipu_client_platformdata pdata;
 881         const char *name;
 882 };
 883
 884 static const struct ipu_platform_reg client_reg[] = {
 885         {
 886                 .pdata = {
 887                         .di = 0,
 888                         .dc = 5,
 889                         .dp = IPU_DP_FLOW_SYNC_BG,
 890                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
 891                         .dma[1] = -EINVAL,
 892                 },
 893                 .name = "imx-ipuv3-crtc",
 894         }, {
 895                 .pdata = {
 896                         .di = 1,
 897                         .dc = 1,
 898                         .dp = -EINVAL,
 899                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
 900                         .dma[1] = -EINVAL,
 901                 },
 902                 .name = "imx-ipuv3-crtc",
 903         },
 904 };
 905
 906 static int ipu_client_id;
 907
 908 static int ipu_add_subdevice_pdata(struct device *dev,
 909                 const struct ipu_platform_reg *reg)
 910 {
 911         struct platform_device *pdev;
 912
 913         pdev = platform_device_register_data(dev, reg->name, ipu_client_id++,
 914                         &reg->pdata, sizeof(struct ipu_platform_reg));
 915
 916         return pdev ? 0 : -EINVAL;
 917 }
 918
 919 static int ipu_add_client_devices(struct ipu_soc *ipu)
 920 {
 921         int ret;
 922         int i;
 923
 924         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
 925                 const struct ipu_platform_reg *reg = &client_reg[i];
 926                 ret = ipu_add_subdevice_pdata(ipu->dev, reg);
 927                 if (ret)
 928                         goto err_register;
 929         }
 930
 931         return 0;
 932
 933 err_register:
 934         platform_device_unregister_children(to_platform_device(ipu->dev));
 935
 936         return ret;
 937 }
 938
 939
 940 static int ipu_irq_init(struct ipu_soc *ipu)
 941 {
 942         struct irq_chip_generic *gc;
 943         struct irq_chip_type *ct;
 944         unsigned long unused[IPU_NUM_IRQS / 32] = {
 945                 0x400100d0, 0xffe000fd,
 946                 0x400100d0, 0xffe000fd,
 947                 0x400100d0, 0xffe000fd,
 948                 0x4077ffff, 0xffe7e1fd,
 949                 0x23fffffe, 0x8880fff0,
 950                 0xf98fe7d0, 0xfff81fff,
 951                 0x400100d0, 0xffe000fd,
 952                 0x00000000,
 953         };
 954         int ret, i;
 955
 956         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
 957                                             &irq_generic_chip_ops, ipu);
 958         if (!ipu->domain) {
 959                 dev_err(ipu->dev, "failed to add irq domain\n");
 960                 return -ENODEV;
 961         }
 962
 963         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
 964                                              handle_level_irq, 0, IRQF_VALID, 0);
 965         if (ret < 0) {
 966                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
 967                 irq_domain_remove(ipu->domain);
 968                 return ret;
 969         }
 970
 971         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
 972                 gc = irq_get_domain_generic_chip(ipu->domain, i);
 973                 gc->reg_base = ipu->cm_reg;
 974                 gc->unused = unused[i / 32];
 975                 ct = gc->chip_types;
 976                 ct->chip.irq_ack = irq_gc_ack_set_bit;
 977                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
 978                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
 979                 ct->regs.ack = IPU_INT_STAT(i / 32);
 980                 ct->regs.mask = IPU_INT_CTRL(i / 32);
 981         }
 982
 983         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
 984         irq_set_handler_data(ipu->irq_sync, ipu);
 985         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
 986         irq_set_handler_data(ipu->irq_err, ipu);
 987
 988         return 0;
 989 }
 990
 991 static void ipu_irq_exit(struct ipu_soc *ipu)
 992 {
 993         int i, irq;
 994
 995         irq_set_chained_handler(ipu->irq_err, NULL);
 996         irq_set_handler_data(ipu->irq_err, NULL);
 997         irq_set_chained_handler(ipu->irq_sync, NULL);
 998         irq_set_handler_data(ipu->irq_sync, NULL);
 999
1000         /* TODO: remove irq_domain_generic_chips */
1001
1002         for (i = 0; i < IPU_NUM_IRQS; i++) {
1003                 irq = irq_linear_revmap(ipu->domain, i);
1004                 if (irq)
1005                         irq_dispose_mapping(irq);
1006         }
1007
1008         irq_domain_remove(ipu->domain);
1009 }
1010
1011 static int ipu_probe(struct platform_device *pdev)
1012 {
1013         const struct of_device_id *of_id =
1014                         of_match_device(imx_ipu_dt_ids, &pdev->dev);
1015         struct ipu_soc *ipu;
1016         struct resource *res;
1017         unsigned long ipu_base;
1018         int i, ret, irq_sync, irq_err;
1019         const struct ipu_devtype *devtype;
1020
1021         devtype = of_id->data;
1022
1023         irq_sync = platform_get_irq(pdev, 0);
1024         irq_err = platform_get_irq(pdev, 1);
1025         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026
1027         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1028                         irq_sync, irq_err);
1029
1030         if (!res || irq_sync < 0 || irq_err < 0)
1031                 return -ENODEV;
1032
1033         ipu_base = res->start;
1034
1035         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1036         if (!ipu)
1037                 return -ENODEV;
1038
1039         for (i = 0; i < 64; i++)
1040                 ipu->channel[i].ipu = ipu;
1041         ipu->devtype = devtype;
1042         ipu->ipu_type = devtype->type;
1043
1044         spin_lock_init(&ipu->lock);
1045         mutex_init(&ipu->channel_lock);
1046
1047         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1048                         ipu_base + devtype->cm_ofs);
1049         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1050                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1051         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1052                         ipu_base + devtype->cpmem_ofs);
1053         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1054                         ipu_base + devtype->disp0_ofs);
1055         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1056                         ipu_base + devtype->disp1_ofs);
1057         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1058                         ipu_base + devtype->srm_ofs);
1059         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1060                         ipu_base + devtype->tpm_ofs);
1061         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1062                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1063         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1064                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1065         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1066                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1067         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1068                         ipu_base + devtype->vdi_ofs);
1069
1070         ipu->cm_reg = devm_ioremap(&pdev->dev,
1071                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1072         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1073                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1074                         PAGE_SIZE);
1075         ipu->cpmem_base = devm_ioremap(&pdev->dev,
1076                         ipu_base + devtype->cpmem_ofs, PAGE_SIZE);
1077
1078         if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base)
1079                 return -ENOMEM;
1080
1081         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1082         if (IS_ERR(ipu->clk)) {
1083                 ret = PTR_ERR(ipu->clk);
1084                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1085                 return ret;
1086         }
1087
1088         platform_set_drvdata(pdev, ipu);
1089
1090         ret = clk_prepare_enable(ipu->clk);
1091         if (ret) {
1092                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1093                 return ret;
1094         }
1095
1096         ipu->dev = &pdev->dev;
1097         ipu->irq_sync = irq_sync;
1098         ipu->irq_err = irq_err;
1099
1100         ret = ipu_irq_init(ipu);
1101         if (ret)
1102                 goto out_failed_irq;
1103
1104         ret = device_reset(&pdev->dev);
1105         if (ret) {
1106                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1107                 goto out_failed_reset;
1108         }
1109         ret = ipu_memory_reset(ipu);
1110         if (ret)
1111                 goto out_failed_reset;
1112
1113         /* Set MCU_T to divide MCU access window into 2 */
1114         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1115                         IPU_DISP_GEN);
1116
1117         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1118         if (ret)
1119                 goto failed_submodules_init;
1120
1121         ret = ipu_add_client_devices(ipu);
1122         if (ret) {
1123                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1124                                 ret);
1125                 goto failed_add_clients;
1126         }
1127
1128         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1129
1130         return 0;
1131
1132 failed_add_clients:
1133         ipu_submodules_exit(ipu);
1134 failed_submodules_init:
1135 out_failed_reset:
1136         ipu_irq_exit(ipu);
1137 out_failed_irq:
1138         clk_disable_unprepare(ipu->clk);
1139         return ret;
1140 }
1141
1142 static int ipu_remove(struct platform_device *pdev)
1143 {
1144         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1145
1146         platform_device_unregister_children(pdev);
1147         ipu_submodules_exit(ipu);
1148         ipu_irq_exit(ipu);
1149
1150         clk_disable_unprepare(ipu->clk);
1151
1152         return 0;
1153 }
1154
1155 static struct platform_driver imx_ipu_driver = {
1156         .driver = {
1157                 .name = "imx-ipuv3",
1158                 .of_match_table = imx_ipu_dt_ids,
1159         },
1160         .probe = ipu_probe,
1161         .remove = ipu_remove,
1162 };
1163
1164 module_platform_driver(imx_ipu_driver);
1165
1166 MODULE_ALIAS("platform:imx-ipuv3");
1167 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1168 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1169 MODULE_LICENSE("GPL");