2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 #include <linux/export.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
23 #include "imx-ipu-v3.h"
26 #define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
27 #define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
32 #define DC_EVT_NFIELD 3
34 #define DC_EVT_EOFIELD 5
35 #define DC_EVT_NEW_ADDR 6
36 #define DC_EVT_NEW_CHAN 7
37 #define DC_EVT_NEW_DATA 8
39 #define DC_EVT_NEW_ADDR_W_0 0
40 #define DC_EVT_NEW_ADDR_W_1 1
41 #define DC_EVT_NEW_CHAN_W_0 2
42 #define DC_EVT_NEW_CHAN_W_1 3
43 #define DC_EVT_NEW_DATA_W_0 4
44 #define DC_EVT_NEW_DATA_W_1 5
45 #define DC_EVT_NEW_ADDR_R_0 6
46 #define DC_EVT_NEW_ADDR_R_1 7
47 #define DC_EVT_NEW_CHAN_R_0 8
48 #define DC_EVT_NEW_CHAN_R_1 9
49 #define DC_EVT_NEW_DATA_R_0 10
50 #define DC_EVT_NEW_DATA_R_1 11
52 #define DC_WR_CH_CONF 0x0
53 #define DC_WR_CH_ADDR 0x4
54 #define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
57 #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
58 #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
61 #define WROD(lf) (0x18 | ((lf) << 1))
66 #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
67 #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
69 #define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
70 #define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
71 #define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
72 #define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
73 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
74 #define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
75 #define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
76 #define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
77 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
78 #define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
79 #define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
80 #define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
82 #define IPU_DC_NUM_CHANNELS 10
92 /* The display interface number assigned to this dc channel */
95 struct ipu_dc_priv *priv;
101 void __iomem *dc_reg;
102 void __iomem *dc_tmpl_reg;
105 struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
109 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
113 reg = readl(dc->base + DC_RL_CH(event));
114 reg &= ~(0xffff << (16 * (event & 0x1)));
115 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
116 writel(reg, dc->base + DC_RL_CH(event));
119 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
120 int map, int wave, int glue, int sync)
122 struct ipu_dc_priv *priv = dc->priv;
126 reg = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
127 writel(reg, priv->dc_tmpl_reg + word * 8);
128 reg = operand >> 12 | opcode << 4 | stop << 9;
129 writel(reg, priv->dc_tmpl_reg + word * 8 + 4);
132 static int ipu_pixfmt_to_map(u32 fmt)
135 case V4L2_PIX_FMT_RGB24:
136 return IPU_DC_MAP_RGB24;
137 case V4L2_PIX_FMT_RGB565:
138 return IPU_DC_MAP_RGB565;
144 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
145 u32 pixel_fmt, u32 width)
147 struct ipu_dc_priv *priv = dc->priv;
150 dc->di = ipu_di_get_num(di);
152 map = ipu_pixfmt_to_map(pixel_fmt);
154 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
159 dc_link_event(dc, DC_EVT_NL, 0, 3);
160 dc_link_event(dc, DC_EVT_EOL, 0, 2);
161 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
163 /* Init template microcode */
164 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8);
167 dc_link_event(dc, DC_EVT_NL, 2, 3);
168 dc_link_event(dc, DC_EVT_EOL, 3, 2);
169 dc_link_event(dc, DC_EVT_NEW_DATA, 4, 1);
170 /* Init template microcode */
171 dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5);
172 dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5);
173 dc_write_tmpl(dc, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5);
175 dc_link_event(dc, DC_EVT_NL, 5, 3);
176 dc_link_event(dc, DC_EVT_EOL, 6, 2);
177 dc_link_event(dc, DC_EVT_NEW_DATA, 7, 1);
178 /* Init template microcode */
179 dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5);
180 dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5);
181 dc_write_tmpl(dc, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5);
184 dc_link_event(dc, DC_EVT_NF, 0, 0);
185 dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
186 dc_link_event(dc, DC_EVT_EOF, 0, 0);
187 dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
188 dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
189 dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
191 reg = readl(dc->base + DC_WR_CH_CONF);
193 reg |= DC_WR_CH_CONF_FIELD_MODE;
195 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
196 writel(reg, dc->base + DC_WR_CH_CONF);
198 writel(0x0, dc->base + DC_WR_CH_ADDR);
199 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
201 ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
205 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
207 void ipu_dc_enable_channel(struct ipu_dc *dc)
214 reg = readl(dc->base + DC_WR_CH_CONF);
215 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
216 writel(reg, dc->base + DC_WR_CH_CONF);
218 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
220 void ipu_dc_disable_channel(struct ipu_dc *dc)
222 struct ipu_dc_priv *priv = dc->priv;
224 int irq = 0, timeout = 50;
227 irq = IPU_IRQ_DC_FC_1;
228 else if (dc->chno == 5)
229 irq = IPU_IRQ_DP_SF_END;
233 /* should wait for the interrupt here */
241 /* Wait for DC triple buffer to empty */
242 while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
249 val = readl(dc->base + DC_WR_CH_CONF);
250 val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
251 writel(val, dc->base + DC_WR_CH_CONF);
253 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
255 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
256 int byte_num, int offset, int mask)
258 int ptr = map * 3 + byte_num;
261 reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
262 reg &= ~(0xffff << (16 * (ptr & 0x1)));
263 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
264 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
266 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
267 reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
268 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
269 writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
272 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
274 u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
276 writel(reg & ~(0xffff << (16 * (map & 0x1))),
277 priv->dc_reg + DC_MAP_CONF_PTR(map));
280 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
282 struct ipu_dc_priv *priv = ipu->dc_priv;
285 if (channel >= IPU_DC_NUM_CHANNELS)
286 return ERR_PTR(-ENODEV);
288 dc = &priv->channels[channel];
290 mutex_lock(&priv->mutex);
293 mutex_unlock(&priv->mutex);
294 return ERR_PTR(-EBUSY);
299 mutex_unlock(&priv->mutex);
303 EXPORT_SYMBOL_GPL(ipu_dc_get);
305 void ipu_dc_put(struct ipu_dc *dc)
307 struct ipu_dc_priv *priv = dc->priv;
309 mutex_lock(&priv->mutex);
311 mutex_unlock(&priv->mutex);
313 EXPORT_SYMBOL_GPL(ipu_dc_put);
315 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
316 unsigned long base, unsigned long template_base)
318 struct ipu_dc_priv *priv;
319 static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
320 0x78, 0, 0x94, 0xb4};
323 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
327 mutex_init(&priv->mutex);
331 priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
332 priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
333 if (!priv->dc_reg || !priv->dc_tmpl_reg)
336 for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
337 priv->channels[i].chno = i;
338 priv->channels[i].priv = priv;
339 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
342 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
343 DC_WR_CH_CONF_PROG_DI_ID,
344 priv->channels[1].base + DC_WR_CH_CONF);
345 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
346 priv->channels[5].base + DC_WR_CH_CONF);
348 writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
352 dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
353 base, template_base);
356 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
357 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
358 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
359 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
362 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
363 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
364 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
365 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
370 void ipu_dc_exit(struct ipu_soc *ipu)