drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include "debug.h"
  16 #include "memory_access.h"
  17
  18 #ifndef __INLINE_INPUT_SYSTEM__
  19 #define __INLINE_INPUT_SYSTEM__
  20 #endif
  21 #ifndef __INLINE_IBUF_CTRL__
  22 #define __INLINE_IBUF_CTRL__
  23 #endif
  24 #ifndef __INLINE_CSI_RX__
  25 #define __INLINE_CSI_RX__
  26 #endif
  27 #ifndef __INLINE_PIXELGEN__
  28 #define __INLINE_PIXELGEN__
  29 #endif
  30 #ifndef __INLINE_STREAM2MMIO__
  31 #define __INLINE_STREAM2MMIO__
  32 #endif
  33
  34 #include "ia_css_debug.h"
  35 #include "ia_css_debug_pipe.h"
  36 #include "ia_css_irq.h"
  37 #include "ia_css_stream.h"
  38 #include "ia_css_pipeline.h"
  39 #include "ia_css_isp_param.h"
  40 #include "sh_css_params.h"
  41 #include "ia_css_bufq.h"
  42 #ifdef ISP2401
  43 #include "ia_css_queue.h"
  44 #endif
  45
  46 #include "ia_css_isp_params.h"
  47
  48 #include "system_local.h"
  49 #include "assert_support.h"
  50 #include "print_support.h"
  51 #include "string_support.h"
  52 #ifdef ISP2401
  53 #include "ia_css_system_ctrl.h"
  54 #endif
  55
  56 #include "fifo_monitor.h"
  57
  58 #if !defined(HAS_NO_INPUT_FORMATTER)
  59 #include "input_formatter.h"
  60 #endif
  61 #include "dma.h"
  62 #include "irq.h"
  63 #include "gp_device.h"
  64 #include "sp.h"
  65 #include "isp.h"
  66 #include "type_support.h"
  67 #include "math_support.h" /* CEIL_DIV */
  68 #if defined(HAS_INPUT_FORMATTER_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
  69 #include "input_system.h"       /* input_formatter_reg_load */
  70 #include "gp_device.h"          /* gp_device_reg_load */
  71 #endif
  72 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
  73 #include "ia_css_tagger_common.h"
  74 #endif
  75
  76 #include "sh_css_internal.h"
  77 #if !defined(HAS_NO_INPUT_SYSTEM)
  78 #include "ia_css_isys.h"
  79 #endif
  80 #include "sh_css_sp.h"          /* sh_css_sp_get_debug_state() */
  81
  82 #include "css_trace.h"      /* tracer */
  83
  84 #include "device_access.h"      /* for ia_css_device_load_uint32 */
  85
  86 /* Include all kernel host interfaces for ISP1 */
  87 #include "anr/anr_1.0/ia_css_anr.host.h"
  88 #include "cnr/cnr_1.0/ia_css_cnr.host.h"
  89 #include "csc/csc_1.0/ia_css_csc.host.h"
  90 #include "de/de_1.0/ia_css_de.host.h"
  91 #include "dp/dp_1.0/ia_css_dp.host.h"
  92 #include "bnr/bnr_1.0/ia_css_bnr.host.h"
  93 #include "fpn/fpn_1.0/ia_css_fpn.host.h"
  94 #include "gc/gc_1.0/ia_css_gc.host.h"
  95 #include "ob/ob_1.0/ia_css_ob.host.h"
  96 #include "s3a/s3a_1.0/ia_css_s3a.host.h"
  97 #include "sc/sc_1.0/ia_css_sc.host.h"
  98 #include "tnr/tnr_1.0/ia_css_tnr.host.h"
  99 #include "uds/uds_1.0/ia_css_uds.host.h"
 100 #include "wb/wb_1.0/ia_css_wb.host.h"
 101 #include "ynr/ynr_1.0/ia_css_ynr.host.h"
 102
 103 /* Include additional kernel host interfaces for ISP2 */
 104 #include "aa/aa_2/ia_css_aa2.host.h"
 105 #include "anr/anr_2/ia_css_anr2.host.h"
 106 #include "cnr/cnr_2/ia_css_cnr2.host.h"
 107 #include "de/de_2/ia_css_de2.host.h"
 108 #include "gc/gc_2/ia_css_gc2.host.h"
 109 #include "ynr/ynr_2/ia_css_ynr2.host.h"
 110
 111 /* Global variable to store the dtrace verbosity level */
 112 unsigned int ia_css_debug_trace_level = IA_CSS_DEBUG_WARNING;
 113
 114 /* Assumes that IA_CSS_STREAM_FORMAT_BINARY_8 is last */
 115 #define N_IA_CSS_STREAM_FORMAT (IA_CSS_STREAM_FORMAT_BINARY_8+1)
 116
 117 #define DPG_START "ia_css_debug_pipe_graph_dump_start "
 118 #define DPG_END   " ia_css_debug_pipe_graph_dump_end\n"
 119
 120 #define ENABLE_LINE_MAX_LENGTH (25)
 121
 122 #ifdef ISP2401
 123 #define DBG_EXT_CMD_TRACE_PNTS_DUMP (1 << 8)
 124 #define DBG_EXT_CMD_PUB_CFG_DUMP (1 << 9)
 125 #define DBG_EXT_CMD_GAC_REG_DUMP (1 << 10)
 126 #define DBG_EXT_CMD_GAC_ACB_REG_DUMP (1 << 11)
 127 #define DBG_EXT_CMD_FIFO_DUMP (1 << 12)
 128 #define DBG_EXT_CMD_QUEUE_DUMP (1 << 13)
 129 #define DBG_EXT_CMD_DMA_DUMP (1 << 14)
 130 #define DBG_EXT_CMD_MASK 0xAB0000CD
 131
 132 #endif
 133 /*
 134  * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads
 135  * future rework should fix this and remove the define MAX_THREAD_NUM
 136  */
 137 #define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS)
 138
 139 static struct pipe_graph_class {
 140         bool do_init;
 141         int height;
 142         int width;
 143         int eff_height;
 144         int eff_width;
 145         enum ia_css_stream_format stream_format;
 146 } pg_inst = {true, 0, 0, 0, 0, N_IA_CSS_STREAM_FORMAT};
 147
 148 static const char * const queue_id_to_str[] = {
 149         /* [SH_CSS_QUEUE_A_ID]     =*/ "queue_A",
 150         /* [SH_CSS_QUEUE_B_ID]     =*/ "queue_B",
 151         /* [SH_CSS_QUEUE_C_ID]     =*/ "queue_C",
 152         /* [SH_CSS_QUEUE_D_ID]     =*/ "queue_D",
 153         /* [SH_CSS_QUEUE_E_ID]     =*/ "queue_E",
 154         /* [SH_CSS_QUEUE_F_ID]     =*/ "queue_F",
 155         /* [SH_CSS_QUEUE_G_ID]     =*/ "queue_G",
 156         /* [SH_CSS_QUEUE_H_ID]     =*/ "queue_H"
 157 };
 158
 159 static const char * const pipe_id_to_str[] = {
 160         /* [IA_CSS_PIPE_ID_PREVIEW]   =*/ "preview",
 161         /* [IA_CSS_PIPE_ID_COPY]      =*/ "copy",
 162         /* [IA_CSS_PIPE_ID_VIDEO]     =*/ "video",
 163         /* [IA_CSS_PIPE_ID_CAPTURE]   =*/ "capture",
 164         /* [IA_CSS_PIPE_ID_YUVPP]     =*/ "yuvpp",
 165         /* [IA_CSS_PIPE_ID_ACC]       =*/ "accelerator"
 166 };
 167
 168 static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME+10];
 169 static char ring_buffer[200];
 170
 171 void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...)
 172 {
 173         va_list ap;
 174
 175         va_start(ap, fmt);
 176         ia_css_debug_vdtrace(level, fmt, ap);
 177         va_end(ap);
 178 }
 179
 180 #if !defined(C_RUN) && !defined(HRT_UNSCHED)
 181 static void debug_dump_long_array_formatted(
 182         const sp_ID_t sp_id,
 183         hrt_address stack_sp_addr,
 184         unsigned stack_size)
 185 {
 186         unsigned int i;
 187         uint32_t val;
 188         uint32_t addr = (uint32_t) stack_sp_addr;
 189         uint32_t stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t));
 190
 191         /* When size is not multiple of four, last word is only relevant for
 192          * remaining bytes */
 193         for (i = 0; i < stack_size_words; i++) {
 194                 val = sp_dmem_load_uint32(sp_id, (hrt_address)addr);
 195                 if ((i%8) == 0)
 196                         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
 197
 198                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val);
 199                 addr += sizeof(uint32_t);
 200         }
 201
 202         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n");
 203 }
 204
 205 static void debug_dump_sp_stack_info(
 206         const sp_ID_t sp_id)
 207 {
 208         const struct ia_css_fw_info *fw;
 209         unsigned int HIVE_ADDR_sp_threads_stack;
 210         unsigned int HIVE_ADDR_sp_threads_stack_size;
 211         uint32_t stack_sizes[MAX_THREAD_NUM];
 212         uint32_t stack_sp_addr[MAX_THREAD_NUM];
 213         unsigned int i;
 214
 215         fw = &sh_css_sp_fw;
 216
 217         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id);
 218         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
 219                 "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n",
 220                 fw->info.sp.threads_stack,
 221                 fw->info.sp.threads_stack_size);
 222
 223         HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack;
 224         HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size;
 225
 226         if (fw->info.sp.threads_stack == 0 ||
 227                 fw->info.sp.threads_stack_size == 0)
 228                 return;
 229
 230         (void) HIVE_ADDR_sp_threads_stack;
 231         (void) HIVE_ADDR_sp_threads_stack_size;
 232
 233         sp_dmem_load(sp_id,
 234                 (unsigned int)sp_address_of(sp_threads_stack),
 235                 &stack_sp_addr, sizeof(stack_sp_addr));
 236         sp_dmem_load(sp_id,
 237                 (unsigned int)sp_address_of(sp_threads_stack_size),
 238                 &stack_sizes, sizeof(stack_sizes));
 239
 240         for (i = 0 ; i < MAX_THREAD_NUM; i++) {
 241                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
 242                         "thread: %u stack_addr: 0x%08x stack_size: %u\n",
 243                         i, stack_sp_addr[i], stack_sizes[i]);
 244                 debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i],
 245                         stack_sizes[i]);
 246         }
 247 }
 248
 249 void ia_css_debug_dump_sp_stack_info(void)
 250 {
 251         debug_dump_sp_stack_info(SP0_ID);
 252 }
 253 #else
 254 /* Empty def for crun */
 255 void ia_css_debug_dump_sp_stack_info(void)
 256 {
 257 }
 258 #endif /* #if __HIVECC */
 259
 260
 261 void ia_css_debug_set_dtrace_level(const unsigned int trace_level)
 262 {
 263         ia_css_debug_trace_level = trace_level;
 264         return;
 265 }
 266
 267 unsigned int ia_css_debug_get_dtrace_level(void)
 268 {
 269         return ia_css_debug_trace_level;
 270 }
 271
 272 static const char *debug_stream_format2str(const enum ia_css_stream_format stream_format)
 273 {
 274         switch (stream_format) {
 275         case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY:
 276                 return "yuv420-8-legacy";
 277         case IA_CSS_STREAM_FORMAT_YUV420_8:
 278                 return "yuv420-8";
 279         case IA_CSS_STREAM_FORMAT_YUV420_10:
 280                 return "yuv420-10";
 281         case IA_CSS_STREAM_FORMAT_YUV420_16:
 282                 return "yuv420-16";
 283         case IA_CSS_STREAM_FORMAT_YUV422_8:
 284                 return "yuv422-8";
 285         case IA_CSS_STREAM_FORMAT_YUV422_10:
 286                 return "yuv422-10";
 287         case IA_CSS_STREAM_FORMAT_YUV422_16:
 288                 return "yuv422-16";
 289         case IA_CSS_STREAM_FORMAT_RGB_444:
 290                 return "rgb444";
 291         case IA_CSS_STREAM_FORMAT_RGB_555:
 292                 return "rgb555";
 293         case IA_CSS_STREAM_FORMAT_RGB_565:
 294                 return "rgb565";
 295         case IA_CSS_STREAM_FORMAT_RGB_666:
 296                 return "rgb666";
 297         case IA_CSS_STREAM_FORMAT_RGB_888:
 298                 return "rgb888";
 299         case IA_CSS_STREAM_FORMAT_RAW_6:
 300                 return "raw6";
 301         case IA_CSS_STREAM_FORMAT_RAW_7:
 302                 return "raw7";
 303         case IA_CSS_STREAM_FORMAT_RAW_8:
 304                 return "raw8";
 305         case IA_CSS_STREAM_FORMAT_RAW_10:
 306                 return "raw10";
 307         case IA_CSS_STREAM_FORMAT_RAW_12:
 308                 return "raw12";
 309         case IA_CSS_STREAM_FORMAT_RAW_14:
 310                 return "raw14";
 311         case IA_CSS_STREAM_FORMAT_RAW_16:
 312                 return "raw16";
 313         case IA_CSS_STREAM_FORMAT_BINARY_8:
 314                 return "binary8";
 315         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT1:
 316                 return "generic-short1";
 317         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT2:
 318                 return "generic-short2";
 319         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT3:
 320                 return "generic-short3";
 321         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT4:
 322                 return "generic-short4";
 323         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT5:
 324                 return "generic-short5";
 325         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT6:
 326                 return "generic-short6";
 327         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT7:
 328                 return "generic-short7";
 329         case IA_CSS_STREAM_FORMAT_GENERIC_SHORT8:
 330                 return "generic-short8";
 331         case IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT:
 332                 return "yuv420-8-shift";
 333         case IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT:
 334                 return "yuv420-10-shift";
 335         case IA_CSS_STREAM_FORMAT_EMBEDDED:
 336                 return "embedded-8";
 337         case IA_CSS_STREAM_FORMAT_USER_DEF1:
 338                 return "user-def-8-type-1";
 339         case IA_CSS_STREAM_FORMAT_USER_DEF2:
 340                 return "user-def-8-type-2";
 341         case IA_CSS_STREAM_FORMAT_USER_DEF3:
 342                 return "user-def-8-type-3";
 343         case IA_CSS_STREAM_FORMAT_USER_DEF4:
 344                 return "user-def-8-type-4";
 345         case IA_CSS_STREAM_FORMAT_USER_DEF5:
 346                 return "user-def-8-type-5";
 347         case IA_CSS_STREAM_FORMAT_USER_DEF6:
 348                 return "user-def-8-type-6";
 349         case IA_CSS_STREAM_FORMAT_USER_DEF7:
 350                 return "user-def-8-type-7";
 351         case IA_CSS_STREAM_FORMAT_USER_DEF8:
 352                 return "user-def-8-type-8";
 353
 354         default:
 355                 assert(!"Unknown stream format");
 356                 return "unknown-stream-format";
 357         }
 358 };
 359
 360 static const char *debug_frame_format2str(const enum ia_css_frame_format frame_format)
 361 {
 362         switch (frame_format) {
 363
 364         case IA_CSS_FRAME_FORMAT_NV11:
 365                 return "NV11";
 366         case IA_CSS_FRAME_FORMAT_NV12:
 367                 return "NV12";
 368         case IA_CSS_FRAME_FORMAT_NV12_16:
 369                 return "NV12_16";
 370         case IA_CSS_FRAME_FORMAT_NV12_TILEY:
 371                 return "NV12_TILEY";
 372         case IA_CSS_FRAME_FORMAT_NV16:
 373                 return "NV16";
 374         case IA_CSS_FRAME_FORMAT_NV21:
 375                 return "NV21";
 376         case IA_CSS_FRAME_FORMAT_NV61:
 377                 return "NV61";
 378         case IA_CSS_FRAME_FORMAT_YV12:
 379                 return "YV12";
 380         case IA_CSS_FRAME_FORMAT_YV16:
 381                 return "YV16";
 382         case IA_CSS_FRAME_FORMAT_YUV420:
 383                 return "YUV420";
 384         case IA_CSS_FRAME_FORMAT_YUV420_16:
 385                 return "YUV420_16";
 386         case IA_CSS_FRAME_FORMAT_YUV422:
 387                 return "YUV422";
 388         case IA_CSS_FRAME_FORMAT_YUV422_16:
 389                 return "YUV422_16";
 390         case IA_CSS_FRAME_FORMAT_UYVY:
 391                 return "UYVY";
 392         case IA_CSS_FRAME_FORMAT_YUYV:
 393                 return "YUYV";
 394         case IA_CSS_FRAME_FORMAT_YUV444:
 395                 return "YUV444";
 396         case IA_CSS_FRAME_FORMAT_YUV_LINE:
 397                 return "YUV_LINE";
 398         case IA_CSS_FRAME_FORMAT_RAW:
 399                 return "RAW";
 400         case IA_CSS_FRAME_FORMAT_RGB565:
 401                 return "RGB565";
 402         case IA_CSS_FRAME_FORMAT_PLANAR_RGB888:
 403                 return "PLANAR_RGB888";
 404         case IA_CSS_FRAME_FORMAT_RGBA888:
 405                 return "RGBA888";
 406         case IA_CSS_FRAME_FORMAT_QPLANE6:
 407                 return "QPLANE6";
 408         case IA_CSS_FRAME_FORMAT_BINARY_8:
 409                 return "BINARY_8";
 410         case IA_CSS_FRAME_FORMAT_MIPI:
 411                 return "MIPI";
 412         case IA_CSS_FRAME_FORMAT_RAW_PACKED:
 413                 return "RAW_PACKED";
 414         case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
 415                 return "CSI_MIPI_YUV420_8";
 416         case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
 417                 return "CSI_MIPI_LEGACY_YUV420_8";
 418         case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10:
 419                 return "CSI_MIPI_YUV420_10";
 420
 421         default:
 422                 assert(!"Unknown frame format");
 423                 return "unknown-frame-format";
 424         }
 425 }
 426
 427 static void debug_print_sp_state(const sp_state_t *state, const char *cell)
 428 {
 429         assert(cell != NULL);
 430         assert(state != NULL);
 431
 432         ia_css_debug_dtrace(2, "%s state:\n", cell);
 433         ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
 434         ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
 435                             state->status_register);
 436         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
 437         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
 438         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
 439                             state->is_sleeping);
 440         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
 441                             state->is_stalling);
 442         return;
 443 }
 444
 445 static void debug_print_isp_state(const isp_state_t *state, const char *cell)
 446 {
 447         assert(state != NULL);
 448         assert(cell != NULL);
 449
 450         ia_css_debug_dtrace(2, "%s state:\n", cell);
 451         ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
 452         ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
 453                             state->status_register);
 454         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
 455         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
 456         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
 457                             state->is_sleeping);
 458         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
 459                             state->is_stalling);
 460         return;
 461 }
 462
 463 void ia_css_debug_dump_isp_state(void)
 464 {
 465         isp_state_t state;
 466         isp_stall_t stall;
 467
 468         isp_get_state(ISP0_ID, &state, &stall);
 469
 470         debug_print_isp_state(&state, "ISP");
 471
 472         if (state.is_stalling) {
 473 #if !defined(HAS_NO_INPUT_FORMATTER)
 474                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 475                                     "[0] if_prim_a_FIFO stalled", stall.fifo0);
 476                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 477                                     "[1] if_prim_b_FIFO stalled", stall.fifo1);
 478 #endif
 479                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled",
 480                                     stall.fifo2);
 481 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) || defined(IS_ISP_2500_SYSTEM)
 482
 483                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled",
 484                                     stall.fifo3);
 485 #if !defined(IS_ISP_2500_SYSTEM)
 486                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled",
 487                                     stall.fifo4);
 488                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled",
 489                                     stall.fifo5);
 490 #endif
 491                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled",
 492                                     stall.fifo6);
 493 #else
 494 #error "ia_css_debug: ISP cell must be one of {2400_MAMOIADA,, 2401_MAMOIADA, 2500_SKYCAM}"
 495 #endif
 496                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 497                                     "status & control stalled",
 498                                     stall.stat_ctrl);
 499                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
 500                                     stall.dmem);
 501                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled",
 502                                     stall.vmem);
 503                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled",
 504                                     stall.vamem1);
 505                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled",
 506                                     stall.vamem2);
 507 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA)
 508                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled",
 509                                     stall.vamem3);
 510                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled",
 511                                     stall.hmem);
 512                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled",
 513                                     stall.pmem);
 514 #endif
 515         }
 516         return;
 517 }
 518
 519 void ia_css_debug_dump_sp_state(void)
 520 {
 521         sp_state_t state;
 522         sp_stall_t stall;
 523         sp_get_state(SP0_ID, &state, &stall);
 524         debug_print_sp_state(&state, "SP");
 525         if (state.is_stalling) {
 526 #if defined(HAS_SP_2400) || defined(IS_ISP_2500_SYSTEM)
 527 #if !defined(HAS_NO_INPUT_SYSTEM)
 528                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled",
 529                                     stall.fifo0);
 530                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled",
 531                                     stall.fifo1);
 532 #endif
 533                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 534                                     "str_to_mem_FIFO stalled", stall.fifo2);
 535                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled",
 536                                     stall.fifo3);
 537 #if !defined(HAS_NO_INPUT_FORMATTER)
 538                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 539                                     "if_prim_a_FIFO stalled", stall.fifo4);
 540 #endif
 541                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled",
 542                                     stall.fifo5);
 543                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled",
 544                                     stall.fifo6);
 545 #if !defined(HAS_NO_INPUT_FORMATTER)
 546                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 547                                     "if_prim_b_FIFO stalled", stall.fifo7);
 548 #endif
 549                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled",
 550                                     stall.fifo8);
 551 #if !defined(IS_ISP_2500_SYSTEM)
 552                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled",
 553                                     stall.fifo9);
 554 #endif
 555                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled",
 556                                     stall.fifoa);
 557 #else
 558 #error "ia_css_debug: SP cell must be one of {SP2400, SP2500}"
 559 #endif
 560                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
 561                                     stall.dmem);
 562                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 563                                     "control master stalled",
 564                                     stall.control_master);
 565                 ia_css_debug_dtrace(2, "\t%-32s: %d\n",
 566                                     "i-cache master stalled",
 567                                     stall.icache_master);
 568         }
 569         ia_css_debug_dump_trace();
 570         return;
 571 }
 572
 573 static void debug_print_fifo_channel_state(const fifo_channel_state_t *state,
 574                                            const char *descr)
 575 {
 576         assert(state != NULL);
 577         assert(descr != NULL);
 578
 579         ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr);
 580         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid",
 581                             state->src_valid);
 582         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept",
 583                             state->fifo_accept);
 584         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid",
 585                             state->fifo_valid);
 586         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept",
 587                             state->sink_accept);
 588         return;
 589 }
 590
 591 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2)
 592 void ia_css_debug_dump_pif_a_isp_fifo_state(void)
 593 {
 594         fifo_channel_state_t pif_to_isp, isp_to_pif;
 595         fifo_channel_get_state(FIFO_MONITOR0_ID,
 596                                FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp);
 597         fifo_channel_get_state(FIFO_MONITOR0_ID,
 598                                FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif);
 599         debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP");
 600         debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A");
 601 }
 602
 603 void ia_css_debug_dump_pif_b_isp_fifo_state(void)
 604 {
 605         fifo_channel_state_t pif_to_isp, isp_to_pif;
 606         fifo_channel_get_state(FIFO_MONITOR0_ID,
 607                                FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp);
 608         fifo_channel_get_state(FIFO_MONITOR0_ID,
 609                                FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif);
 610         debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP");
 611         debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B");
 612 }
 613
 614 void ia_css_debug_dump_str2mem_sp_fifo_state(void)
 615 {
 616         fifo_channel_state_t s2m_to_sp, sp_to_s2m;
 617         fifo_channel_get_state(FIFO_MONITOR0_ID,
 618                                FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp);
 619         fifo_channel_get_state(FIFO_MONITOR0_ID,
 620                                FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m);
 621         debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP");
 622         debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory");
 623 }
 624
 625 static void debug_print_if_state(input_formatter_state_t *state, const char *id)
 626 {
 627         unsigned int val;
 628
 629 #if defined(HAS_INPUT_FORMATTER_VERSION_1)
 630         const char *st_reset = (state->reset ? "Active" : "Not active");
 631 #endif
 632         const char *st_vsync_active_low =
 633             (state->vsync_active_low ? "low" : "high");
 634         const char *st_hsync_active_low =
 635             (state->hsync_active_low ? "low" : "high");
 636
 637         const char *fsm_sync_status_str = "unknown";
 638         const char *fsm_crop_status_str = "unknown";
 639         const char *fsm_padding_status_str = "unknown";
 640
 641         int st_stline = state->start_line;
 642         int st_stcol = state->start_column;
 643         int st_crpht = state->cropped_height;
 644         int st_crpwd = state->cropped_width;
 645         int st_verdcm = state->ver_decimation;
 646         int st_hordcm = state->hor_decimation;
 647         int st_ver_deinterleaving = state->ver_deinterleaving;
 648         int st_hor_deinterleaving = state->hor_deinterleaving;
 649         int st_leftpd = state->left_padding;
 650         int st_eoloff = state->eol_offset;
 651         int st_vmstartaddr = state->vmem_start_address;
 652         int st_vmendaddr = state->vmem_end_address;
 653         int st_vmincr = state->vmem_increment;
 654         int st_yuv420 = state->is_yuv420;
 655         int st_allow_fifo_overflow = state->allow_fifo_overflow;
 656         int st_block_fifo_when_no_req = state->block_fifo_when_no_req;
 657
 658         assert(state != NULL);
 659         ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id);
 660
 661         ia_css_debug_dtrace(2, "\tConfiguration:\n");
 662
 663 #if defined(HAS_INPUT_FORMATTER_VERSION_1)
 664         ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "Software reset", st_reset);
 665 #endif
 666         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline);
 667         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol);
 668         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht);
 669         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd);
 670         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm);
 671         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm);
 672         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 673                             "Ver deinterleaving", st_ver_deinterleaving);
 674         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 675                             "Hor deinterleaving", st_hor_deinterleaving);
 676         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd);
 677         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 678                             "EOL offset (bytes)", st_eoloff);
 679         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
 680                             "VMEM start address", st_vmstartaddr);
 681         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
 682                             "VMEM end address", st_vmendaddr);
 683         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
 684                             "VMEM increment", st_vmincr);
 685         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420);
 686         ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
 687                             "Vsync", st_vsync_active_low);
 688         ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
 689                             "Hsync", st_hsync_active_low);
 690         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 691                             "Allow FIFO overflow", st_allow_fifo_overflow);
 692 /* Flag that tells whether the IF gives backpressure on frames */
 693 /*
 694  * FYI, this is only on the frame request (indicate), when the IF has
 695  * synch'd on a frame it will always give back pressure
 696  */
 697         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 698                             "Block when no request", st_block_fifo_when_no_req);
 699
 700 #if defined(HAS_INPUT_FORMATTER_VERSION_2)
 701         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 702                             "IF_BLOCKED_FIFO_NO_REQ_ADDRESS",
 703                             input_formatter_reg_load(INPUT_FORMATTER0_ID,
 704                             HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS)
 705             );
 706
 707         ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State");
 708
 709         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 710                             "_REG_GP_IFMT_input_switch_lut_reg0",
 711                             gp_device_reg_load(GP_DEVICE0_ID,
 712                             _REG_GP_IFMT_input_switch_lut_reg0));
 713
 714         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 715                             "_REG_GP_IFMT_input_switch_lut_reg1",
 716                             gp_device_reg_load(GP_DEVICE0_ID,
 717                                 _REG_GP_IFMT_input_switch_lut_reg1));
 718
 719         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 720                             "_REG_GP_IFMT_input_switch_lut_reg2",
 721                             gp_device_reg_load(GP_DEVICE0_ID,
 722                                 _REG_GP_IFMT_input_switch_lut_reg2));
 723
 724         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 725                             "_REG_GP_IFMT_input_switch_lut_reg3",
 726                             gp_device_reg_load(GP_DEVICE0_ID,
 727                                 _REG_GP_IFMT_input_switch_lut_reg3));
 728
 729         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 730                             "_REG_GP_IFMT_input_switch_lut_reg4",
 731                             gp_device_reg_load(GP_DEVICE0_ID,
 732                                 _REG_GP_IFMT_input_switch_lut_reg4));
 733
 734         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 735                             "_REG_GP_IFMT_input_switch_lut_reg5",
 736                             gp_device_reg_load(GP_DEVICE0_ID,
 737                                 _REG_GP_IFMT_input_switch_lut_reg5));
 738
 739         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 740                             "_REG_GP_IFMT_input_switch_lut_reg6",
 741                             gp_device_reg_load(GP_DEVICE0_ID,
 742                                 _REG_GP_IFMT_input_switch_lut_reg6));
 743
 744         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 745                             "_REG_GP_IFMT_input_switch_lut_reg7",
 746                             gp_device_reg_load(GP_DEVICE0_ID,
 747                                 _REG_GP_IFMT_input_switch_lut_reg7));
 748
 749         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 750                             "_REG_GP_IFMT_input_switch_fsync_lut",
 751                             gp_device_reg_load(GP_DEVICE0_ID,
 752                                 _REG_GP_IFMT_input_switch_fsync_lut));
 753
 754         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 755                             "_REG_GP_IFMT_srst",
 756                             gp_device_reg_load(GP_DEVICE0_ID,
 757                                 _REG_GP_IFMT_srst));
 758
 759         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 760                             "_REG_GP_IFMT_slv_reg_srst",
 761                             gp_device_reg_load(GP_DEVICE0_ID,
 762                                  _REG_GP_IFMT_slv_reg_srst));
 763 #endif
 764
 765         ia_css_debug_dtrace(2, "\tFSM Status:\n");
 766
 767         val = state->fsm_sync_status;
 768
 769         if (val > 7)
 770                 fsm_sync_status_str = "ERROR";
 771
 772         switch (val & 0x7) {
 773         case 0:
 774                 fsm_sync_status_str = "idle";
 775                 break;
 776         case 1:
 777                 fsm_sync_status_str = "request frame";
 778                 break;
 779         case 2:
 780                 fsm_sync_status_str = "request lines";
 781                 break;
 782         case 3:
 783                 fsm_sync_status_str = "request vectors";
 784                 break;
 785         case 4:
 786                 fsm_sync_status_str = "send acknowledge";
 787                 break;
 788         default:
 789                 fsm_sync_status_str = "unknown";
 790                 break;
 791         }
 792
 793         ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
 794                             "FSM Synchronization Status", val,
 795                             fsm_sync_status_str);
 796
 797         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 798                             "FSM Synchronization Counter",
 799                             state->fsm_sync_counter);
 800
 801         val = state->fsm_crop_status;
 802
 803         if (val > 7)
 804                 fsm_crop_status_str = "ERROR";
 805
 806         switch (val & 0x7) {
 807         case 0:
 808                 fsm_crop_status_str = "idle";
 809                 break;
 810         case 1:
 811                 fsm_crop_status_str = "wait line";
 812                 break;
 813         case 2:
 814                 fsm_crop_status_str = "crop line";
 815                 break;
 816         case 3:
 817                 fsm_crop_status_str = "crop pixel";
 818                 break;
 819         case 4:
 820                 fsm_crop_status_str = "pass pixel";
 821                 break;
 822         case 5:
 823                 fsm_crop_status_str = "pass line";
 824                 break;
 825         case 6:
 826                 fsm_crop_status_str = "lost line";
 827                 break;
 828         default:
 829                 fsm_crop_status_str = "unknown";
 830                 break;
 831         }
 832         ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
 833                             "FSM Crop Status", val, fsm_crop_status_str);
 834
 835         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 836                             "FSM Crop Line Counter",
 837                             state->fsm_crop_line_counter);
 838         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 839                             "FSM Crop Pixel Counter",
 840                             state->fsm_crop_pixel_counter);
 841         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 842                             "FSM Deinterleaving idx buffer",
 843                             state->fsm_deinterleaving_index);
 844         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 845                             "FSM H decimation counter",
 846                             state->fsm_dec_h_counter);
 847         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 848                             "FSM V decimation counter",
 849                             state->fsm_dec_v_counter);
 850         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 851                             "FSM block V decimation counter",
 852                             state->fsm_dec_block_v_counter);
 853
 854         val = state->fsm_padding_status;
 855
 856         if (val > 7)
 857                 fsm_padding_status_str = "ERROR";
 858
 859         switch (val & 0x7) {
 860         case 0:
 861                 fsm_padding_status_str = "idle";
 862                 break;
 863         case 1:
 864                 fsm_padding_status_str = "left pad";
 865                 break;
 866         case 2:
 867                 fsm_padding_status_str = "write";
 868                 break;
 869         case 3:
 870                 fsm_padding_status_str = "right pad";
 871                 break;
 872         case 4:
 873                 fsm_padding_status_str = "send end of line";
 874                 break;
 875         default:
 876                 fsm_padding_status_str = "unknown";
 877                 break;
 878         }
 879
 880         ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status",
 881                             val, fsm_padding_status_str);
 882
 883         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
 884                             "FSM Padding element idx counter",
 885                             state->fsm_padding_elem_counter);
 886         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error",
 887                             state->fsm_vector_support_error);
 888         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full",
 889                             state->fsm_vector_buffer_full);
 890         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support",
 891                             state->vector_support);
 892         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost",
 893                             state->sensor_data_lost);
 894         return;
 895 }
 896
 897 static void debug_print_if_bin_state(input_formatter_bin_state_t *state)
 898 {
 899         ia_css_debug_dtrace(2, "Stream-to-memory state:\n");
 900         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset);
 901         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness",
 902                             state->input_endianness);
 903         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness",
 904                             state->output_endianness);
 905         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap);
 906         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch",
 907                             state->block_synch);
 908         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch",
 909                             state->packet_synch);
 910         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync",
 911                             state->readpostwrite_synch);
 912         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc);
 913         ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update",
 914                             state->en_status_update);
 915 }
 916
 917 void ia_css_debug_dump_if_state(void)
 918 {
 919         input_formatter_state_t if_state;
 920         input_formatter_bin_state_t if_bin_state;
 921
 922         input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state);
 923         debug_print_if_state(&if_state, "Primary IF A");
 924         ia_css_debug_dump_pif_a_isp_fifo_state();
 925
 926         input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state);
 927         debug_print_if_state(&if_state, "Primary IF B");
 928         ia_css_debug_dump_pif_b_isp_fifo_state();
 929
 930         input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state);
 931         debug_print_if_bin_state(&if_bin_state);
 932         ia_css_debug_dump_str2mem_sp_fifo_state();
 933 }
 934 #endif
 935
 936 void ia_css_debug_dump_dma_state(void)
 937 {
 938         /* note: the var below is made static as it is quite large;
 939            if it is not static it ends up on the stack which could
 940            cause issues for drivers
 941         */
 942         static dma_state_t state;
 943         int i, ch_id;
 944
 945         const char *fsm_cmd_st_lbl = "FSM Command flag state";
 946         const char *fsm_ctl_st_lbl = "FSM Control flag state";
 947         const char *fsm_ctl_state = NULL;
 948         const char *fsm_ctl_flag = NULL;
 949         const char *fsm_pack_st = NULL;
 950         const char *fsm_read_st = NULL;
 951         const char *fsm_write_st = NULL;
 952         char last_cmd_str[64];
 953
 954         dma_get_state(DMA0_ID, &state);
 955         /* Print header for DMA dump status */
 956         ia_css_debug_dtrace(2, "DMA dump status:\n");
 957
 958         /* Print FSM command flag state */
 959         if (state.fsm_command_idle)
 960                 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE");
 961         if (state.fsm_command_run)
 962                 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN");
 963         if (state.fsm_command_stalling)
 964                 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
 965                                     "STALL");
 966         if (state.fsm_command_error)
 967                 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
 968                                     "ERROR");
 969
 970         /* Print last command along with the channel */
 971         ch_id = state.last_command_channel;
 972
 973         switch (state.last_command) {
 974         case DMA_COMMAND_READ:
 975                 snprintf(last_cmd_str, 64,
 976                          "Read 2D Block [Channel: %d]", ch_id);
 977                 break;
 978         case DMA_COMMAND_WRITE:
 979                 snprintf(last_cmd_str, 64,
 980                          "Write 2D Block [Channel: %d]", ch_id);
 981                 break;
 982         case DMA_COMMAND_SET_CHANNEL:
 983                 snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id);
 984                 break;
 985         case DMA_COMMAND_SET_PARAM:
 986                 snprintf(last_cmd_str, 64,
 987                          "Set Param: %d [Channel: %d]",
 988                          state.last_command_param, ch_id);
 989                 break;
 990         case DMA_COMMAND_READ_SPECIFIC:
 991                 snprintf(last_cmd_str, 64,
 992                          "Read Specific 2D Block [Channel: %d]", ch_id);
 993                 break;
 994         case DMA_COMMAND_WRITE_SPECIFIC:
 995                 snprintf(last_cmd_str, 64,
 996                          "Write Specific 2D Block [Channel: %d]", ch_id);
 997                 break;
 998         case DMA_COMMAND_INIT:
 999                 snprintf(last_cmd_str, 64,
1000                          "Init 2D Block on Device A [Channel: %d]", ch_id);
1001                 break;
1002         case DMA_COMMAND_INIT_SPECIFIC:
1003                 snprintf(last_cmd_str, 64,
1004                          "Init Specific 2D Block [Channel: %d]", ch_id);
1005                 break;
1006         case DMA_COMMAND_RST:
1007                 snprintf(last_cmd_str, 64, "DMA SW Reset");
1008                 break;
1009         case N_DMA_COMMANDS:
1010                 snprintf(last_cmd_str, 64, "UNKNOWN");
1011                 break;
1012         default:
1013                 snprintf(last_cmd_str, 64,
1014                   "unknown [Channel: %d]", ch_id);
1015                 break;
1016         }
1017         ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n",
1018                             "last command received", state.last_command,
1019                             last_cmd_str);
1020
1021         /* Print DMA registers */
1022         ia_css_debug_dtrace(2, "\t%-32s\n",
1023                             "DMA registers, connection group 0");
1024         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command",
1025                             state.current_command);
1026         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A",
1027                             state.current_addr_a);
1028         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B",
1029                             state.current_addr_b);
1030
1031         if (state.fsm_ctrl_idle)
1032                 fsm_ctl_flag = "IDLE";
1033         else if (state.fsm_ctrl_run)
1034                 fsm_ctl_flag = "RUN";
1035         else if (state.fsm_ctrl_stalling)
1036                 fsm_ctl_flag = "STAL";
1037         else if (state.fsm_ctrl_error)
1038                 fsm_ctl_flag = "ERROR";
1039         else
1040                 fsm_ctl_flag = "UNKNOWN";
1041
1042         switch (state.fsm_ctrl_state) {
1043         case DMA_CTRL_STATE_IDLE:
1044                 fsm_ctl_state = "Idle state";
1045                 break;
1046         case DMA_CTRL_STATE_REQ_RCV:
1047                 fsm_ctl_state = "Req Rcv state";
1048                 break;
1049         case DMA_CTRL_STATE_RCV:
1050                 fsm_ctl_state = "Rcv state";
1051                 break;
1052         case DMA_CTRL_STATE_RCV_REQ:
1053                 fsm_ctl_state = "Rcv Req state";
1054                 break;
1055         case DMA_CTRL_STATE_INIT:
1056                 fsm_ctl_state = "Init state";
1057                 break;
1058         case N_DMA_CTRL_STATES:
1059                 fsm_ctl_state = "Unknown";
1060                 break;
1061         }
1062
1063         ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl,
1064                             fsm_ctl_flag, fsm_ctl_state);
1065
1066         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev",
1067                             state.fsm_ctrl_source_dev);
1068         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr",
1069                             state.fsm_ctrl_source_addr);
1070         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride",
1071                             state.fsm_ctrl_source_stride);
1072         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width",
1073                             state.fsm_ctrl_source_width);
1074         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height",
1075                             state.fsm_ctrl_source_height);
1076         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev",
1077                             state.fsm_ctrl_pack_source_dev);
1078         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev",
1079                             state.fsm_ctrl_pack_dest_dev);
1080         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr",
1081                             state.fsm_ctrl_dest_addr);
1082         ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride",
1083                             state.fsm_ctrl_dest_stride);
1084         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width",
1085                             state.fsm_ctrl_pack_source_width);
1086         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height",
1087                             state.fsm_ctrl_pack_dest_height);
1088         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width",
1089                             state.fsm_ctrl_pack_dest_width);
1090         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems",
1091                             state.fsm_ctrl_pack_source_elems);
1092         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems",
1093                             state.fsm_ctrl_pack_dest_elems);
1094         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension",
1095                             state.fsm_ctrl_pack_extension);
1096
1097         if (state.pack_idle)
1098                 fsm_pack_st = "IDLE";
1099         if (state.pack_run)
1100                 fsm_pack_st = "RUN";
1101         if (state.pack_stalling)
1102                 fsm_pack_st = "STALL";
1103         if (state.pack_error)
1104                 fsm_pack_st = "ERROR";
1105
1106         ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state",
1107                             fsm_pack_st);
1108
1109         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height",
1110                             state.pack_cnt_height);
1111         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width",
1112                             state.pack_src_cnt_width);
1113         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width",
1114                             state.pack_dest_cnt_width);
1115
1116         if (state.read_state == DMA_RW_STATE_IDLE)
1117                 fsm_read_st = "Idle state";
1118         if (state.read_state == DMA_RW_STATE_REQ)
1119                 fsm_read_st = "Req state";
1120         if (state.read_state == DMA_RW_STATE_NEXT_LINE)
1121                 fsm_read_st = "Next line";
1122         if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1123                 fsm_read_st = "Unlock channel";
1124
1125         ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state",
1126                             fsm_read_st);
1127
1128         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height",
1129                             state.read_cnt_height);
1130         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width",
1131                             state.read_cnt_width);
1132
1133         if (state.write_state == DMA_RW_STATE_IDLE)
1134                 fsm_write_st = "Idle state";
1135         if (state.write_state == DMA_RW_STATE_REQ)
1136                 fsm_write_st = "Req state";
1137         if (state.write_state == DMA_RW_STATE_NEXT_LINE)
1138                 fsm_write_st = "Next line";
1139         if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL)
1140                 fsm_write_st = "Unlock channel";
1141
1142         ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state",
1143                             fsm_write_st);
1144
1145         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height",
1146                             state.write_height);
1147         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width",
1148                             state.write_width);
1149
1150         for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
1151                 dma_port_state_t *port = &(state.port_states[i]);
1152                 ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i);
1153                 ia_css_debug_dtrace(2, "\t\tDMA internal side state\n");
1154                 ia_css_debug_dtrace(2,
1155                                     "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1156                                     port->req_cs, port->req_we_n, port->req_run,
1157                                     port->req_ack);
1158                 ia_css_debug_dtrace(2, "\t\tMaster Output side state\n");
1159                 ia_css_debug_dtrace(2,
1160                                     "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
1161                                     port->send_cs, port->send_we_n,
1162                                     port->send_run, port->send_ack);
1163                 ia_css_debug_dtrace(2, "\t\tFifo state\n");
1164                 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL)
1165                         ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n");
1166                 else if (port->fifo_state == DMA_FIFO_STATE_FULL)
1167                         ia_css_debug_dtrace(2, "\t\t\tFifo Full\n");
1168                 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY)
1169                         ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n");
1170                 else
1171                         ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n");
1172
1173                 ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n",
1174                                     port->fifo_counter);
1175         }
1176
1177         for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
1178                 dma_channel_state_t *ch = &(state.channel_states[i]);
1179                 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register",
1180                                     i);
1181                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection",
1182                                     ch->connection);
1183                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend",
1184                                     ch->sign_extend);
1185                 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A",
1186                                     ch->stride_a);
1187                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A",
1188                                     ch->elems_a);
1189                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A",
1190                                     ch->cropping_a);
1191                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A",
1192                                     ch->width_a);
1193                 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B",
1194                                     ch->stride_b);
1195                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B",
1196                                     ch->elems_b);
1197                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B",
1198                                     ch->cropping_b);
1199                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B",
1200                                     ch->width_b);
1201                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height);
1202         }
1203         ia_css_debug_dtrace(2, "\n");
1204         return;
1205 }
1206
1207 void ia_css_debug_dump_dma_sp_fifo_state(void)
1208 {
1209         fifo_channel_state_t dma_to_sp, sp_to_dma;
1210         fifo_channel_get_state(FIFO_MONITOR0_ID,
1211                                FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp);
1212         fifo_channel_get_state(FIFO_MONITOR0_ID,
1213                                FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma);
1214         debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP");
1215         debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA");
1216         return;
1217 }
1218
1219 void ia_css_debug_dump_dma_isp_fifo_state(void)
1220 {
1221         fifo_channel_state_t dma_to_isp, isp_to_dma;
1222         fifo_channel_get_state(FIFO_MONITOR0_ID,
1223                                FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp);
1224         fifo_channel_get_state(FIFO_MONITOR0_ID,
1225                                FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma);
1226         debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP");
1227         debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA");
1228         return;
1229 }
1230
1231 void ia_css_debug_dump_isp_sp_fifo_state(void)
1232 {
1233         fifo_channel_state_t sp_to_isp, isp_to_sp;
1234         fifo_channel_get_state(FIFO_MONITOR0_ID,
1235                                FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp);
1236         fifo_channel_get_state(FIFO_MONITOR0_ID,
1237                                FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp);
1238         debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP");
1239         debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP");
1240         return;
1241 }
1242
1243 void ia_css_debug_dump_isp_gdc_fifo_state(void)
1244 {
1245         fifo_channel_state_t gdc_to_isp, isp_to_gdc;
1246
1247         fifo_channel_get_state(FIFO_MONITOR0_ID,
1248                                FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp);
1249         fifo_channel_get_state(FIFO_MONITOR0_ID,
1250                                FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc);
1251         debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP");
1252         debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC");
1253         return;
1254 }
1255
1256 void ia_css_debug_dump_all_fifo_state(void)
1257 {
1258         int i;
1259         fifo_monitor_state_t state;
1260         fifo_monitor_get_state(FIFO_MONITOR0_ID, &state);
1261
1262         for (i = 0; i < N_FIFO_CHANNEL; i++)
1263                 debug_print_fifo_channel_state(&(state.fifo_channels[i]),
1264                                                "squepfstqkt");
1265         return;
1266 }
1267
1268 static void debug_binary_info_print(const struct ia_css_binary_xinfo *info)
1269 {
1270         assert(info != NULL);
1271         ia_css_debug_dtrace(2, "id = %d\n", info->sp.id);
1272         ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode);
1273         ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width);
1274         ia_css_debug_dtrace(2, "min_output_width = %d\n",
1275                             info->sp.output.min_width);
1276         ia_css_debug_dtrace(2, "max_output_width = %d\n",
1277                             info->sp.output.max_width);
1278         ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping);
1279         ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping);
1280         ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr);
1281         ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n",
1282                             info->sp.enable.vf_veceven);
1283         ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis);
1284         ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds);
1285         ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds);
1286         ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem);
1287         return;
1288 }
1289
1290 void ia_css_debug_binary_print(const struct ia_css_binary *bi)
1291 {
1292         unsigned int i;
1293         debug_binary_info_print(bi->info);
1294         ia_css_debug_dtrace(2,
1295                             "input:  %dx%d, format = %d, padded width = %d\n",
1296                             bi->in_frame_info.res.width,
1297                             bi->in_frame_info.res.height,
1298                             bi->in_frame_info.format,
1299                             bi->in_frame_info.padded_width);
1300         ia_css_debug_dtrace(2,
1301                             "internal :%dx%d, format = %d, padded width = %d\n",
1302                             bi->internal_frame_info.res.width,
1303                             bi->internal_frame_info.res.height,
1304                             bi->internal_frame_info.format,
1305                             bi->internal_frame_info.padded_width);
1306         for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
1307                 if (bi->out_frame_info[i].res.width != 0) {
1308                         ia_css_debug_dtrace(2,
1309                                     "out%d:    %dx%d, format = %d, padded width = %d\n",
1310                                         i,
1311                                     bi->out_frame_info[i].res.width,
1312                                     bi->out_frame_info[i].res.height,
1313                                     bi->out_frame_info[i].format,
1314                                     bi->out_frame_info[i].padded_width);
1315                 }
1316         }
1317         ia_css_debug_dtrace(2,
1318                             "vf out: %dx%d, format = %d, padded width = %d\n",
1319                             bi->vf_frame_info.res.width,
1320                             bi->vf_frame_info.res.height,
1321                             bi->vf_frame_info.format,
1322                             bi->vf_frame_info.padded_width);
1323         ia_css_debug_dtrace(2, "online = %d\n", bi->online);
1324         ia_css_debug_dtrace(2, "input_buf_vectors = %d\n",
1325                             bi->input_buf_vectors);
1326         ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2);
1327         ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n",
1328                             bi->vf_downscale_log2);
1329         ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n",
1330                             bi->dis.deci_factor_log2);
1331         ia_css_debug_dtrace(2, "dis hor coef num = %d\n",
1332                             bi->dis.coef.pad.width);
1333         ia_css_debug_dtrace(2, "dis ver coef num = %d\n",
1334                             bi->dis.coef.pad.height);
1335         ia_css_debug_dtrace(2, "dis hor proj num = %d\n",
1336                             bi->dis.proj.pad.height);
1337         ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n",
1338                             bi->sctbl_width_per_color);
1339         ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width);
1340         ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height);
1341         return;
1342 }
1343
1344 void ia_css_debug_frame_print(const struct ia_css_frame *frame,
1345                               const char *descr)
1346 {
1347         char *data = NULL;
1348
1349         assert(frame != NULL);
1350         assert(descr != NULL);
1351
1352         data = (char *)HOST_ADDRESS(frame->data);
1353         ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame);
1354         ia_css_debug_dtrace(2, "  resolution    = %dx%d\n",
1355                             frame->info.res.width, frame->info.res.height);
1356         ia_css_debug_dtrace(2, "  padded width  = %d\n",
1357                             frame->info.padded_width);
1358         ia_css_debug_dtrace(2, "  format        = %d\n", frame->info.format);
1359         ia_css_debug_dtrace(2, "  is contiguous = %s\n",
1360                             frame->contiguous ? "yes" : "no");
1361         switch (frame->info.format) {
1362         case IA_CSS_FRAME_FORMAT_NV12:
1363         case IA_CSS_FRAME_FORMAT_NV16:
1364         case IA_CSS_FRAME_FORMAT_NV21:
1365         case IA_CSS_FRAME_FORMAT_NV61:
1366                 ia_css_debug_dtrace(2, "  Y = %p\n",
1367                                     data + frame->planes.nv.y.offset);
1368                 ia_css_debug_dtrace(2, "  UV = %p\n",
1369                                     data + frame->planes.nv.uv.offset);
1370                 break;
1371         case IA_CSS_FRAME_FORMAT_YUYV:
1372         case IA_CSS_FRAME_FORMAT_UYVY:
1373         case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8:
1374         case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8:
1375         case IA_CSS_FRAME_FORMAT_YUV_LINE:
1376                 ia_css_debug_dtrace(2, "  YUYV = %p\n",
1377                                     data + frame->planes.yuyv.offset);
1378                 break;
1379         case IA_CSS_FRAME_FORMAT_YUV420:
1380         case IA_CSS_FRAME_FORMAT_YUV422:
1381         case IA_CSS_FRAME_FORMAT_YUV444:
1382         case IA_CSS_FRAME_FORMAT_YV12:
1383         case IA_CSS_FRAME_FORMAT_YV16:
1384         case IA_CSS_FRAME_FORMAT_YUV420_16:
1385         case IA_CSS_FRAME_FORMAT_YUV422_16:
1386                 ia_css_debug_dtrace(2, "  Y = %p\n",
1387                                     data + frame->planes.yuv.y.offset);
1388                 ia_css_debug_dtrace(2, "  U = %p\n",
1389                                     data + frame->planes.yuv.u.offset);
1390                 ia_css_debug_dtrace(2, "  V = %p\n",
1391                                     data + frame->planes.yuv.v.offset);
1392                 break;
1393         case IA_CSS_FRAME_FORMAT_RAW_PACKED:
1394                 ia_css_debug_dtrace(2, "  RAW PACKED = %p\n",
1395                                     data + frame->planes.raw.offset);
1396                 break;
1397         case IA_CSS_FRAME_FORMAT_RAW:
1398                 ia_css_debug_dtrace(2, "  RAW = %p\n",
1399                                     data + frame->planes.raw.offset);
1400                 break;
1401         case IA_CSS_FRAME_FORMAT_RGBA888:
1402         case IA_CSS_FRAME_FORMAT_RGB565:
1403                 ia_css_debug_dtrace(2, "  RGB = %p\n",
1404                                     data + frame->planes.rgb.offset);
1405                 break;
1406         case IA_CSS_FRAME_FORMAT_QPLANE6:
1407                 ia_css_debug_dtrace(2, "  R    = %p\n",
1408                                     data + frame->planes.plane6.r.offset);
1409                 ia_css_debug_dtrace(2, "  RatB = %p\n",
1410                                     data + frame->planes.plane6.r_at_b.offset);
1411                 ia_css_debug_dtrace(2, "  Gr   = %p\n",
1412                                     data + frame->planes.plane6.gr.offset);
1413                 ia_css_debug_dtrace(2, "  Gb   = %p\n",
1414                                     data + frame->planes.plane6.gb.offset);
1415                 ia_css_debug_dtrace(2, "  B    = %p\n",
1416                                     data + frame->planes.plane6.b.offset);
1417                 ia_css_debug_dtrace(2, "  BatR = %p\n",
1418                                     data + frame->planes.plane6.b_at_r.offset);
1419                 break;
1420         case IA_CSS_FRAME_FORMAT_BINARY_8:
1421                 ia_css_debug_dtrace(2, "  Binary data = %p\n",
1422                                     data + frame->planes.binary.data.offset);
1423                 break;
1424         default:
1425                 ia_css_debug_dtrace(2, "  unknown frame type\n");
1426                 break;
1427         }
1428         return;
1429 }
1430
1431 #if SP_DEBUG != SP_DEBUG_NONE
1432
1433 void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state
1434                                        *state)
1435 {
1436
1437 #endif
1438
1439 #if SP_DEBUG == SP_DEBUG_DUMP
1440
1441         assert(state != NULL);
1442         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1443                             "current SP software counter: %d\n",
1444                             state->debug[0]);
1445         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1446                             "empty output buffer queue head: 0x%x\n",
1447                             state->debug[1]);
1448         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1449                             "empty output buffer queue tail: 0x%x\n",
1450                             state->debug[2]);
1451         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1452                             "empty s3a buffer queue head: 0x%x\n",
1453                             state->debug[3]);
1454         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1455                             "empty s3a buffer queue tail: 0x%x\n",
1456                             state->debug[4]);
1457         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1458                             "full output buffer queue head: 0x%x\n",
1459                             state->debug[5]);
1460         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1461                             "full output buffer queue tail: 0x%x\n",
1462                             state->debug[6]);
1463         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1464                             "full s3a buffer queue head: 0x%x\n",
1465                             state->debug[7]);
1466         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1467                             "full s3a buffer queue tail: 0x%x\n",
1468                             state->debug[8]);
1469         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n",
1470                             state->debug[9]);
1471         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n",
1472                             state->debug[10]);
1473         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1474                             "num of stages of current pipeline: 0x%x\n",
1475                             state->debug[11]);
1476         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n",
1477                             state->debug[12]);
1478         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n",
1479                             state->debug[13]);
1480         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1481                             "current stage out_vf buffer idx: 0x%x\n",
1482                             state->debug[14]);
1483         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1484                             "current stage output buffer idx: 0x%x\n",
1485                             state->debug[15]);
1486         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1487                             "current stage s3a buffer idx: 0x%x\n",
1488                             state->debug[16]);
1489         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1490                             "first char of current stage name: 0x%x\n",
1491                             state->debug[17]);
1492         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n",
1493                             state->debug[18]);
1494         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1495                             "empty output buffer address 1: 0x%x\n",
1496                             state->debug[19]);
1497         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1498                             "empty output buffer address 2: 0x%x\n",
1499                             state->debug[20]);
1500         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1501                             "empty out_vf buffer address 1: 0x%x\n",
1502                             state->debug[21]);
1503         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1504                             "empty out_vf buffer address 2: 0x%x\n",
1505                             state->debug[22]);
1506         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1507                             "empty s3a_hi buffer address 1: 0x%x\n",
1508                             state->debug[23]);
1509         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1510                             "empty s3a_hi buffer address 2: 0x%x\n",
1511                             state->debug[24]);
1512         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1513                             "empty s3a_lo buffer address 1: 0x%x\n",
1514                             state->debug[25]);
1515         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1516                             "empty s3a_lo buffer address 2: 0x%x\n",
1517                             state->debug[26]);
1518         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1519                             "empty dis_hor buffer address 1: 0x%x\n",
1520                             state->debug[27]);
1521         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1522                             "empty dis_hor buffer address 2: 0x%x\n",
1523                             state->debug[28]);
1524         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1525                             "empty dis_ver buffer address 1: 0x%x\n",
1526                             state->debug[29]);
1527         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1528                             "empty dis_ver buffer address 2: 0x%x\n",
1529                             state->debug[30]);
1530         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1531                             "empty param buffer address: 0x%x\n",
1532                             state->debug[31]);
1533         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1534                             "first incorrect frame address: 0x%x\n",
1535                             state->debug[32]);
1536         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1537                             "first incorrect frame container address: 0x%x\n",
1538                             state->debug[33]);
1539         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1540                             "first incorrect frame container payload: 0x%x\n",
1541                             state->debug[34]);
1542         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1543                             "first incorrect s3a_hi address: 0x%x\n",
1544                             state->debug[35]);
1545         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1546                             "first incorrect s3a_hi container address: 0x%x\n",
1547                             state->debug[36]);
1548         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1549                             "first incorrect s3a_hi container payload: 0x%x\n",
1550                             state->debug[37]);
1551         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1552                             "first incorrect s3a_lo address: 0x%x\n",
1553                             state->debug[38]);
1554         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1555                             "first incorrect s3a_lo container address: 0x%x\n",
1556                             state->debug[39]);
1557         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1558                             "first incorrect s3a_lo container payload: 0x%x\n",
1559                             state->debug[40]);
1560         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1561                             "number of calling flash start function: 0x%x\n",
1562                             state->debug[41]);
1563         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1564                             "number of calling flash close function: 0x%x\n",
1565                             state->debug[42]);
1566         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n",
1567                             state->debug[43]);
1568         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n",
1569                             state->debug[44]);
1570         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1571                             "number of update frame flashed flag: 0x%x\n",
1572                             state->debug[46]);
1573         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1574                             "number of active threads: 0x%x\n",
1575                             state->debug[45]);
1576
1577 #elif SP_DEBUG == SP_DEBUG_COPY
1578
1579         /* Remember last_index because we only want to print new entries */
1580         static int last_index;
1581         int sp_index = state->index;
1582         int n;
1583
1584         assert(state != NULL);
1585         if (sp_index < last_index) {
1586                 /* SP has been reset */
1587                 last_index = 0;
1588         }
1589
1590         if (last_index == 0) {
1591                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1592                                     "copy-trace init: sp_dbg_if_start_line=%d, "
1593                                     "sp_dbg_if_start_column=%d, "
1594                                     "sp_dbg_if_cropped_height=%d, "
1595                                     "sp_debg_if_cropped_width=%d\n",
1596                                     state->if_start_line,
1597                                     state->if_start_column,
1598                                     state->if_cropped_height,
1599                                     state->if_cropped_width);
1600         }
1601
1602         if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) {
1603                 /* last index can be multiple rounds behind */
1604                 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1605                 last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH;
1606         }
1607
1608         for (n = last_index; n < sp_index; n++) {
1609                 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1610                 if (state->trace[i].frame != 0) {
1611                         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1612                                             "copy-trace: frame=%d, line=%d, "
1613                                             "pixel_distance=%d, "
1614                                             "mipi_used_dword=%d, "
1615                                             "sp_index=%d\n",
1616                                             state->trace[i].frame,
1617                                             state->trace[i].line,
1618                                             state->trace[i].pixel_distance,
1619                                             state->trace[i].mipi_used_dword,
1620                                             state->trace[i].sp_index);
1621                 }
1622         }
1623
1624         last_index = sp_index;
1625
1626 #elif SP_DEBUG == SP_DEBUG_TRACE
1627
1628 /**
1629  * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will
1630  * me mapped on the file name string.
1631  *
1632  * Adjust this to your trace case!
1633  */
1634         static char const * const id2filename[8] = {
1635                 "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c",
1636                 "isp_init.sp.c",
1637                 "sp_raw_copy.hive.c",
1638                 "dma_configure.sp.c",
1639                 "sp.hive.c",
1640                 "event_proxy_sp.hive.c",
1641                 "circular_buffer.sp.c",
1642                 "frame_buffer.sp.c"
1643         };
1644
1645 #if 1
1646         /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */
1647         /* Adjust this to your trace case */
1648         static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = {
1649                 "default"
1650         };
1651 #else
1652         /* Example SH_CSS_SP_DBG_NR_OF_TRACES==4 */
1653         /* Adjust this to your trace case */
1654         static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = {
1655                 "copy", "preview/video", "capture", "acceleration"
1656         };
1657 #endif
1658
1659         /* Remember host_index_last because we only want to print new entries */
1660         static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 };
1661         int t, n;
1662
1663         assert(state != NULL);
1664
1665         for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) {
1666                 int sp_index_last = state->index_last[t];
1667
1668                 if (sp_index_last < host_index_last[t]) {
1669                         /* SP has been reset */
1670                         host_index_last[t] = 0;
1671                 }
1672
1673                 if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) <
1674                     sp_index_last) {
1675                         /* last index can be multiple rounds behind */
1676                         /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */
1677                         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1678                                             "Warning: trace %s has gap of %d "
1679                                             "traces\n",
1680                                             trace_name[t],
1681                                             (sp_index_last -
1682                                              (host_index_last[t] +
1683                                               SH_CSS_SP_DBG_TRACE_DEPTH)));
1684
1685                         host_index_last[t] =
1686                             sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH;
1687                 }
1688
1689                 for (n = host_index_last[t]; n < sp_index_last; n++) {
1690                         int i = n % SH_CSS_SP_DBG_TRACE_DEPTH;
1691                         int l = state->trace[t][i].location &
1692                             ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1);
1693                         int fid = state->trace[t][i].location >>
1694                             SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS;
1695                         int ts = state->trace[t][i].time_stamp;
1696
1697                         if (ts) {
1698                                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1699                                                     "%05d trace=%s, file=%s:%d, "
1700                                                     "data=0x%08x\n",
1701                                                     ts,
1702                                                     trace_name[t],
1703                                                     id2filename[fid], l,
1704                                                     state->trace[t][i].data);
1705                         }
1706                 }
1707                 host_index_last[t] = sp_index_last;
1708         }
1709
1710 #elif SP_DEBUG == SP_DEBUG_MINIMAL
1711         int i;
1712         int base = 0;
1713         int limit = SH_CSS_NUM_SP_DEBUG;
1714         int step = 1;
1715
1716         assert(state != NULL);
1717
1718         for (i = base; i < limit; i += step) {
1719                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
1720                                     "sp_dbg_trace[%d] = %d\n",
1721                                     i, state->debug[i]);
1722         }
1723 #endif
1724
1725 #if SP_DEBUG != SP_DEBUG_NONE
1726
1727         return;
1728 }
1729 #endif
1730
1731 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER)
1732 static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)
1733 {
1734         int i;
1735         unsigned int bits, infos;
1736
1737         assert(state != NULL);
1738
1739         bits = state->irq_status;
1740         infos = ia_css_isys_rx_translate_irq_infos(bits);
1741
1742         ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n",
1743                             "receiver errors", bits);
1744
1745         if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
1746                 ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n");
1747         if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
1748                 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n");
1749         if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
1750                 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n");
1751         if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
1752                 ia_css_debug_dtrace(2, "\t\t\tcontrol error\n");
1753         if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
1754                 ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n");
1755         if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
1756                 ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n");
1757         if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
1758                 ia_css_debug_dtrace(2, "\t\t\tunknown error\n");
1759         if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
1760                 ia_css_debug_dtrace(2, "\t\t\tframe sync error\n");
1761         if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
1762                 ia_css_debug_dtrace(2, "\t\t\tframe data error\n");
1763         if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
1764                 ia_css_debug_dtrace(2, "\t\t\tdata timeout\n");
1765         if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
1766                 ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n");
1767         if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
1768                 ia_css_debug_dtrace(2, "\t\t\tline sync error\n");
1769
1770         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1771                             "device_ready", state->device_ready);
1772
1773         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1774                             "irq_status", state->irq_status);
1775
1776         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1777                             "irq_enable", state->irq_enable);
1778
1779         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1780                             "timeout_count", state->timeout_count);
1781
1782         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1783                             "init_count", state->init_count);
1784
1785         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18);
1786
1787         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1788                             "sync_count", state->sync_count);
1789
1790         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count);
1791
1792         for (i = 0; i < MIPI_4LANE_CFG; i++) {
1793                 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1794                                     "lane_sync_count[", i, "]",
1795                                     state->lane_sync_count[i]);
1796         }
1797
1798         for (i = 0; i < MIPI_4LANE_CFG; i++) {
1799                 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
1800                                     "lane_rx_count[", i, "]",
1801                                     state->lane_rx_count[i]);
1802         }
1803
1804         return;
1805 }
1806
1807 static void debug_print_rx_channel_state(rx_channel_state_t *state)
1808 {
1809         int i;
1810
1811         assert(state != NULL);
1812         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1813                             "compression_scheme0", state->comp_scheme0);
1814
1815         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1816                             "compression_scheme1", state->comp_scheme1);
1817
1818         for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1819                 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1820                                     "MIPI Predictor ", i, state->pred[i]);
1821         }
1822
1823         for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
1824                 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
1825                                     "MIPI Compressor ", i, state->comp[i]);
1826         }
1827
1828         return;
1829 }
1830
1831 static void debug_print_rx_state(receiver_state_t *state)
1832 {
1833         int i;
1834
1835         assert(state != NULL);
1836         ia_css_debug_dtrace(2, "CSI Receiver State:\n");
1837
1838         ia_css_debug_dtrace(2, "\tConfiguration:\n");
1839
1840         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1841                             "fs_to_ls_delay", state->fs_to_ls_delay);
1842
1843         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1844                             "ls_to_data_delay", state->ls_to_data_delay);
1845
1846         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1847                             "data_to_le_delay", state->data_to_le_delay);
1848
1849         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1850                             "le_to_fe_delay", state->le_to_fe_delay);
1851
1852         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1853                             "fe_to_fs_delay", state->fe_to_fs_delay);
1854
1855         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1856                             "le_to_fs_delay", state->le_to_fs_delay);
1857
1858         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1859                             "is_two_ppc", state->is_two_ppc);
1860
1861         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1862                             "backend_rst", state->backend_rst);
1863
1864         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18);
1865
1866         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1867                             "force_raw8", state->force_raw8);
1868
1869         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16);
1870
1871         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1872                             "be_gsp_acc_ovl", state->be_gsp_acc_ovl);
1873
1874         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst);
1875
1876         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1877                             "be_is_two_ppc", state->be_is_two_ppc);
1878
1879         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1880                             "be_comp_format0", state->be_comp_format0);
1881
1882         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1883                             "be_comp_format1", state->be_comp_format1);
1884
1885         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1886                             "be_comp_format2", state->be_comp_format2);
1887
1888         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1889                             "be_comp_format3", state->be_comp_format3);
1890
1891         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel);
1892
1893         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1894                             "be_raw16_config", state->be_raw16_config);
1895
1896         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1897                             "be_raw18_config", state->be_raw18_config);
1898
1899         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1900                             "be_force_raw8", state->be_force_raw8);
1901
1902         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1903                             "be_irq_status", state->be_irq_status);
1904
1905         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1906                             "be_irq_clear", state->be_irq_clear);
1907
1908         /* mipi port state */
1909         for (i = 0; i < N_MIPI_PORT_ID; i++) {
1910                 ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i);
1911
1912                 debug_print_rx_mipi_port_state(&state->mipi_port_state[i]);
1913         }
1914         /* end of mipi port state */
1915
1916         /* rx channel state */
1917         for (i = 0; i < N_RX_CHANNEL_ID; i++) {
1918                 ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i);
1919
1920                 debug_print_rx_channel_state(&state->rx_channel_state[i]);
1921         }
1922         /* end of rx channel state */
1923
1924         return;
1925 }
1926 #endif
1927
1928 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
1929 void ia_css_debug_dump_rx_state(void)
1930 {
1931 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER)
1932         receiver_state_t state;
1933
1934         receiver_get_state(RX0_ID, &state);
1935         debug_print_rx_state(&state);
1936 #endif
1937 }
1938 #endif
1939
1940 void ia_css_debug_dump_sp_sw_debug_info(void)
1941 {
1942 #if SP_DEBUG != SP_DEBUG_NONE
1943         struct sh_css_sp_debug_state state;
1944
1945         sh_css_sp_get_debug_state(&state);
1946         ia_css_debug_print_sp_debug_state(&state);
1947 #endif
1948         ia_css_bufq_dump_queue_info();
1949         ia_css_pipeline_dump_thread_map_info();
1950         return;
1951 }
1952
1953 #if defined(USE_INPUT_SYSTEM_VERSION_2)
1954 static void debug_print_isys_capture_unit_state(capture_unit_state_t *state)
1955 {
1956         assert(state != NULL);
1957         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1958                             "Packet_Length", state->Packet_Length);
1959
1960         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1961                             "Received_Length", state->Received_Length);
1962
1963         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1964                             "Received_Short_Packets",
1965                             state->Received_Short_Packets);
1966
1967         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1968                             "Received_Long_Packets",
1969                             state->Received_Long_Packets);
1970
1971         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1972                             "Last_Command", state->Last_Command);
1973
1974         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1975                             "Next_Command", state->Next_Command);
1976
1977         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1978                             "Last_Acknowledge", state->Last_Acknowledge);
1979
1980         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1981                             "Next_Acknowledge", state->Next_Acknowledge);
1982
1983         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1984                             "FSM_State_Info", state->FSM_State_Info);
1985
1986         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1987                             "StartMode", state->StartMode);
1988
1989         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1990                             "Start_Addr", state->Start_Addr);
1991
1992         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1993                             "Mem_Region_Size", state->Mem_Region_Size);
1994
1995         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
1996                             "Num_Mem_Regions", state->Num_Mem_Regions);
1997         return;
1998 }
1999
2000 static void debug_print_isys_acquisition_unit_state(
2001                                 acquisition_unit_state_t *state)
2002 {
2003         assert(state != NULL);
2004
2005         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2006                             "Received_Short_Packets",
2007                             state->Received_Short_Packets);
2008
2009         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2010                             "Received_Long_Packets",
2011                             state->Received_Long_Packets);
2012
2013         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2014                             "Last_Command", state->Last_Command);
2015
2016         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2017                             "Next_Command", state->Next_Command);
2018
2019         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2020                             "Last_Acknowledge", state->Last_Acknowledge);
2021
2022         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2023                             "Next_Acknowledge", state->Next_Acknowledge);
2024
2025         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2026                             "FSM_State_Info", state->FSM_State_Info);
2027
2028         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2029                             "Int_Cntr_Info", state->Int_Cntr_Info);
2030
2031         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2032                             "Start_Addr", state->Start_Addr);
2033
2034         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2035                             "Mem_Region_Size", state->Mem_Region_Size);
2036
2037         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2038                             "Num_Mem_Regions", state->Num_Mem_Regions);
2039 }
2040
2041 static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state)
2042 {
2043         assert(state != NULL);
2044         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd);
2045
2046         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd);
2047
2048         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack);
2049
2050         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack);
2051
2052         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2053                             "top_fsm_state", state->top_fsm_state);
2054
2055         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2056                             "captA_fsm_state", state->captA_fsm_state);
2057
2058         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2059                             "captB_fsm_state", state->captB_fsm_state);
2060
2061         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2062                             "captC_fsm_state", state->captC_fsm_state);
2063
2064         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2065                             "acq_fsm_state", state->acq_fsm_state);
2066
2067         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2068                             "captA_start_addr", state->captA_start_addr);
2069
2070         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2071                             "captB_start_addr", state->captB_start_addr);
2072
2073         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2074                             "captC_start_addr", state->captC_start_addr);
2075
2076         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2077                             "captA_mem_region_size",
2078                             state->captA_mem_region_size);
2079
2080         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2081                             "captB_mem_region_size",
2082                             state->captB_mem_region_size);
2083
2084         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2085                             "captC_mem_region_size",
2086                             state->captC_mem_region_size);
2087
2088         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2089                             "captA_num_mem_regions",
2090                             state->captA_num_mem_regions);
2091
2092         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2093                             "captB_num_mem_regions",
2094                             state->captB_num_mem_regions);
2095
2096         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2097                             "captC_num_mem_regions",
2098                             state->captC_num_mem_regions);
2099
2100         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2101                             "acq_start_addr", state->acq_start_addr);
2102
2103         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2104                             "acq_mem_region_size", state->acq_mem_region_size);
2105
2106         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2107                             "acq_num_mem_regions", state->acq_num_mem_regions);
2108
2109         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2110                             "capt_reserve_one_mem_region",
2111                             state->capt_reserve_one_mem_region);
2112
2113         return;
2114 }
2115
2116 static void debug_print_isys_state(input_system_state_t *state)
2117 {
2118         int i;
2119
2120         assert(state != NULL);
2121         ia_css_debug_dtrace(2, "InputSystem State:\n");
2122
2123         /* configuration */
2124         ia_css_debug_dtrace(2, "\tConfiguration:\n");
2125
2126         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2127                             "str_multiCastA_sel", state->str_multicastA_sel);
2128
2129         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2130                             "str_multicastB_sel", state->str_multicastB_sel);
2131
2132         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2133                             "str_multicastC_sel", state->str_multicastC_sel);
2134
2135         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2136                             "str_mux_sel", state->str_mux_sel);
2137
2138         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2139                             "str_mon_status", state->str_mon_status);
2140
2141         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2142                             "str_mon_irq_cond", state->str_mon_irq_cond);
2143
2144         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2145                             "str_mon_irq_en", state->str_mon_irq_en);
2146
2147         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2148                             "isys_srst", state->isys_srst);
2149
2150         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2151                             "isys_slv_reg_srst", state->isys_slv_reg_srst);
2152
2153         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2154                             "str_deint_portA_cnt", state->str_deint_portA_cnt);
2155
2156         ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2157                             "str_deint_portB_cnd", state->str_deint_portB_cnt);
2158         /* end of configuration */
2159
2160         /* capture unit state */
2161         for (i = 0; i < N_CAPTURE_UNIT_ID; i++) {
2162                 capture_unit_state_t *capture_unit_state;
2163
2164                 ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i);
2165
2166                 capture_unit_state = &state->capture_unit[i];
2167                 debug_print_isys_capture_unit_state(capture_unit_state);
2168         }
2169         /* end of capture unit state */
2170
2171         /* acquisition unit state */
2172         for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) {
2173                 acquisition_unit_state_t *acquisition_unit_state;
2174
2175                 ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i);
2176
2177                 acquisition_unit_state = &state->acquisition_unit[i];
2178                 debug_print_isys_acquisition_unit_state(acquisition_unit_state);
2179         }
2180         /* end of acquisition unit state */
2181
2182         /* control unit state */
2183         for (i = 0; i < N_CTRL_UNIT_ID; i++) {
2184                 ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i);
2185
2186                 debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]);
2187         }
2188         /* end of control unit state */
2189 }
2190
2191 void ia_css_debug_dump_isys_state(void)
2192 {
2193         input_system_state_t state;
2194
2195         input_system_get_state(INPUT_SYSTEM0_ID, &state);
2196         debug_print_isys_state(&state);
2197
2198         return;
2199 }
2200 #endif
2201 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
2202 void ia_css_debug_dump_isys_state(void)
2203 {
2204         /* Android compilation fails if made a local variable
2205         stack size on android is limited to 2k and this structure
2206         is around 3.5K, in place of static malloc can be done but
2207         if this call is made too often it will lead to fragment memory
2208         versus a fixed allocation */
2209         static input_system_state_t state;
2210
2211         input_system_get_state(INPUT_SYSTEM0_ID, &state);
2212         input_system_dump_state(INPUT_SYSTEM0_ID, &state);
2213 }
2214 #endif
2215
2216 void ia_css_debug_dump_debug_info(const char *context)
2217 {
2218         if (context == NULL)
2219                 context = "No Context provided";
2220
2221         ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context);
2222 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
2223         ia_css_debug_dump_rx_state();
2224 #endif
2225 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2)
2226         ia_css_debug_dump_if_state();
2227 #endif
2228         ia_css_debug_dump_isp_state();
2229         ia_css_debug_dump_isp_sp_fifo_state();
2230         ia_css_debug_dump_isp_gdc_fifo_state();
2231         ia_css_debug_dump_sp_state();
2232         ia_css_debug_dump_perf_counters();
2233
2234 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
2235         sh_css_dump_thread_wait_info();
2236         sh_css_dump_pipe_stage_info();
2237         sh_css_dump_pipe_stripe_info();
2238 #endif
2239         ia_css_debug_dump_dma_isp_fifo_state();
2240         ia_css_debug_dump_dma_sp_fifo_state();
2241         ia_css_debug_dump_dma_state();
2242 #if defined(USE_INPUT_SYSTEM_VERSION_2)
2243         ia_css_debug_dump_isys_state();
2244
2245         {
2246                 irq_controller_state_t state;
2247                 irq_controller_get_state(IRQ2_ID, &state);
2248
2249                 ia_css_debug_dtrace(2, "\t%-32s:\n",
2250                                     "Input System IRQ Controller State");
2251
2252                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2253                                     "irq_edge", state.irq_edge);
2254
2255                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2256                                     "irq_mask", state.irq_mask);
2257
2258                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2259                                     "irq_status", state.irq_status);
2260
2261                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2262                                     "irq_enable", state.irq_enable);
2263
2264                 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
2265                                     "irq_level_not_pulse",
2266                                     state.irq_level_not_pulse);
2267         }
2268 #endif
2269 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401)
2270         ia_css_debug_dump_isys_state();
2271 #endif
2272 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
2273         ia_css_debug_tagger_state();
2274 #endif
2275         return;
2276 }
2277
2278 /** this function is for debug use, it can make SP go to sleep
2279   state after each frame, then user can dump the stable SP dmem.
2280   this function can be called after ia_css_start_sp()
2281   and before sh_css_init_buffer_queues()
2282 */
2283 void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode)
2284 {
2285         const struct ia_css_fw_info *fw;
2286         unsigned int HIVE_ADDR_sp_sleep_mode;
2287
2288         fw = &sh_css_sp_fw;
2289         HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode;
2290
2291         (void)HIVE_ADDR_sp_sleep_mode;  /* Suppres warnings in CRUN */
2292
2293         sp_dmem_store_uint32(SP0_ID,
2294                              (unsigned int)sp_address_of(sp_sleep_mode),
2295                              (uint32_t) mode);
2296 }
2297
2298 void ia_css_debug_wake_up_sp(void)
2299 {
2300         /*hrt_ctl_start(SP); */
2301         sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT);
2302 }
2303
2304 #if !defined(IS_ISP_2500_SYSTEM)
2305 #define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \
2306         (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \
2307         findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel))
2308
2309 #define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel)
2310
2311 /* Find a stage that support the kernel and return the parameters for that kernel */
2312 static char *
2313 findf_dmem_params(struct ia_css_stream *stream, short idx)
2314 {
2315         int i;
2316         for (i = 0; i < stream->num_pipes; i++) {
2317                 struct ia_css_pipe *pipe = stream->pipes[i];
2318                 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe);
2319                 struct ia_css_pipeline_stage *stage;
2320                 for (stage = pipeline->stages; stage; stage = stage->next) {
2321                         struct ia_css_binary *binary = stage->binary;
2322                         short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem;
2323                         short dmem_offset = offsets[idx];
2324                         const struct ia_css_host_data *isp_data =
2325                                 ia_css_isp_param_get_mem_init(&binary->mem_params,
2326                                                         IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0);
2327                         if (dmem_offset < 0)
2328                                 continue;
2329                         return &isp_data->address[dmem_offset];
2330                 }
2331         }
2332         return NULL;
2333 }
2334 #endif
2335
2336 void ia_css_debug_dump_isp_params(struct ia_css_stream *stream,
2337                                   unsigned int enable)
2338 {
2339         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n");
2340 #if defined(IS_ISP_2500_SYSTEM)
2341         (void)enable;
2342         (void)stream;
2343 #else
2344
2345         assert(stream != NULL);
2346         if ((enable & IA_CSS_DEBUG_DUMP_FPN)
2347             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2348                 ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE);
2349         }
2350         if ((enable & IA_CSS_DEBUG_DUMP_OB)
2351             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2352                 ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE);
2353         }
2354         if ((enable & IA_CSS_DEBUG_DUMP_SC)
2355             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2356                 ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE);
2357         }
2358         if ((enable & IA_CSS_DEBUG_DUMP_WB)
2359             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2360                 ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE);
2361         }
2362         if ((enable & IA_CSS_DEBUG_DUMP_DP)
2363             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2364                 ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE);
2365         }
2366         if ((enable & IA_CSS_DEBUG_DUMP_BNR)
2367             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2368                 ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE);
2369         }
2370         if ((enable & IA_CSS_DEBUG_DUMP_S3A)
2371             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2372                 ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE);
2373         }
2374         if ((enable & IA_CSS_DEBUG_DUMP_DE)
2375             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2376                 ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE);
2377         }
2378         if ((enable & IA_CSS_DEBUG_DUMP_YNR)
2379             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2380                 ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr),  IA_CSS_DEBUG_VERBOSE);
2381                 ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE);
2382         }
2383         if ((enable & IA_CSS_DEBUG_DUMP_CSC)
2384             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2385                 ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE);
2386                 ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), IA_CSS_DEBUG_VERBOSE);
2387                 ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), IA_CSS_DEBUG_VERBOSE);
2388         }
2389         if ((enable & IA_CSS_DEBUG_DUMP_GC)
2390             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2391                 ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE);
2392         }
2393         if ((enable & IA_CSS_DEBUG_DUMP_TNR)
2394             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2395                 ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE);
2396         }
2397         if ((enable & IA_CSS_DEBUG_DUMP_ANR)
2398             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2399                 ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE);
2400         }
2401         if ((enable & IA_CSS_DEBUG_DUMP_CE)
2402             || (enable & IA_CSS_DEBUG_DUMP_ALL)) {
2403                 ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE);
2404         }
2405 #endif
2406 }
2407
2408 void sh_css_dump_sp_raw_copy_linecount(bool reduced)
2409 {
2410         const struct ia_css_fw_info *fw;
2411         unsigned int HIVE_ADDR_raw_copy_line_count;
2412         int32_t raw_copy_line_count;
2413         static int32_t prev_raw_copy_line_count = -1;
2414
2415         fw = &sh_css_sp_fw;
2416         HIVE_ADDR_raw_copy_line_count =
2417                         fw->info.sp.raw_copy_line_count;
2418
2419         (void)HIVE_ADDR_raw_copy_line_count;
2420
2421         sp_dmem_load(SP0_ID,
2422                 (unsigned int)sp_address_of(raw_copy_line_count),
2423                      &raw_copy_line_count,
2424                      sizeof(raw_copy_line_count));
2425
2426         /* only indicate if copy loop is active */
2427         if (reduced)
2428                 raw_copy_line_count = (raw_copy_line_count < 0)?raw_copy_line_count:1;
2429         /* do the handling */
2430         if (prev_raw_copy_line_count != raw_copy_line_count) {
2431                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2432                         "sh_css_dump_sp_raw_copy_linecount() "
2433                         "line_count=%d\n",
2434                         raw_copy_line_count);
2435                 prev_raw_copy_line_count = raw_copy_line_count;
2436         }
2437 }
2438
2439 void ia_css_debug_dump_isp_binary(void)
2440 {
2441         const struct ia_css_fw_info *fw;
2442         unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id;
2443         uint32_t curr_binary_id;
2444         static uint32_t prev_binary_id = 0xFFFFFFFF;
2445         static uint32_t sample_count;
2446
2447         fw = &sh_css_sp_fw;
2448         HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id;
2449
2450         (void)HIVE_ADDR_pipeline_sp_curr_binary_id;
2451
2452         sp_dmem_load(SP0_ID,
2453                      (unsigned int)sp_address_of(pipeline_sp_curr_binary_id),
2454                      &curr_binary_id,
2455                      sizeof(curr_binary_id));
2456
2457         /* do the handling */
2458         sample_count++;
2459         if (prev_binary_id != curr_binary_id) {
2460                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2461                                     "sh_css_dump_isp_binary() "
2462                                     "pipe_id=%d, binary_id=%d, sample_count=%d\n",
2463                                     (curr_binary_id >> 16),
2464                                     (curr_binary_id & 0x0ffff),
2465                                     sample_count);
2466                 sample_count = 0;
2467                 prev_binary_id = curr_binary_id;
2468         }
2469 }
2470
2471 void ia_css_debug_dump_perf_counters(void)
2472 {
2473 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2)
2474         const struct ia_css_fw_info *fw;
2475         int i;
2476         unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt;
2477         int32_t ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; /* 3 Capture Units and 1 Acquire Unit. */
2478
2479         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n");
2480
2481         fw = &sh_css_sp_fw;
2482         HIVE_ADDR_ia_css_isys_sp_error_cnt = fw->info.sp.perf_counter_input_system_error;
2483
2484         (void)HIVE_ADDR_ia_css_isys_sp_error_cnt;
2485
2486         sp_dmem_load(SP0_ID,
2487                      (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt),
2488                      &ia_css_sp_input_system_error_cnt,
2489                      sizeof(ia_css_sp_input_system_error_cnt));
2490
2491         for (i = 0; i < N_MIPI_PORT_ID + 1; i++) {
2492                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n",
2493                                 i, ia_css_sp_input_system_error_cnt[i]);
2494         }
2495 #endif
2496 }
2497
2498 /*
2499
2500 void sh_css_init_ddr_debug_queue(void)
2501 {
2502         hrt_vaddress ddr_debug_queue_addr =
2503                         mmgr_malloc(sizeof(debug_data_ddr_t));
2504         const struct ia_css_fw_info *fw;
2505         unsigned int HIVE_ADDR_debug_buffer_ddr_address;
2506
2507         fw = &sh_css_sp_fw;
2508         HIVE_ADDR_debug_buffer_ddr_address =
2509                         fw->info.sp.debug_buffer_ddr_address;
2510
2511         (void)HIVE_ADDR_debug_buffer_ddr_address;
2512
2513         debug_buffer_ddr_init(ddr_debug_queue_addr);
2514
2515         sp_dmem_store_uint32(SP0_ID,
2516                 (unsigned int)sp_address_of(debug_buffer_ddr_address),
2517                 (uint32_t)(ddr_debug_queue_addr));
2518 }
2519
2520 void sh_css_load_ddr_debug_queue(void)
2521 {
2522         debug_synch_queue_ddr();
2523 }
2524
2525 void ia_css_debug_dump_ddr_debug_queue(void)
2526 {
2527         int i;
2528         sh_css_load_ddr_debug_queue();
2529         for (i = 0; i < DEBUG_BUF_SIZE; i++) {
2530                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2531                         "ddr_debug_queue[%d] = 0x%x\n",
2532                         i, debug_data_ptr->buf[i]);
2533         }
2534 }
2535 */
2536
2537 /**
2538  * @brief Initialize the debug mode.
2539  * Refer to "ia_css_debug.h" for more details.
2540  */
2541 bool ia_css_debug_mode_init(void)
2542 {
2543         bool rc;
2544         rc = sh_css_sp_init_dma_sw_reg(0);
2545         return rc;
2546 }
2547
2548 /**
2549  * @brief Disable the DMA channel.
2550  * Refer to "ia_css_debug.h" for more details.
2551  */
2552 bool
2553 ia_css_debug_mode_disable_dma_channel(int dma_id,
2554                                       int channel_id, int request_type)
2555 {
2556         bool rc;
2557
2558         rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false);
2559
2560         return rc;
2561 }
2562
2563 /**
2564  * @brief Enable the DMA channel.
2565  * Refer to "ia_css_debug.h" for more details.
2566  */
2567 bool
2568 ia_css_debug_mode_enable_dma_channel(int dma_id,
2569                                      int channel_id, int request_type)
2570 {
2571         bool rc;
2572
2573         rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true);
2574
2575         return rc;
2576 }
2577
2578 void dtrace_dot(const char *fmt, ...)
2579 {
2580         va_list ap;
2581 #ifdef HRT_CSIM
2582         va_list ap2;
2583 #endif
2584
2585         assert(fmt != NULL);
2586         va_start(ap, fmt);
2587 #ifdef HRT_CSIM
2588         va_start(ap2, fmt);
2589 #endif
2590
2591         ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);
2592         ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap);
2593         ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);
2594 #ifdef HRT_CSIM
2595         /* For CSIM we print double because HSS log can mess up this output
2596          * As post processing, we remove incomplete lines and make lines uniq.
2597          * */
2598         ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START);
2599         ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap2);
2600         ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);\
2601
2602         va_end(ap2);
2603 #endif
2604         va_end(ap);
2605 }
2606 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG
2607 void sh_css_dump_thread_wait_info(void)
2608 {
2609         const struct ia_css_fw_info *fw;
2610         int i;
2611         unsigned int HIVE_ADDR_sp_thread_wait;
2612         int32_t sp_thread_wait[MAX_THREAD_NUM];
2613         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n");
2614
2615         fw = &sh_css_sp_fw;
2616         HIVE_ADDR_sp_thread_wait =
2617                         fw->info.sp.debug_wait;
2618
2619         (void)HIVE_ADDR_sp_thread_wait;
2620
2621         sp_dmem_load(SP0_ID,
2622                 (unsigned int)sp_address_of(sp_thread_wait),
2623                      &sp_thread_wait,
2624                      sizeof(sp_thread_wait));
2625         for (i = 0; i < MAX_THREAD_NUM; i++) {
2626                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2627                         "\twait[%d] = 0x%X\n",
2628                         i, sp_thread_wait[i]);
2629         }
2630
2631 }
2632
2633 void sh_css_dump_pipe_stage_info(void)
2634 {
2635         const struct ia_css_fw_info *fw;
2636         int i;
2637         unsigned int HIVE_ADDR_sp_pipe_stage;
2638         int32_t sp_pipe_stage[MAX_THREAD_NUM];
2639         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n");
2640
2641         fw = &sh_css_sp_fw;
2642         HIVE_ADDR_sp_pipe_stage =
2643                         fw->info.sp.debug_stage;
2644
2645         (void)HIVE_ADDR_sp_pipe_stage;
2646
2647         sp_dmem_load(SP0_ID,
2648                 (unsigned int)sp_address_of(sp_pipe_stage),
2649                      &sp_pipe_stage,
2650                      sizeof(sp_pipe_stage));
2651         for (i = 0; i < MAX_THREAD_NUM; i++) {
2652                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2653                         "\tstage[%d] = %d\n",
2654                         i, sp_pipe_stage[i]);
2655         }
2656
2657 }
2658
2659 void sh_css_dump_pipe_stripe_info(void)
2660 {
2661         const struct ia_css_fw_info *fw;
2662         int i;
2663         unsigned int HIVE_ADDR_sp_pipe_stripe;
2664         int32_t sp_pipe_stripe[MAX_THREAD_NUM];
2665         ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n");
2666
2667         fw = &sh_css_sp_fw;
2668         HIVE_ADDR_sp_pipe_stripe =
2669                         fw->info.sp.debug_stripe;
2670
2671         (void)HIVE_ADDR_sp_pipe_stripe;
2672
2673         sp_dmem_load(SP0_ID,
2674                 (unsigned int)sp_address_of(sp_pipe_stripe),
2675                      &sp_pipe_stripe,
2676                      sizeof(sp_pipe_stripe));
2677         for (i = 0; i < MAX_THREAD_NUM; i++) {
2678                 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE,
2679                         "\tstripe[%d] = %d\n",
2680                         i, sp_pipe_stripe[i]);
2681         }
2682
2683 }
2684 #endif
2685
2686 static void
2687 ia_css_debug_pipe_graph_dump_frame(
2688         struct ia_css_frame *frame,
2689         enum ia_css_pipe_id id,
2690         char const *blob_name,
2691         char const *frame_name,
2692         bool in_frame)
2693 {
2694         char bufinfo[100];
2695
2696         if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) {
2697                 snprintf(bufinfo, sizeof(bufinfo), "Internal");
2698         } else {
2699                 snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s",
2700                         pipe_id_to_str[id],
2701                         queue_id_to_str[frame->dynamic_queue_id]);
2702         }
2703         dtrace_dot(
2704                 "node [shape = box, "
2705                 "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" "
2706                 "[label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];",
2707                 HOST_ADDRESS(frame),
2708                 debug_frame_format2str(frame->info.format),
2709                 frame->info.res.width,
2710                 frame->info.padded_width,
2711                 frame->info.res.height,
2712                 frame->info.raw_bit_depth,
2713                 bufinfo);
2714
2715         if (in_frame) {
2716                 dtrace_dot(
2717                         "\"0x%08lx\"->\"%s(pipe%d)\" "
2718                         "[label = %s_frame];",
2719                         HOST_ADDRESS(frame),
2720                         blob_name, id, frame_name);
2721         } else {
2722                 dtrace_dot(
2723                         "\"%s(pipe%d)\"->\"0x%08lx\" "
2724                         "[label = %s_frame];",
2725                         blob_name, id,
2726                         HOST_ADDRESS(frame),
2727                         frame_name);
2728         }
2729 }
2730
2731 void
2732 ia_css_debug_pipe_graph_dump_prologue(void)
2733 {
2734         dtrace_dot("digraph sh_css_pipe_graph {");
2735         dtrace_dot("rankdir=LR;");
2736
2737         dtrace_dot("fontsize=9;");
2738         dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, "
2739                 "dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, "
2740                 "fbds=fixed_bayer_ds, bf6=bayer_fir_6db, "
2741                 "rawb=raw_binning, cont=continuous, disc=dis_crop\\n"
2742                 "dp2a=dp_2adjacent, outp=output, outt=out_table, "
2743                 "reff=ref_frame, par=params, gam=gamma, "
2744                 "cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, "
2745                 "outf=out_frame, hs=high_speed, inpc=input_chunking\"");
2746 }
2747
2748 void ia_css_debug_pipe_graph_dump_epilogue(void)
2749 {
2750
2751         if (strlen(ring_buffer) > 0) {
2752                 dtrace_dot(ring_buffer);
2753         }
2754
2755
2756         if (pg_inst.stream_format != N_IA_CSS_STREAM_FORMAT) {
2757                 /* An input stream format has been set so assume we have
2758                  * an input system and sensor
2759                  */
2760
2761
2762                 dtrace_dot(
2763                         "node [shape = doublecircle, "
2764                         "fixedsize=true, width=2.5]; \"input_system\" "
2765                         "[label = \"Input system\"];");
2766
2767                 dtrace_dot(
2768                         "\"input_system\"->\"%s\" "
2769                         "[label = \"%s\"];",
2770                         dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format));
2771
2772                 dtrace_dot(
2773                         "node [shape = doublecircle, "
2774                         "fixedsize=true, width=2.5]; \"sensor\" "
2775                         "[label = \"Sensor\"];");
2776
2777                 dtrace_dot(
2778                         "\"sensor\"->\"input_system\" "
2779                         "[label = \"%s\\n%d x %d\\n(%d x %d)\"];",
2780                         debug_stream_format2str(pg_inst.stream_format),
2781                         pg_inst.width, pg_inst.height,
2782                         pg_inst.eff_width, pg_inst.eff_height);
2783         }
2784
2785         dtrace_dot("}");
2786
2787         /* Reset temp strings */
2788         memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin));
2789         memset(ring_buffer, 0, sizeof(ring_buffer));
2790
2791         pg_inst.do_init = true;
2792         pg_inst.width = 0;
2793         pg_inst.height = 0;
2794         pg_inst.eff_width = 0;
2795         pg_inst.eff_height = 0;
2796         pg_inst.stream_format = N_IA_CSS_STREAM_FORMAT;
2797 }
2798
2799 void
2800 ia_css_debug_pipe_graph_dump_stage(
2801         struct ia_css_pipeline_stage *stage,
2802         enum ia_css_pipe_id id)
2803 {
2804         char blob_name[SH_CSS_MAX_BINARY_NAME+10] = "<unknown type>";
2805         char const *bin_type = "<unknown type>";
2806         int i;
2807
2808         assert(stage != NULL);
2809         if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC)
2810                 return;
2811
2812         if (pg_inst.do_init) {
2813                 ia_css_debug_pipe_graph_dump_prologue();
2814                 pg_inst.do_init = false;
2815         }
2816
2817         if (stage->binary) {
2818                 bin_type = "binary";
2819                 if (stage->binary->info->blob)
2820                         snprintf(blob_name, sizeof(blob_name), "%s_stage%d",
2821                                 stage->binary->info->blob->name, stage->stage_num);
2822         } else if (stage->firmware) {
2823                 bin_type = "firmware";
2824                 strncpy_s(blob_name, sizeof(blob_name), IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), sizeof(blob_name));
2825         }
2826
2827         /* Guard in case of binaries that don't have any binary_info */
2828         if (stage->binary_info != NULL) {
2829                 char enable_info1[100];
2830                 char enable_info2[100];
2831                 char enable_info3[100];
2832                 char enable_info[200];
2833                 struct ia_css_binary_info *bi = stage->binary_info;
2834
2835                 /* Split it in 2 function-calls to keep the amount of
2836                  * parameters per call "reasonable"
2837                  */
2838                 snprintf(enable_info1, sizeof(enable_info1),
2839                         "%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
2840                         bi->enable.reduced_pipe ?       "rp," : "",
2841                         bi->enable.vf_veceven ?         "vfve," : "",
2842                         bi->enable.dis ?                "dis," : "",
2843                         bi->enable.dvs_envelope ?       "dvse," : "",
2844                         bi->enable.uds ?                "uds," : "",
2845                         bi->enable.dvs_6axis ?          "dvs6," : "",
2846                         bi->enable.block_output ?       "bo," : "",
2847                         bi->enable.ds ?                 "ds," : "",
2848                         bi->enable.bayer_fir_6db ?      "bf6," : "",
2849                         bi->enable.raw_binning ?        "rawb," : "",
2850                         bi->enable.continuous ?         "cont," : "",
2851                         bi->enable.s3a ?                "s3a," : "",
2852                         bi->enable.fpnr ?               "fpnr," : "",
2853                         bi->enable.sc ?                 "sc," : ""
2854                         );
2855
2856                 snprintf(enable_info2, sizeof(enable_info2),
2857                         "%s%s%s%s%s%s%s%s%s%s%s",
2858                         bi->enable.macc ?               "macc," : "",
2859                         bi->enable.output ?             "outp," : "",
2860                         bi->enable.ref_frame ?          "reff," : "",
2861                         bi->enable.tnr ?                "tnr," : "",
2862                         bi->enable.xnr ?                "xnr," : "",
2863                         bi->enable.params ?             "par," : "",
2864                         bi->enable.ca_gdc ?             "cagdc," : "",
2865                         bi->enable.isp_addresses ?      "ispa," : "",
2866                         bi->enable.in_frame ?           "inf," : "",
2867                         bi->enable.out_frame ?          "outf," : "",
2868                         bi->enable.high_speed ?         "hs," : ""
2869                         );
2870
2871                 /* And merge them into one string */
2872                 snprintf(enable_info, sizeof(enable_info), "%s%s",
2873                                                 enable_info1, enable_info2);
2874                 {
2875                         int l, p;
2876                         char *ei = enable_info;
2877
2878                         l = strlen(ei);
2879
2880                         /* Replace last ',' with \0 if present */
2881                         if (l && enable_info[l-1] == ',')
2882                                 enable_info[--l] = '\0';
2883
2884                         if (l <= ENABLE_LINE_MAX_LENGTH) {
2885                                 /* It fits on one line, copy string and init */
2886                                 /* other helper strings with empty string */
2887                                 strcpy_s(enable_info,
2888                                         sizeof(enable_info),
2889                                         ei);
2890                         } else {
2891                                 /* Too big for one line, find last comma */
2892                                 p = ENABLE_LINE_MAX_LENGTH;
2893                                 while (ei[p] != ',')
2894                                         p--;
2895                                 /* Last comma found, copy till that comma */
2896                                 strncpy_s(enable_info1,
2897                                         sizeof(enable_info1),
2898                                         ei, p);
2899                                 enable_info1[p] = '\0';
2900
2901                                 ei += p+1;
2902                                 l = strlen(ei);
2903
2904                                 if (l <= ENABLE_LINE_MAX_LENGTH) {
2905                                         /* The 2nd line fits */
2906                                         /* we cannot use ei as argument because
2907                                          * it is not guarenteed dword aligned
2908                                          */
2909                                         strncpy_s(enable_info2,
2910                                                 sizeof(enable_info2),
2911                                                 ei, l);
2912                                         enable_info2[l] = '\0';
2913                                         snprintf(enable_info, sizeof(enable_info), "%s\\n%s",
2914                                                 enable_info1, enable_info2);
2915
2916                                 } else {
2917                                         /* 2nd line is still too long */
2918                                         p = ENABLE_LINE_MAX_LENGTH;
2919                                         while (ei[p] != ',')
2920                                                 p--;
2921                                         strncpy_s(enable_info2,
2922                                                 sizeof(enable_info2),
2923                                                 ei, p);
2924                                         enable_info2[p] = '\0';
2925                                         ei += p+1;
2926                                         l = strlen(ei);
2927
2928                                         if (l <= ENABLE_LINE_MAX_LENGTH) {
2929                                                 /* The 3rd line fits */
2930                                                 /* we cannot use ei as argument because
2931                                                 * it is not guarenteed dword aligned
2932                                                 */
2933                                                 strcpy_s(enable_info3,
2934                                                         sizeof(enable_info3), ei);
2935                                                 enable_info3[l] = '\0';
2936                                                 snprintf(enable_info, sizeof(enable_info),
2937                                                         "%s\\n%s\\n%s",
2938                                                         enable_info1, enable_info2,
2939                                                         enable_info3);
2940                                         } else {
2941                                                 /* 3rd line is still too long */
2942                                                 p = ENABLE_LINE_MAX_LENGTH;
2943                                                 while (ei[p] != ',')
2944                                                         p--;
2945                                                 strncpy_s(enable_info3,
2946                                                         sizeof(enable_info3),
2947                                                         ei, p);
2948                                                 enable_info3[p] = '\0';
2949                                                 ei += p+1;
2950                                                 strcpy_s(enable_info3,
2951                                                         sizeof(enable_info3), ei);
2952                                                 snprintf(enable_info, sizeof(enable_info),
2953                                                         "%s\\n%s\\n%s",
2954                                                         enable_info1, enable_info2,
2955                                                         enable_info3);
2956                                         }
2957                                 }
2958                         }
2959                 }
2960
2961                 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
2962                         "label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"",
2963                         bin_type, blob_name, enable_info, blob_name, id);
2964
2965         }
2966         else {
2967                 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
2968                         "label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"",
2969                         bin_type, blob_name, blob_name, id);
2970         }
2971
2972         if (stage->stage_num == 0) {
2973                 /*
2974                  * There are some implicite assumptions about which bin is the
2975                  * input binary e.g. which one is connected to the input system
2976                  * Priority:
2977                  * 1) sp_raw_copy bin has highest priority
2978                  * 2) First stage==0 binary of preview, video or capture
2979                  */
2980                 if (strlen(dot_id_input_bin) == 0) {
2981                         snprintf(dot_id_input_bin, sizeof(dot_id_input_bin),
2982                                 "%s(pipe%d)", blob_name, id);
2983                 }
2984         }
2985
2986         if (stage->args.in_frame) {
2987                 ia_css_debug_pipe_graph_dump_frame(
2988                         stage->args.in_frame, id, blob_name,
2989                         "in", true);
2990         }
2991
2992 #ifndef ISP2401
2993         for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) {
2994 #else
2995         for (i = 0; i < NUM_TNR_FRAMES; i++) {
2996 #endif
2997                 if (stage->args.tnr_frames[i]) {
2998                         ia_css_debug_pipe_graph_dump_frame(
2999                                         stage->args.tnr_frames[i], id,
3000                                         blob_name, "tnr_frame", true);
3001                 }
3002         }
3003
3004         for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) {
3005                 if (stage->args.delay_frames[i]) {
3006                         ia_css_debug_pipe_graph_dump_frame(
3007                                         stage->args.delay_frames[i], id,
3008                                         blob_name, "delay_frame", true);
3009                 }
3010         }
3011
3012         for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) {
3013                 if (stage->args.out_frame[i]) {
3014                         ia_css_debug_pipe_graph_dump_frame(
3015                                 stage->args.out_frame[i], id, blob_name,
3016                                 "out", false);
3017                 }
3018         }
3019
3020         if (stage->args.out_vf_frame) {
3021                 ia_css_debug_pipe_graph_dump_frame(
3022                         stage->args.out_vf_frame, id, blob_name,
3023                         "out_vf", false);
3024         }
3025 }
3026
3027 void
3028 ia_css_debug_pipe_graph_dump_sp_raw_copy(
3029         struct ia_css_frame *out_frame)
3030 {
3031         assert(out_frame != NULL);
3032         if (pg_inst.do_init) {
3033                 ia_css_debug_pipe_graph_dump_prologue();
3034                 pg_inst.do_init = false;
3035         }
3036
3037         dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, "
3038                 "label=\"%s\\n%s\"]; \"%s(pipe%d)\"",
3039                 "sp-binary", "sp_raw_copy", "sp_raw_copy", 1);
3040
3041         snprintf(ring_buffer, sizeof(ring_buffer),
3042                 "node [shape = box, "
3043                 "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" "
3044                 "[label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];",
3045                 HOST_ADDRESS(out_frame),
3046                 debug_frame_format2str(out_frame->info.format),
3047                 out_frame->info.res.width,
3048                 out_frame->info.padded_width,
3049                 out_frame->info.res.height);
3050
3051         dtrace_dot(ring_buffer);
3052
3053         dtrace_dot(
3054                 "\"%s(pipe%d)\"->\"0x%08lx\" "
3055                 "[label = out_frame];",
3056                 "sp_raw_copy", 1, HOST_ADDRESS(out_frame));
3057
3058         snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", "sp_raw_copy", 1);
3059 }
3060
3061 void
3062 ia_css_debug_pipe_graph_dump_stream_config(
3063         const struct ia_css_stream_config *stream_config)
3064 {
3065         pg_inst.width = stream_config->input_config.input_res.width;
3066         pg_inst.height = stream_config->input_config.input_res.height;
3067         pg_inst.eff_width = stream_config->input_config.effective_res.width;
3068         pg_inst.eff_height = stream_config->input_config.effective_res.height;
3069         pg_inst.stream_format = stream_config->input_config.format;
3070 }
3071
3072 void
3073 ia_css_debug_dump_resolution(
3074         const struct ia_css_resolution *res,
3075         const char *label)
3076 {
3077         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n",
3078                         label, res->width, res->height);
3079 }
3080
3081 void
3082 ia_css_debug_dump_frame_info(
3083         const struct ia_css_frame_info *info,
3084         const char *label)
3085 {
3086         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label);
3087         ia_css_debug_dump_resolution(&info->res, "res");
3088         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n",
3089                         info->padded_width);
3090         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format);
3091         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n",
3092                         info->raw_bit_depth);
3093         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n",
3094                         info->raw_bayer_order);
3095 }
3096
3097 void
3098 ia_css_debug_dump_capture_config(
3099         const struct ia_css_capture_config *config)
3100 {
3101         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
3102         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3103         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr:  %d\n",
3104                         config->enable_xnr);
3105         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n",
3106                         config->enable_raw_output);
3107 }
3108
3109 void
3110 ia_css_debug_dump_pipe_extra_config(
3111         const struct ia_css_pipe_extra_config *extra_config)
3112 {
3113         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__);
3114         if (extra_config) {
3115                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3116                                 "enable_raw_binning: %d\n",
3117                                 extra_config->enable_raw_binning);
3118                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n",
3119                                 extra_config->enable_yuv_ds);
3120                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3121                                 "enable_high_speed:  %d\n",
3122                                 extra_config->enable_high_speed);
3123                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3124                                 "enable_dvs_6axis: %d\n",
3125                                 extra_config->enable_dvs_6axis);
3126                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3127                                 "enable_reduced_pipe: %d\n",
3128                                 extra_config->enable_reduced_pipe);
3129                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3130                                 "enable_fractional_ds: %d\n",
3131                                 extra_config->enable_fractional_ds);
3132                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n",
3133                                 extra_config->disable_vf_pp);
3134         }
3135 }
3136
3137 void
3138 ia_css_debug_dump_pipe_config(
3139         const struct ia_css_pipe_config *config)
3140 {
3141         unsigned int i;
3142
3143         IA_CSS_ENTER_PRIVATE("config = %p", config);
3144         if (!config) {
3145                 IA_CSS_ERROR("NULL input parameter");
3146                 IA_CSS_LEAVE_PRIVATE("");
3147                 return;
3148         }
3149         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3150         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n",
3151                         config->isp_pipe_version);
3152         ia_css_debug_dump_resolution(&config->bayer_ds_out_res,
3153                         "bayer_ds_out_res");
3154         ia_css_debug_dump_resolution(&config->capt_pp_in_res,
3155                         "capt_pp_in_res");
3156         ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res");
3157 #ifdef ISP2401
3158         ia_css_debug_dump_resolution(&config->output_system_in_res,
3159                                      "output_system_in_res");
3160 #endif
3161         ia_css_debug_dump_resolution(&config->dvs_crop_out_res,
3162                         "dvs_crop_out_res");
3163         for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) {
3164                 ia_css_debug_dump_frame_info(&config->output_info[i], "output_info");
3165                 ia_css_debug_dump_frame_info(&config->vf_output_info[i],
3166                                 "vf_output_info");
3167         }
3168         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_extension: 0x%x\n",
3169                         config->acc_extension);
3170         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_acc_stages: %d\n",
3171                         config->num_acc_stages);
3172         ia_css_debug_dump_capture_config(&config->default_capture_config);
3173         ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope");
3174         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n",
3175                         config->dvs_frame_delay);
3176         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_num_execs: %d\n",
3177                         config->acc_num_execs);
3178         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n",
3179                         config->enable_dz);
3180         IA_CSS_LEAVE_PRIVATE("");
3181 }
3182
3183 void
3184 ia_css_debug_dump_stream_config_source(
3185         const struct ia_css_stream_config *config)
3186 {
3187         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3188         switch (config->mode) {
3189         case IA_CSS_INPUT_MODE_SENSOR:
3190         case IA_CSS_INPUT_MODE_BUFFERED_SENSOR:
3191                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n");
3192                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n",
3193                                 config->source.port.port);
3194                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n",
3195                                 config->source.port.num_lanes);
3196                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n",
3197                                 config->source.port.timeout);
3198                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n",
3199                                 config->source.port.compression);
3200                 break;
3201         case IA_CSS_INPUT_MODE_TPG:
3202                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n");
3203                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3204                                 config->source.tpg.id);
3205                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n",
3206                                 config->source.tpg.mode);
3207                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n",
3208                                 config->source.tpg.x_mask);
3209                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n",
3210                                 config->source.tpg.x_delta);
3211                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n",
3212                                 config->source.tpg.y_mask);
3213                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n",
3214                                 config->source.tpg.y_delta);
3215                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n",
3216                                 config->source.tpg.xy_mask);
3217                 break;
3218         case IA_CSS_INPUT_MODE_PRBS:
3219                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n");
3220                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n",
3221                                 config->source.prbs.id);
3222                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n",
3223                                 config->source.prbs.h_blank);
3224                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n",
3225                                 config->source.prbs.v_blank);
3226                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n",
3227                                 config->source.prbs.seed);
3228                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n",
3229                                 config->source.prbs.seed1);
3230                 break;
3231         default:
3232         case IA_CSS_INPUT_MODE_FIFO:
3233         case IA_CSS_INPUT_MODE_MEMORY:
3234                 break;
3235         }
3236 }
3237
3238 void
3239 ia_css_debug_dump_mipi_buffer_config(
3240         const struct ia_css_mipi_buffer_config *config)
3241 {
3242         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3243         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n",
3244                         config->size_mem_words);
3245         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n",
3246                         config->nof_mipi_buffers);
3247 }
3248
3249 void
3250 ia_css_debug_dump_metadata_config(
3251         const struct ia_css_metadata_config *config)
3252 {
3253         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3254         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n",
3255                         config->data_type);
3256         ia_css_debug_dump_resolution(&config->resolution, "resolution");
3257 }
3258
3259 void
3260 ia_css_debug_dump_stream_config(
3261         const struct ia_css_stream_config *config,
3262         int num_pipes)
3263 {
3264         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__);
3265         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes);
3266         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode);
3267         ia_css_debug_dump_stream_config_source(config);
3268         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n",
3269                         config->channel_id);
3270         ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res");
3271         ia_css_debug_dump_resolution(&config->input_config.effective_res, "effective_res");
3272         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n",
3273                         config->input_config.format);
3274         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n",
3275                         config->input_config.bayer_order);
3276         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n",
3277                         config->sensor_binning_factor);
3278         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n",
3279                         config->pixels_per_clock);
3280         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n",
3281                         config->online);
3282         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n",
3283                         config->init_num_cont_raw_buf);
3284         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,
3285                         "target_num_cont_raw_buf: %d\n",
3286                         config->target_num_cont_raw_buf);
3287         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n",
3288                         config->pack_raw_pixels);
3289         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n",
3290                         config->continuous);
3291         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n",
3292                         config->flash_gpio_pin);
3293         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n",
3294                         config->left_padding);
3295         ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config);
3296         ia_css_debug_dump_metadata_config(&config->metadata_config);
3297 }
3298
3299 /*
3300     Trace support.
3301
3302     This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details).
3303     Currently, support is only for SKC.
3304     To enable support for other platforms:
3305      - Allocate a buffer for tracing in DMEM. The longer the better.
3306      - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected.
3307      - Add trace points in the SP code wherever needed.
3308      - Enable the dump below with the required address and required adjustments.
3309            Dump is called at the end of ia_css_debug_dump_sp_state().
3310 */
3311
3312 /*
3313  dump_trace() : dump the trace points from DMEM2.
3314  for every trace point, the following are printed: index, major:minor and the 16-bit attached value.
3315  The routine looks for the first 0, and then prints from it cyclically.
3316  Data forma in DMEM2:
3317   first 4 DWORDS: header
3318    DWORD 0: data description
3319     byte 0: version
3320     byte 1: number of threads (for future use)
3321     byte 2+3: number ot TPs
3322    DWORD 1: command byte + data (for future use)
3323     byte 0: command
3324     byte 1-3: command signature
3325    DWORD 2-3: additional data (for future use)
3326   Following data is 4-byte oriented:
3327     byte 0:   major
3328         byte 1:   minor
3329         byte 2-3: data
3330 */
3331 #if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP
3332 #ifndef ISP2401
3333 static void debug_dump_one_trace(TRACE_CORE_ID proc_id)
3334 #else
3335 static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id)
3336 #endif
3337 {
3338 #if defined(HAS_TRACER_V2)
3339         uint32_t start_addr;
3340         uint32_t start_addr_data;
3341         uint32_t item_size;
3342 #ifndef ISP2401
3343         uint32_t tmp;
3344 #else
3345         uint8_t tid_val;
3346         enum TRACE_DUMP_FORMAT dump_format;
3347 #endif
3348         int i, j, max_trace_points, point_num, limit = -1;
3349         /* using a static buffer here as the driver has issues allocating memory */
3350         static uint32_t trace_read_buf[TRACE_BUFF_SIZE] = {0};
3351 #ifdef ISP2401
3352         static struct trace_header_t header;
3353         uint8_t *header_arr;
3354 #endif
3355
3356         /* read the header and parse it */
3357         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer ");
3358         switch (proc_id)
3359         {
3360         case TRACE_SP0_ID:
3361                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0");
3362                 start_addr = TRACE_SP0_ADDR;
3363                 start_addr_data = TRACE_SP0_DATA_ADDR;
3364                 item_size = TRACE_SP0_ITEM_SIZE;
3365                 max_trace_points = TRACE_SP0_MAX_POINTS;
3366                 break;
3367         case TRACE_SP1_ID:
3368                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1");
3369                 start_addr = TRACE_SP1_ADDR;
3370                 start_addr_data = TRACE_SP1_DATA_ADDR;
3371                 item_size = TRACE_SP1_ITEM_SIZE;
3372                 max_trace_points = TRACE_SP1_MAX_POINTS;
3373                 break;
3374         case TRACE_ISP_ID:
3375                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP");
3376                 start_addr = TRACE_ISP_ADDR;
3377                 start_addr_data = TRACE_ISP_DATA_ADDR;
3378                 item_size = TRACE_ISP_ITEM_SIZE;
3379                 max_trace_points = TRACE_ISP_MAX_POINTS;
3380                 break;
3381         default:
3382                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\ttraces are not supported for this processor ID - exiting\n");
3383                 return;
3384         }
3385 #ifndef ISP2401
3386         tmp = ia_css_device_load_uint32(start_addr);
3387         point_num = (tmp >> 16) & 0xFFFF;
3388 #endif
3389
3390 #ifndef ISP2401
3391         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, point_num);
3392         if ((tmp & 0xFF) != TRACER_VER) {
3393 #else
3394         /* Loading byte-by-byte as using the master routine had issues */
3395         header_arr = (uint8_t *)&header;
3396         for (i = 0; i < (int)sizeof(struct trace_header_t); i++)
3397                 header_arr[i] = ia_css_device_load_uint8(start_addr + (i));
3398
3399         point_num = header.max_tracer_points;
3400
3401         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, point_num);
3402         if ((header.version & 0xFF) != TRACER_VER) {
3403 #endif
3404                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n");
3405                 return;
3406         }
3407         if (point_num > max_trace_points) {
3408                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n");
3409                 return;
3410         }
3411         /* copy the TPs and find the first 0 */
3412         for (i = 0; i < point_num; i++) {
3413                 trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + (i * item_size));
3414                 if ((limit == (-1)) && (trace_read_buf[i] == 0))
3415                         limit = i;
3416         }
3417 #ifdef ISP2401
3418         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n");
3419         for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++)
3420                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\tT%d: %3d (%02x)  %6d (%04x)  %10d (%08x)\n", i,
3421                                 header.thr_status_byte[i], header.thr_status_byte[i],
3422                                 header.thr_status_word[i], header.thr_status_word[i],
3423                                 header.thr_status_dword[i], header.thr_status_dword[i]);
3424         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n");
3425         for (i = 0; i < MAX_SCRATCH_DATA; i++)
3426                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x)  ",
3427                         header.scratch_debug[i], header.scratch_debug[i]);
3428         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n");
3429
3430 #endif
3431         /* two 0s in the beginning: empty buffer */
3432         if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) {
3433                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n");
3434                 return;
3435         }
3436         /* no overrun: start from 0 */
3437         if ((limit == point_num-1) ||         /* first 0 is at the end - border case */
3438             (trace_read_buf[limit+1] == 0))   /* did not make a full cycle after the memset */
3439                 limit = 0;
3440         /* overrun: limit is the first non-zero after the first zero */
3441         else
3442                 limit++;
3443
3444         /* print the TPs */
3445         for (i = 0; i < point_num; i++) {
3446                 j = (limit + i) % point_num;
3447                 if (trace_read_buf[j])
3448                 {
3449 #ifndef ISP2401
3450                         TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3451 #else
3452
3453                         tid_val = FIELD_TID_UNPACK(trace_read_buf[j]);
3454                         dump_format = TRACE_DUMP_FORMAT_POINT;
3455
3456                         /*
3457                          * When tid value is 111b, the data will be interpreted differently:
3458                          * tid val is ignored, major field contains 2 bits (msb) for format type
3459                          */
3460                         if (tid_val == FIELD_TID_SEL_FORMAT_PAT) {
3461                                 dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]);
3462                         }
3463 #endif
3464                         switch (dump_format)
3465                         {
3466                         case TRACE_DUMP_FORMAT_POINT:
3467                                 ia_css_debug_dtrace(
3468 #ifndef ISP2401
3469                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d %d:%d value - %d\n",
3470                                                 j, FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3471 #else
3472                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d T%d %d:%d value - %x (%d)\n",
3473                                                 j,
3474                                                 tid_val,
3475                                                 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3476 #endif
3477                                                 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3478 #ifdef ISP2401
3479                                                 FIELD_VALUE_UNPACK(trace_read_buf[j]),
3480 #endif
3481                                                 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3482                                 break;
3483 #ifndef ISP2401
3484                         case TRACE_DUMP_FORMAT_VALUE24_HEX:
3485 #else
3486                         case TRACE_DUMP_FORMAT_POINT_NO_TID:
3487 #endif
3488                                 ia_css_debug_dtrace(
3489 #ifndef ISP2401
3490                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d, %d, 24bit value %x H\n",
3491 #else
3492                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d %d:%d value - %x (%d)\n",
3493 #endif
3494                                                 j,
3495 #ifndef ISP2401
3496                                                 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3497                                                 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3498 #else
3499                                                 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3500                                                 FIELD_MINOR_UNPACK(trace_read_buf[j]),
3501                                                 FIELD_VALUE_UNPACK(trace_read_buf[j]),
3502                                                 FIELD_VALUE_UNPACK(trace_read_buf[j]));
3503 #endif
3504                                 break;
3505 #ifndef ISP2401
3506                         case TRACE_DUMP_FORMAT_VALUE24_DEC:
3507 #else
3508                         case TRACE_DUMP_FORMAT_VALUE24:
3509 #endif
3510                                 ia_css_debug_dtrace(
3511 #ifndef ISP2401
3512                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d, %d, 24bit value %d D\n",
3513 #else
3514                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d, %d, 24bit value %x (%d)\n",
3515 #endif
3516                                                 j,
3517                                                 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3518 #ifdef ISP2401
3519                                                 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3520                                                 FIELD_VALUE_24_UNPACK(trace_read_buf[j]),
3521 #endif
3522                                                 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3523                                 break;
3524 #ifdef ISP2401
3525
3526 #endif
3527                         case TRACE_DUMP_FORMAT_VALUE24_TIMING:
3528                                 ia_css_debug_dtrace(
3529                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d, %d, timing %x\n",
3530                                                 j,
3531 #ifndef ISP2401
3532                                                 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3533 #else
3534                                                 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3535 #endif
3536                                                 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3537                                 break;
3538                         case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA:
3539                                 ia_css_debug_dtrace(
3540                                                 IA_CSS_DEBUG_TRACE,     "\t\t%d, %d, timing delta %x\n",
3541                                                 j,
3542 #ifndef ISP2401
3543                                                 FIELD_MAJOR_UNPACK(trace_read_buf[j]),
3544 #else
3545                                                 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]),
3546 #endif
3547                                                 FIELD_VALUE_24_UNPACK(trace_read_buf[j]));
3548                                 break;
3549                         default:
3550                                 ia_css_debug_dtrace(
3551                                                 IA_CSS_DEBUG_TRACE,
3552                                                 "no such trace dump format %d",
3553 #ifndef ISP2401
3554                                                 FIELD_FORMAT_UNPACK(trace_read_buf[j]));
3555 #else
3556                                                 dump_format);
3557 #endif
3558                                 break;
3559                         }
3560                 }
3561         }
3562 #else
3563         (void)proc_id;
3564 #endif /* HAS_TRACER_V2 */
3565 }
3566 #endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */
3567
3568 void ia_css_debug_dump_trace(void)
3569 {
3570 #if TRACE_ENABLE_SP0
3571         debug_dump_one_trace(TRACE_SP0_ID);
3572 #endif
3573 #if TRACE_ENABLE_SP1
3574         debug_dump_one_trace(TRACE_SP1_ID);
3575 #endif
3576 #if TRACE_ENABLE_ISP
3577         debug_dump_one_trace(TRACE_ISP_ID);
3578 #endif
3579 }
3580
3581 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401)
3582 /* Tagger state dump function. The tagger is only available when the CSS
3583  * contains an input system (2400 or 2401). */
3584 void ia_css_debug_tagger_state(void)
3585 {
3586         unsigned int i;
3587         unsigned int HIVE_ADDR_tagger_frames;
3588         ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER];
3589
3590         HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr;
3591
3592         /* This variable is not used in crun */
3593         (void)HIVE_ADDR_tagger_frames;
3594
3595         /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */
3596         sp_dmem_load(SP0_ID,
3597                      (unsigned int)sp_address_of(tagger_frames),
3598                      tbuf_frames,
3599                      sizeof(tbuf_frames));
3600
3601         ia_css_debug_dtrace(2, "Tagger Info:\n");
3602         for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) {
3603                 ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n",
3604                                 i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock);
3605         }
3606
3607 }
3608 #endif /* defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) */
3609
3610 #ifdef ISP2401
3611 void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps)
3612 {
3613         unsigned int pc;
3614         unsigned int i;
3615         hrt_data sc = sp_ctrl_load(id, SP_SC_REG);
3616         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc);
3617         sc = sp_ctrl_load(id, SP_CTRL_SINK_REG);
3618         ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc);
3619         for (i = 0; i < num_of_dumps; i++) {
3620                 pc = sp_ctrl_load(id, SP_PC_REG);
3621                 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc);
3622         }
3623 }
3624 #endif
3625
3626 #if defined(HRT_SCHED) || defined(SH_CSS_DEBUG_SPMEM_DUMP_SUPPORT)
3627 #include "spmem_dump.c"
3628 #endif