1 /***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 #include <linux/module.h>
22 #include <linux/version.h>
23 #include <linux/stringify.h>
24 #include <linux/delay.h>
25 #include <linux/kthread.h>
26 #include <linux/slab.h>
27 #include <media/v4l2-dev.h>
28 #include <media/v4l2-ioctl.h>
29 #include <media/v4l2-common.h>
30 #include <media/videobuf2-dma-contig.h>
32 #include "dt3155v4l.h"
34 #define DT3155_VENDOR_ID 0x8086
35 #define DT3155_DEVICE_ID 0x1223
37 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
38 #define DT3155_CHUNK_SIZE (1U << 22)
40 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
42 #define DT3155_BUF_SIZE (768 * 576)
44 #ifdef CONFIG_DT3155_STREAMING
45 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
47 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
50 /* global initializers (for all boards) */
51 #ifdef CONFIG_DT3155_CCIR
52 static const u8 csr2_init = VT_50HZ;
53 #define DT3155_CURRENT_NORM V4L2_STD_625_50
54 static const unsigned int img_width = 768;
55 static const unsigned int img_height = 576;
56 static const unsigned int frames_per_sec = 25;
57 static const struct v4l2_fmtdesc frame_std[] = {
60 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
62 .description = "CCIR/50Hz 8 bits gray",
63 .pixelformat = V4L2_PIX_FMT_GREY,
67 static const u8 csr2_init = VT_60HZ;
68 #define DT3155_CURRENT_NORM V4L2_STD_525_60
69 static const unsigned int img_width = 640;
70 static const unsigned int img_height = 480;
71 static const unsigned int frames_per_sec = 30;
72 static const struct v4l2_fmtdesc frame_std[] = {
75 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
77 .description = "RS-170/60Hz 8 bits gray",
78 .pixelformat = V4L2_PIX_FMT_GREY,
83 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
85 static u8 config_init = ACQ_MODE_EVEN;
88 * read_i2c_reg - reads an internal i2c register
90 * @addr: dt3155 mmio base address
91 * @index: index (internal address) of register to read
92 * @data: pointer to byte the read data will be placed in
94 * returns: zero on success or error code
96 * This function starts reading the specified (by index) register
97 * and busy waits for the process to finish. The result is placed
98 * in a byte pointed by data.
101 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
105 iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
107 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
108 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
109 return -EIO; /* error: NEW_CYCLE not cleared */
110 tmp = ioread32(addr + IIC_CSR1);
111 if (tmp & DIRECT_ABORT) {
112 /* reset DIRECT_ABORT bit */
113 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
114 return -EIO; /* error: DIRECT_ABORT set */
121 * write_i2c_reg - writes to an internal i2c register
123 * @addr: dt3155 mmio base address
124 * @index: index (internal address) of register to read
125 * @data: data to be written
127 * returns: zero on success or error code
129 * This function starts writting the specified (by index) register
130 * and busy waits for the process to finish.
133 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
137 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
139 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
140 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
141 return -EIO; /* error: NEW_CYCLE not cleared */
142 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
143 /* reset DIRECT_ABORT bit */
144 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
145 return -EIO; /* error: DIRECT_ABORT set */
151 * write_i2c_reg_nowait - writes to an internal i2c register
153 * @addr: dt3155 mmio base address
154 * @index: index (internal address) of register to read
155 * @data: data to be written
157 * This function starts writting the specified (by index) register
160 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
164 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
169 * wait_i2c_reg - waits the read/write to finish
171 * @addr: dt3155 mmio base address
173 * returns: zero on success or error code
175 * This function waits reading/writting to finish.
177 static int wait_i2c_reg(void __iomem *addr)
179 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
180 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
181 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
182 return -EIO; /* error: NEW_CYCLE not cleared */
183 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
184 /* reset DIRECT_ABORT bit */
185 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
186 return -EIO; /* error: DIRECT_ABORT set */
192 dt3155_start_acq(struct dt3155_priv *pd)
194 struct vb2_buffer *vb = pd->curr_buf;
197 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
198 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
199 iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
200 iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
201 iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
202 /* enable interrupts, clear all irq flags */
203 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
204 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
205 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
206 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
208 wait_i2c_reg(pd->regs);
209 write_i2c_reg(pd->regs, CONFIG, pd->config);
210 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
211 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
213 /* start the board */
214 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
215 return 0; /* success */
219 * driver-specific callbacks (vb2_ops)
222 dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
223 unsigned int *num_buffers, unsigned int *num_planes,
224 unsigned int sizes[], void *alloc_ctxs[])
227 struct dt3155_priv *pd = vb2_get_drv_priv(q);
230 if (*num_buffers == 0)
233 sizes[0] = img_width * img_height;
234 if (pd->q->alloc_ctx[0])
236 ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
239 pd->q->alloc_ctx[0] = ret;
244 dt3155_wait_prepare(struct vb2_queue *q)
246 struct dt3155_priv *pd = vb2_get_drv_priv(q);
248 mutex_unlock(pd->vdev->lock);
252 dt3155_wait_finish(struct vb2_queue *q)
254 struct dt3155_priv *pd = vb2_get_drv_priv(q);
256 mutex_lock(pd->vdev->lock);
260 dt3155_buf_prepare(struct vb2_buffer *vb)
262 vb2_set_plane_payload(vb, 0, img_width * img_height);
267 dt3155_stop_streaming(struct vb2_queue *q)
269 struct dt3155_priv *pd = vb2_get_drv_priv(q);
270 struct vb2_buffer *vb;
272 spin_lock_irq(&pd->lock);
273 while (!list_empty(&pd->dmaq)) {
274 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
275 list_del(&vb->done_entry);
276 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
278 spin_unlock_irq(&pd->lock);
279 msleep(45); /* irq hendler will stop the hardware */
284 dt3155_buf_queue(struct vb2_buffer *vb)
286 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
288 /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */
289 spin_lock_irq(&pd->lock);
291 list_add_tail(&vb->done_entry, &pd->dmaq);
294 dt3155_start_acq(pd);
296 spin_unlock_irq(&pd->lock);
299 * end driver-specific callbacks
302 const struct vb2_ops q_ops = {
303 .queue_setup = dt3155_queue_setup,
304 .wait_prepare = dt3155_wait_prepare,
305 .wait_finish = dt3155_wait_finish,
306 .buf_prepare = dt3155_buf_prepare,
307 .stop_streaming = dt3155_stop_streaming,
308 .buf_queue = dt3155_buf_queue,
312 dt3155_irq_handler_even(int irq, void *dev_id)
314 struct dt3155_priv *ipd = dev_id;
315 struct vb2_buffer *ivb;
319 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
321 return IRQ_NONE; /* not our irq */
322 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
323 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
324 ipd->regs + INT_CSR);
326 return IRQ_HANDLED; /* start of field irq */
328 if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
329 ipd->stats.start_before_end++;
330 /* check for corrupted fields */
331 /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
332 /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
333 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
335 ipd->stats.corrupted_fields++;
336 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
337 FLD_DN_ODD | FLD_DN_EVEN |
338 CAP_CONT_EVEN | CAP_CONT_ODD,
343 spin_lock(&ipd->lock);
345 v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp);
346 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
347 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
350 if (!ipd->q->streaming || list_empty(&ipd->dmaq))
352 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
353 list_del(&ivb->done_entry);
355 dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
356 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
357 iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
358 iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
359 iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
361 /* enable interrupts, clear all irq flags */
362 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
363 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
364 spin_unlock(&ipd->lock);
368 ipd->curr_buf = NULL;
370 write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
371 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
372 FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
373 /* disable interrupts, clear all irq flags */
374 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
375 spin_unlock(&ipd->lock);
380 dt3155_open(struct file *filp)
383 struct dt3155_priv *pd = video_drvdata(filp);
385 if (mutex_lock_interruptible(&pd->mux))
388 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
391 goto err_alloc_queue;
393 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
394 pd->q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
395 pd->q->io_modes = VB2_READ | VB2_MMAP;
397 pd->q->mem_ops = &vb2_dma_contig_memops;
398 pd->q->drv_priv = pd;
401 ret = vb2_queue_init(pd->q);
403 goto err_request_irq;
404 INIT_LIST_HEAD(&pd->dmaq);
405 spin_lock_init(&pd->lock);
406 /* disable all irqs, clear all irq flags */
407 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
409 ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
410 IRQF_SHARED, DT3155_NAME, pd);
412 goto err_request_irq;
415 mutex_unlock(&pd->mux);
416 return 0; /* success */
421 mutex_unlock(&pd->mux);
426 dt3155_release(struct file *filp)
428 struct dt3155_priv *pd = video_drvdata(filp);
430 mutex_lock(&pd->mux);
432 BUG_ON(pd->users < 0);
434 vb2_queue_release(pd->q);
435 free_irq(pd->pdev->irq, pd);
436 if (pd->q->alloc_ctx[0])
437 vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
441 mutex_unlock(&pd->mux);
446 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
448 struct dt3155_priv *pd = video_drvdata(filp);
451 if (mutex_lock_interruptible(&pd->mux))
453 res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
454 mutex_unlock(&pd->mux);
459 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
461 struct dt3155_priv *pd = video_drvdata(filp);
464 mutex_lock(&pd->mux);
465 res = vb2_poll(pd->q, filp, polltbl);
466 mutex_unlock(&pd->mux);
471 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
473 struct dt3155_priv *pd = video_drvdata(filp);
476 if (mutex_lock_interruptible(&pd->mux))
478 res = vb2_mmap(pd->q, vma);
479 mutex_unlock(&pd->mux);
483 static const struct v4l2_file_operations dt3155_fops = {
484 .owner = THIS_MODULE,
486 .release = dt3155_release,
489 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
494 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
496 struct dt3155_priv *pd = video_drvdata(filp);
498 return vb2_streamon(pd->q, type);
502 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
504 struct dt3155_priv *pd = video_drvdata(filp);
506 return vb2_streamoff(pd->q, type);
510 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
512 struct dt3155_priv *pd = video_drvdata(filp);
514 strcpy(cap->driver, DT3155_NAME);
515 strcpy(cap->card, DT3155_NAME " frame grabber");
516 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
518 KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
519 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
520 DT3155_CAPTURE_METHOD;
525 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
527 if (f->index >= NUM_OF_FORMATS)
529 *f = frame_std[f->index];
534 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
536 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
538 f->fmt.pix.width = img_width;
539 f->fmt.pix.height = img_height;
540 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
541 f->fmt.pix.field = V4L2_FIELD_NONE;
542 f->fmt.pix.bytesperline = f->fmt.pix.width;
543 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
544 f->fmt.pix.colorspace = 0;
550 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
552 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
554 if (f->fmt.pix.width == img_width &&
555 f->fmt.pix.height == img_height &&
556 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
557 f->fmt.pix.field == V4L2_FIELD_NONE &&
558 f->fmt.pix.bytesperline == f->fmt.pix.width &&
559 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
566 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
568 return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
572 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
574 struct dt3155_priv *pd = video_drvdata(filp);
576 return vb2_reqbufs(pd->q, b);
580 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
582 struct dt3155_priv *pd = video_drvdata(filp);
584 return vb2_querybuf(pd->q, b);
588 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
590 struct dt3155_priv *pd = video_drvdata(filp);
592 return vb2_qbuf(pd->q, b);
596 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
598 struct dt3155_priv *pd = video_drvdata(filp);
600 return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
604 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
606 *norm = DT3155_CURRENT_NORM;
611 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
613 *norm = DT3155_CURRENT_NORM;
618 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id norm)
620 if (norm & DT3155_CURRENT_NORM)
626 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
630 strcpy(input->name, "Coax in");
631 input->type = V4L2_INPUT_TYPE_CAMERA;
633 * FIXME: input->std = 0 according to v4l2 API
634 * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
635 * should return -EINVAL
637 input->std = DT3155_CURRENT_NORM;
638 input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
643 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
650 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
658 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
660 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
662 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
663 parms->parm.capture.capturemode = 0;
664 parms->parm.capture.timeperframe.numerator = 1001;
665 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
666 parms->parm.capture.extendedmode = 0;
667 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
672 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
674 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
676 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
677 parms->parm.capture.capturemode = 0;
678 parms->parm.capture.timeperframe.numerator = 1001;
679 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
680 parms->parm.capture.extendedmode = 0;
681 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
685 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
686 .vidioc_streamon = dt3155_ioc_streamon,
687 .vidioc_streamoff = dt3155_ioc_streamoff,
688 .vidioc_querycap = dt3155_ioc_querycap,
690 .vidioc_g_priority = dt3155_ioc_g_priority,
691 .vidioc_s_priority = dt3155_ioc_s_priority,
693 .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
694 .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
695 .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
696 .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
697 .vidioc_reqbufs = dt3155_ioc_reqbufs,
698 .vidioc_querybuf = dt3155_ioc_querybuf,
699 .vidioc_qbuf = dt3155_ioc_qbuf,
700 .vidioc_dqbuf = dt3155_ioc_dqbuf,
701 .vidioc_querystd = dt3155_ioc_querystd,
702 .vidioc_g_std = dt3155_ioc_g_std,
703 .vidioc_s_std = dt3155_ioc_s_std,
704 .vidioc_enum_input = dt3155_ioc_enum_input,
705 .vidioc_g_input = dt3155_ioc_g_input,
706 .vidioc_s_input = dt3155_ioc_s_input,
708 .vidioc_queryctrl = dt3155_ioc_queryctrl,
709 .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
710 .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
711 .vidioc_querymenu = dt3155_ioc_querymenu,
712 .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
713 .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
715 .vidioc_g_parm = dt3155_ioc_g_parm,
716 .vidioc_s_parm = dt3155_ioc_s_parm,
718 .vidioc_cropcap = dt3155_ioc_cropcap,
719 .vidioc_g_crop = dt3155_ioc_g_crop,
720 .vidioc_s_crop = dt3155_ioc_s_crop,
721 .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
722 .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
727 dt3155_init_board(struct pci_dev *pdev)
729 struct dt3155_priv *pd = pci_get_drvdata(pdev);
735 pci_set_master(pdev); /* dt3155 needs it */
737 /* resetting the adapter */
738 iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
743 /* initializing adaper registers */
744 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
746 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
747 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
748 iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
749 iowrite32(0x00000103, pd->regs + XFER_MODE);
750 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
751 iowrite32(0, pd->regs + INT_CSR);
752 iowrite32(1, pd->regs + EVEN_FLD_MASK);
753 iowrite32(1, pd->regs + ODD_FLD_MASK);
754 iowrite32(0, pd->regs + MASK_LENGTH);
755 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
756 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
759 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
760 read_i2c_reg(pd->regs, DT_ID, &tmp);
761 if (tmp != DT3155_ID)
764 /* initialize AD LUT */
765 write_i2c_reg(pd->regs, AD_ADDR, 0);
766 for (i = 0; i < 256; i++)
767 write_i2c_reg(pd->regs, AD_LUT, i);
769 /* initialize ADC references */
770 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
771 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
772 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
773 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
774 write_i2c_reg(pd->regs, AD_CMD, 34);
775 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
776 write_i2c_reg(pd->regs, AD_CMD, 0);
778 /* initialize PM LUT */
779 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
780 for (i = 0; i < 256; i++) {
781 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
782 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
784 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
785 for (i = 0; i < 256; i++) {
786 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
787 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
789 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
791 /* select channel 1 for input and set sync level */
792 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
793 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
795 /* allocate memory, and initialize the DMA machine */
796 buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
800 iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
801 iowrite32(buf_dma, pd->regs + ODD_DMA_START);
802 iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
803 iowrite32(0, pd->regs + ODD_DMA_STRIDE);
805 /* Perform a pseudo even field acquire */
806 iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
807 write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
808 write_i2c_reg(pd->regs, CONFIG, pd->config);
809 write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
810 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
812 read_i2c_reg(pd->regs, CSR2, &tmp);
813 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
814 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
815 write_i2c_reg(pd->regs, CSR2, pd->csr2);
816 iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
818 /* deallocate memory */
819 dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
825 static struct video_device dt3155_vdev = {
827 .fops = &dt3155_fops,
828 .ioctl_ops = &dt3155_ioctl_ops,
830 .release = video_device_release,
831 .tvnorms = DT3155_CURRENT_NORM,
834 /* same as in drivers/base/dma-coherent.c */
835 struct dma_coherent_mem {
837 dma_addr_t device_base;
840 unsigned long *bitmap;
844 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
846 struct dma_coherent_mem *mem;
848 int pages = size >> PAGE_SHIFT;
849 int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
851 if ((flags & DMA_MEMORY_MAP) == 0)
858 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
861 mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
864 goto err_alloc_coherent;
865 mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
869 /* coherent_dma_mask is already set to 32 bits */
870 mem->device_base = dev_base;
874 return DMA_MEMORY_MAP;
877 dma_free_coherent(dev, size, mem->virt_base, dev_base);
885 dt3155_free_coherent(struct device *dev)
887 struct dma_coherent_mem *mem = dev->dma_mem;
892 dma_free_coherent(dev, mem->size << PAGE_SHIFT,
893 mem->virt_base, mem->device_base);
899 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
902 struct dt3155_priv *pd;
904 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
907 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
910 pd->vdev = video_device_alloc();
912 goto err_video_device_alloc;
913 *pd->vdev = dt3155_vdev;
914 pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */
915 video_set_drvdata(pd->vdev, pd); /* for use in video_fops */
918 INIT_LIST_HEAD(&pd->dmaq);
919 mutex_init(&pd->mux);
920 pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
921 spin_lock_init(&pd->lock);
922 pd->csr2 = csr2_init;
923 pd->config = config_init;
924 err = pci_enable_device(pdev);
927 err = pci_request_region(pdev, 0, pci_name(pdev));
930 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
935 err = dt3155_init_board(pdev);
938 err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
941 if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
943 dev_info(&pdev->dev, "preallocated 8 buffers\n");
944 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor);
945 return 0; /* success */
948 pci_iounmap(pdev, pd->regs);
950 pci_release_region(pdev, 0);
952 pci_disable_device(pdev);
954 video_device_release(pd->vdev);
955 err_video_device_alloc:
961 dt3155_remove(struct pci_dev *pdev)
963 struct dt3155_priv *pd = pci_get_drvdata(pdev);
965 dt3155_free_coherent(&pdev->dev);
966 video_unregister_device(pd->vdev);
967 pci_iounmap(pdev, pd->regs);
968 pci_release_region(pdev, 0);
969 pci_disable_device(pdev);
971 * video_device_release() is invoked automatically
972 * see: struct video_device dt3155_vdev
977 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
978 { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
979 { 0, /* zero marks the end */ },
981 MODULE_DEVICE_TABLE(pci, pci_ids);
983 static struct pci_driver pci_driver = {
986 .probe = dt3155_probe,
987 .remove = dt3155_remove,
990 module_pci_driver(pci_driver);
992 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
993 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
994 MODULE_VERSION(DT3155_VERSION);
995 MODULE_LICENSE("GPL");