2 * TI OMAP4 ISS V4L2 Driver - CSI PHY module
4 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <media/v4l2-common.h>
16 #include <linux/v4l2-mediabus.h>
24 * csi2_if_enable - Enable CSI2 Receiver interface.
25 * @enable: enable flag
28 static void csi2_if_enable(struct iss_csi2_device *csi2, u8 enable)
30 struct iss_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
32 iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTRL, CSI2_CTRL_IF_EN,
33 enable ? CSI2_CTRL_IF_EN : 0);
35 currctrl->if_enable = enable;
39 * csi2_recv_config - CSI2 receiver module configuration.
40 * @currctrl: iss_csi2_ctrl_cfg structure
43 static void csi2_recv_config(struct iss_csi2_device *csi2,
44 struct iss_csi2_ctrl_cfg *currctrl)
48 if (currctrl->frame_mode)
49 reg |= CSI2_CTRL_FRAME;
51 reg &= ~CSI2_CTRL_FRAME;
53 if (currctrl->vp_clk_enable)
54 reg |= CSI2_CTRL_VP_CLK_EN;
56 reg &= ~CSI2_CTRL_VP_CLK_EN;
58 if (currctrl->vp_only_enable)
59 reg |= CSI2_CTRL_VP_ONLY_EN;
61 reg &= ~CSI2_CTRL_VP_ONLY_EN;
63 reg &= ~CSI2_CTRL_VP_OUT_CTRL_MASK;
64 reg |= currctrl->vp_out_ctrl << CSI2_CTRL_VP_OUT_CTRL_SHIFT;
66 if (currctrl->ecc_enable)
67 reg |= CSI2_CTRL_ECC_EN;
69 reg &= ~CSI2_CTRL_ECC_EN;
72 * Set MFlag assertion boundaries to:
73 * Low: 4/8 of FIFO size
74 * High: 6/8 of FIFO size
76 reg &= ~(CSI2_CTRL_MFLAG_LEVH_MASK | CSI2_CTRL_MFLAG_LEVL_MASK);
77 reg |= (2 << CSI2_CTRL_MFLAG_LEVH_SHIFT) |
78 (4 << CSI2_CTRL_MFLAG_LEVL_SHIFT);
80 /* Generation of 16x64-bit bursts (Recommended) */
81 reg |= CSI2_CTRL_BURST_SIZE_EXPAND;
83 /* Do Non-Posted writes (Recommended) */
84 reg |= CSI2_CTRL_NON_POSTED_WRITE;
87 * Enforce Little endian for all formats, including:
88 * YUV4:2:2 8-bit and YUV4:2:0 Legacy
90 reg |= CSI2_CTRL_ENDIANNESS;
92 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTRL, reg);
95 static const unsigned int csi2_input_fmts[] = {
96 MEDIA_BUS_FMT_SGRBG10_1X10,
97 MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
98 MEDIA_BUS_FMT_SRGGB10_1X10,
99 MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
100 MEDIA_BUS_FMT_SBGGR10_1X10,
101 MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
102 MEDIA_BUS_FMT_SGBRG10_1X10,
103 MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
104 MEDIA_BUS_FMT_SBGGR8_1X8,
105 MEDIA_BUS_FMT_SGBRG8_1X8,
106 MEDIA_BUS_FMT_SGRBG8_1X8,
107 MEDIA_BUS_FMT_SRGGB8_1X8,
108 MEDIA_BUS_FMT_UYVY8_1X16,
109 MEDIA_BUS_FMT_YUYV8_1X16,
112 /* To set the format on the CSI2 requires a mapping function that takes
113 * the following inputs:
114 * - 3 different formats (at this time)
115 * - 2 destinations (mem, vp+mem) (vp only handled separately)
116 * - 2 decompression options (on, off)
117 * Output should be CSI2 frame format code
118 * Array indices as follows: [format][dest][decompr]
119 * Not all combinations are valid. 0 means invalid.
121 static const u16 __csi2_fmt_map[][2][2] = {
124 /* Output to memory */
126 /* No DPCM decompression */
127 CSI2_PIX_FMT_RAW10_EXP16,
128 /* DPCM decompression */
133 /* No DPCM decompression */
134 CSI2_PIX_FMT_RAW10_EXP16_VP,
135 /* DPCM decompression */
139 /* RAW10 DPCM8 formats */
141 /* Output to memory */
143 /* No DPCM decompression */
144 CSI2_USERDEF_8BIT_DATA1,
145 /* DPCM decompression */
146 CSI2_USERDEF_8BIT_DATA1_DPCM10,
150 /* No DPCM decompression */
151 CSI2_PIX_FMT_RAW8_VP,
152 /* DPCM decompression */
153 CSI2_USERDEF_8BIT_DATA1_DPCM10_VP,
158 /* Output to memory */
160 /* No DPCM decompression */
162 /* DPCM decompression */
167 /* No DPCM decompression */
168 CSI2_PIX_FMT_RAW8_VP,
169 /* DPCM decompression */
175 /* Output to memory */
177 /* No DPCM decompression */
178 CSI2_PIX_FMT_YUV422_8BIT,
179 /* DPCM decompression */
184 /* No DPCM decompression */
185 CSI2_PIX_FMT_YUV422_8BIT_VP16,
186 /* DPCM decompression */
193 * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
194 * @csi2: ISS CSI2 device
196 * Returns CSI2 physical format id
198 static u16 csi2_ctx_map_format(struct iss_csi2_device *csi2)
200 const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
204 case MEDIA_BUS_FMT_SGRBG10_1X10:
205 case MEDIA_BUS_FMT_SRGGB10_1X10:
206 case MEDIA_BUS_FMT_SBGGR10_1X10:
207 case MEDIA_BUS_FMT_SGBRG10_1X10:
210 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
211 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
212 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
213 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
216 case MEDIA_BUS_FMT_SBGGR8_1X8:
217 case MEDIA_BUS_FMT_SGBRG8_1X8:
218 case MEDIA_BUS_FMT_SGRBG8_1X8:
219 case MEDIA_BUS_FMT_SRGGB8_1X8:
222 case MEDIA_BUS_FMT_UYVY8_1X16:
223 case MEDIA_BUS_FMT_YUYV8_1X16:
227 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
232 if (!(csi2->output & CSI2_OUTPUT_IPIPEIF) &&
233 !(csi2->output & CSI2_OUTPUT_MEMORY)) {
234 /* Neither output enabled is a valid combination */
235 return CSI2_PIX_FMT_OTHERS;
238 /* If we need to skip frames at the beginning of the stream disable the
239 * video port to avoid sending the skipped frames to the IPIPEIF.
241 destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
243 return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress];
247 * csi2_set_outaddr - Set memory address to save output image
248 * @csi2: Pointer to ISS CSI2a device.
249 * @addr: 32-bit memory address aligned on 32 byte boundary.
251 * Sets the memory address where the output will be saved.
253 * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
256 static void csi2_set_outaddr(struct iss_csi2_device *csi2, u32 addr)
258 struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[0];
260 ctx->ping_addr = addr;
261 ctx->pong_addr = addr;
262 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
264 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
269 * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
270 * be enabled by CSI2.
271 * @format_id: mapped format id
274 static inline int is_usr_def_mapping(u32 format_id)
276 return (format_id & 0xf0) == 0x40 ? 1 : 0;
280 * csi2_ctx_enable - Enable specified CSI2 context
281 * @ctxnum: Context number, valid between 0 and 7 values.
285 static void csi2_ctx_enable(struct iss_csi2_device *csi2, u8 ctxnum, u8 enable)
287 struct iss_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
290 reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum));
293 unsigned int skip = 0;
295 if (csi2->frame_skip)
296 skip = csi2->frame_skip;
297 else if (csi2->output & CSI2_OUTPUT_MEMORY)
300 reg &= ~CSI2_CTX_CTRL1_COUNT_MASK;
301 reg |= CSI2_CTX_CTRL1_COUNT_UNLOCK
302 | (skip << CSI2_CTX_CTRL1_COUNT_SHIFT)
303 | CSI2_CTX_CTRL1_CTX_EN;
305 reg &= ~CSI2_CTX_CTRL1_CTX_EN;
308 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctxnum), reg);
309 ctx->enabled = enable;
313 * csi2_ctx_config - CSI2 context configuration.
314 * @ctx: context configuration
317 static void csi2_ctx_config(struct iss_csi2_device *csi2,
318 struct iss_csi2_ctx_cfg *ctx)
324 /* Set up CSI2_CTx_CTRL1 */
325 if (ctx->eof_enabled)
326 reg = CSI2_CTX_CTRL1_EOF_EN;
328 if (ctx->eol_enabled)
329 reg |= CSI2_CTX_CTRL1_EOL_EN;
331 if (ctx->checksum_enabled)
332 reg |= CSI2_CTX_CTRL1_CS_EN;
334 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL1(ctx->ctxnum), reg);
336 /* Set up CSI2_CTx_CTRL2 */
337 reg = ctx->virtual_id << CSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
338 reg |= ctx->format_id << CSI2_CTX_CTRL2_FORMAT_SHIFT;
340 if (ctx->dpcm_decompress && ctx->dpcm_predictor)
341 reg |= CSI2_CTX_CTRL2_DPCM_PRED;
343 if (is_usr_def_mapping(ctx->format_id))
344 reg |= 2 << CSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
346 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL2(ctx->ctxnum), reg);
348 /* Set up CSI2_CTx_CTRL3 */
349 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_CTRL3(ctx->ctxnum),
350 ctx->alpha << CSI2_CTX_CTRL3_ALPHA_SHIFT);
352 /* Set up CSI2_CTx_DAT_OFST */
353 iss_reg_update(csi2->iss, csi2->regs1, CSI2_CTX_DAT_OFST(ctx->ctxnum),
354 CSI2_CTX_DAT_OFST_MASK, ctx->data_offset);
356 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PING_ADDR(ctx->ctxnum),
358 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_PONG_ADDR(ctx->ctxnum),
363 * csi2_timing_config - CSI2 timing configuration.
364 * @timing: csi2_timing_cfg structure
366 static void csi2_timing_config(struct iss_csi2_device *csi2,
367 struct iss_csi2_timing_cfg *timing)
371 reg = iss_reg_read(csi2->iss, csi2->regs1, CSI2_TIMING);
373 if (timing->force_rx_mode)
374 reg |= CSI2_TIMING_FORCE_RX_MODE_IO1;
376 reg &= ~CSI2_TIMING_FORCE_RX_MODE_IO1;
378 if (timing->stop_state_16x)
379 reg |= CSI2_TIMING_STOP_STATE_X16_IO1;
381 reg &= ~CSI2_TIMING_STOP_STATE_X16_IO1;
383 if (timing->stop_state_4x)
384 reg |= CSI2_TIMING_STOP_STATE_X4_IO1;
386 reg &= ~CSI2_TIMING_STOP_STATE_X4_IO1;
388 reg &= ~CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK;
389 reg |= timing->stop_state_counter <<
390 CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT;
392 iss_reg_write(csi2->iss, csi2->regs1, CSI2_TIMING, reg);
396 * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
397 * @enable: Enable/disable CSI2 Context interrupts
399 static void csi2_irq_ctx_set(struct iss_csi2_device *csi2, int enable)
401 const u32 mask = CSI2_CTX_IRQ_FE | CSI2_CTX_IRQ_FS;
404 for (i = 0; i < 8; i++) {
405 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(i),
408 iss_reg_set(csi2->iss, csi2->regs1,
409 CSI2_CTX_IRQENABLE(i), mask);
411 iss_reg_clr(csi2->iss, csi2->regs1,
412 CSI2_CTX_IRQENABLE(i), mask);
417 * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
418 * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
420 static void csi2_irq_complexio1_set(struct iss_csi2_device *csi2, int enable)
424 reg = CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT |
425 CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER |
426 CSI2_COMPLEXIO_IRQ_STATEULPM5 |
427 CSI2_COMPLEXIO_IRQ_ERRCONTROL5 |
428 CSI2_COMPLEXIO_IRQ_ERRESC5 |
429 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5 |
430 CSI2_COMPLEXIO_IRQ_ERRSOTHS5 |
431 CSI2_COMPLEXIO_IRQ_STATEULPM4 |
432 CSI2_COMPLEXIO_IRQ_ERRCONTROL4 |
433 CSI2_COMPLEXIO_IRQ_ERRESC4 |
434 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4 |
435 CSI2_COMPLEXIO_IRQ_ERRSOTHS4 |
436 CSI2_COMPLEXIO_IRQ_STATEULPM3 |
437 CSI2_COMPLEXIO_IRQ_ERRCONTROL3 |
438 CSI2_COMPLEXIO_IRQ_ERRESC3 |
439 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3 |
440 CSI2_COMPLEXIO_IRQ_ERRSOTHS3 |
441 CSI2_COMPLEXIO_IRQ_STATEULPM2 |
442 CSI2_COMPLEXIO_IRQ_ERRCONTROL2 |
443 CSI2_COMPLEXIO_IRQ_ERRESC2 |
444 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2 |
445 CSI2_COMPLEXIO_IRQ_ERRSOTHS2 |
446 CSI2_COMPLEXIO_IRQ_STATEULPM1 |
447 CSI2_COMPLEXIO_IRQ_ERRCONTROL1 |
448 CSI2_COMPLEXIO_IRQ_ERRESC1 |
449 CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1 |
450 CSI2_COMPLEXIO_IRQ_ERRSOTHS1;
451 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS, reg);
453 iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
456 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQENABLE,
461 * csi2_irq_status_set - Enables CSI2 Status IRQs.
462 * @enable: Enable/disable CSI2 Status interrupts
464 static void csi2_irq_status_set(struct iss_csi2_device *csi2, int enable)
468 reg = CSI2_IRQ_OCP_ERR |
469 CSI2_IRQ_SHORT_PACKET |
470 CSI2_IRQ_ECC_CORRECTION |
471 CSI2_IRQ_ECC_NO_CORRECTION |
472 CSI2_IRQ_COMPLEXIO_ERR |
475 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, reg);
477 iss_reg_set(csi2->iss, csi2->regs1, CSI2_IRQENABLE, reg);
479 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQENABLE, 0);
483 * omap4iss_csi2_reset - Resets the CSI2 module.
485 * Must be called with the phy lock held.
487 * Returns 0 if successful, or -EBUSY if power command didn't respond.
489 int omap4iss_csi2_reset(struct iss_csi2_device *csi2)
491 unsigned int timeout;
493 if (!csi2->available)
496 if (csi2->phy->phy_in_use)
499 iss_reg_set(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
500 CSI2_SYSCONFIG_SOFT_RESET);
502 timeout = iss_poll_condition_timeout(
503 iss_reg_read(csi2->iss, csi2->regs1, CSI2_SYSSTATUS) &
504 CSI2_SYSSTATUS_RESET_DONE, 500, 100, 200);
506 dev_err(csi2->iss->dev, "CSI2: Soft reset timeout!\n");
510 iss_reg_set(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_CFG,
511 CSI2_COMPLEXIO_CFG_RESET_CTRL);
513 timeout = iss_poll_condition_timeout(
514 iss_reg_read(csi2->iss, csi2->phy->phy_regs, REGISTER1) &
515 REGISTER1_RESET_DONE_CTRLCLK, 10000, 100, 500);
517 dev_err(csi2->iss->dev, "CSI2: CSI2_96M_FCLK reset timeout!\n");
521 iss_reg_update(csi2->iss, csi2->regs1, CSI2_SYSCONFIG,
522 CSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
523 CSI2_SYSCONFIG_AUTO_IDLE,
524 CSI2_SYSCONFIG_MSTANDBY_MODE_NO);
529 static int csi2_configure(struct iss_csi2_device *csi2)
531 const struct iss_v4l2_subdevs_group *pdata;
532 struct iss_csi2_timing_cfg *timing = &csi2->timing[0];
533 struct v4l2_subdev *sensor;
534 struct media_pad *pad;
537 * CSI2 fields that can be updated while the context has
538 * been enabled or the interface has been enabled are not
539 * updated dynamically currently. So we do not allow to
540 * reconfigure if either has been enabled
542 if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
545 pad = media_entity_remote_pad(&csi2->pads[CSI2_PAD_SINK]);
546 sensor = media_entity_to_v4l2_subdev(pad->entity);
547 pdata = sensor->host_priv;
549 csi2->frame_skip = 0;
550 v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
552 csi2->ctrl.vp_out_ctrl = pdata->bus.csi2.vpclk_div;
553 csi2->ctrl.frame_mode = ISS_CSI2_FRAME_IMMEDIATE;
554 csi2->ctrl.ecc_enable = pdata->bus.csi2.crc;
556 timing->force_rx_mode = 1;
557 timing->stop_state_16x = 1;
558 timing->stop_state_4x = 1;
559 timing->stop_state_counter = 0x1ff;
562 * The CSI2 receiver can't do any format conversion except DPCM
563 * decompression, so every set_format call configures both pads
564 * and enables DPCM decompression as a special case:
566 if (csi2->formats[CSI2_PAD_SINK].code !=
567 csi2->formats[CSI2_PAD_SOURCE].code)
568 csi2->dpcm_decompress = true;
570 csi2->dpcm_decompress = false;
572 csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
574 if (csi2->video_out.bpl_padding == 0)
575 csi2->contexts[0].data_offset = 0;
577 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
580 * Enable end of frame and end of line signals generation for
581 * context 0. These signals are generated from CSI2 receiver to
582 * qualify the last pixel of a frame and the last pixel of a line.
583 * Without enabling the signals CSI2 receiver writes data to memory
584 * beyond buffer size and/or data line offset is not handled correctly.
586 csi2->contexts[0].eof_enabled = 1;
587 csi2->contexts[0].eol_enabled = 1;
589 csi2_irq_complexio1_set(csi2, 1);
590 csi2_irq_ctx_set(csi2, 1);
591 csi2_irq_status_set(csi2, 1);
593 /* Set configuration (timings, format and links) */
594 csi2_timing_config(csi2, timing);
595 csi2_recv_config(csi2, &csi2->ctrl);
596 csi2_ctx_config(csi2, &csi2->contexts[0]);
602 * csi2_print_status - Prints CSI2 debug information.
604 #define CSI2_PRINT_REGISTER(iss, regs, name)\
605 dev_dbg(iss->dev, "###CSI2 " #name "=0x%08x\n", \
606 iss_reg_read(iss, regs, CSI2_##name))
608 static void csi2_print_status(struct iss_csi2_device *csi2)
610 struct iss_device *iss = csi2->iss;
612 if (!csi2->available)
615 dev_dbg(iss->dev, "-------------CSI2 Register dump-------------\n");
617 CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSCONFIG);
618 CSI2_PRINT_REGISTER(iss, csi2->regs1, SYSSTATUS);
619 CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQENABLE);
620 CSI2_PRINT_REGISTER(iss, csi2->regs1, IRQSTATUS);
621 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTRL);
622 CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_H);
623 CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_CFG);
624 CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQSTATUS);
625 CSI2_PRINT_REGISTER(iss, csi2->regs1, SHORT_PACKET);
626 CSI2_PRINT_REGISTER(iss, csi2->regs1, COMPLEXIO_IRQENABLE);
627 CSI2_PRINT_REGISTER(iss, csi2->regs1, DBG_P);
628 CSI2_PRINT_REGISTER(iss, csi2->regs1, TIMING);
629 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL1(0));
630 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL2(0));
631 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_DAT_OFST(0));
632 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PING_ADDR(0));
633 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_PONG_ADDR(0));
634 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQENABLE(0));
635 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_IRQSTATUS(0));
636 CSI2_PRINT_REGISTER(iss, csi2->regs1, CTX_CTRL3(0));
638 dev_dbg(iss->dev, "--------------------------------------------\n");
641 /* -----------------------------------------------------------------------------
646 * csi2_isr_buffer - Does buffer handling at end-of-frame
647 * when writing to memory.
649 static void csi2_isr_buffer(struct iss_csi2_device *csi2)
651 struct iss_buffer *buffer;
653 csi2_ctx_enable(csi2, 0, 0);
655 buffer = omap4iss_video_buffer_next(&csi2->video_out);
658 * Let video queue operation restart engine if there is an underrun
664 csi2_set_outaddr(csi2, buffer->iss_addr);
665 csi2_ctx_enable(csi2, 0, 1);
668 static void csi2_isr_ctx(struct iss_csi2_device *csi2,
669 struct iss_csi2_ctx_cfg *ctx)
671 unsigned int n = ctx->ctxnum;
674 status = iss_reg_read(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n));
675 iss_reg_write(csi2->iss, csi2->regs1, CSI2_CTX_IRQSTATUS(n), status);
677 if (omap4iss_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
680 /* Propagate frame number */
681 if (status & CSI2_CTX_IRQ_FS) {
682 struct iss_pipeline *pipe =
683 to_iss_pipeline(&csi2->subdev.entity);
687 frame = iss_reg_read(csi2->iss, csi2->regs1,
688 CSI2_CTX_CTRL2(ctx->ctxnum))
689 >> CSI2_CTX_CTRL2_FRAME_SHIFT;
692 /* A zero value means that the counter isn't implemented
693 * by the source. Increment the frame number in software
696 atomic_inc(&pipe->frame_number);
698 /* Extend the 16 bit frame number to 32 bits by
699 * computing the delta between two consecutive CSI2
700 * frame numbers and adding it to the software frame
701 * number. The hardware counter starts at 1 and wraps
702 * from 0xffff to 1 without going through 0, so subtract
703 * 1 when the counter wraps.
705 delta = frame - ctx->frame;
706 if (frame < ctx->frame)
710 atomic_add(delta, &pipe->frame_number);
714 if (!(status & CSI2_CTX_IRQ_FE))
717 /* Skip interrupts until we reach the frame skip count. The CSI2 will be
718 * automatically disabled, as the frame skip count has been programmed
719 * in the CSI2_CTx_CTRL1::COUNT field, so reenable it.
721 * It would have been nice to rely on the FRAME_NUMBER interrupt instead
722 * but it turned out that the interrupt is only generated when the CSI2
723 * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
724 * correctly and reaches 0 when data is forwarded to the video port only
725 * but no interrupt arrives). Maybe a CSI2 hardware bug.
727 if (csi2->frame_skip) {
729 if (csi2->frame_skip == 0) {
730 ctx->format_id = csi2_ctx_map_format(csi2);
731 csi2_ctx_config(csi2, ctx);
732 csi2_ctx_enable(csi2, n, 1);
737 if (csi2->output & CSI2_OUTPUT_MEMORY)
738 csi2_isr_buffer(csi2);
742 * omap4iss_csi2_isr - CSI2 interrupt handling.
744 void omap4iss_csi2_isr(struct iss_csi2_device *csi2)
746 struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
747 u32 csi2_irqstatus, cpxio1_irqstatus;
748 struct iss_device *iss = csi2->iss;
750 if (!csi2->available)
753 csi2_irqstatus = iss_reg_read(csi2->iss, csi2->regs1, CSI2_IRQSTATUS);
754 iss_reg_write(csi2->iss, csi2->regs1, CSI2_IRQSTATUS, csi2_irqstatus);
757 if (csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR) {
758 cpxio1_irqstatus = iss_reg_read(csi2->iss, csi2->regs1,
759 CSI2_COMPLEXIO_IRQSTATUS);
760 iss_reg_write(csi2->iss, csi2->regs1, CSI2_COMPLEXIO_IRQSTATUS,
762 dev_dbg(iss->dev, "CSI2: ComplexIO Error IRQ %x\n",
767 if (csi2_irqstatus & (CSI2_IRQ_OCP_ERR |
768 CSI2_IRQ_SHORT_PACKET |
769 CSI2_IRQ_ECC_NO_CORRECTION |
770 CSI2_IRQ_COMPLEXIO_ERR |
771 CSI2_IRQ_FIFO_OVF)) {
773 "CSI2 Err: OCP:%d SHORT:%d ECC:%d CPXIO:%d OVF:%d\n",
774 csi2_irqstatus & CSI2_IRQ_OCP_ERR ? 1 : 0,
775 csi2_irqstatus & CSI2_IRQ_SHORT_PACKET ? 1 : 0,
776 csi2_irqstatus & CSI2_IRQ_ECC_NO_CORRECTION ? 1 : 0,
777 csi2_irqstatus & CSI2_IRQ_COMPLEXIO_ERR ? 1 : 0,
778 csi2_irqstatus & CSI2_IRQ_FIFO_OVF ? 1 : 0);
782 /* Successful cases */
783 if (csi2_irqstatus & CSI2_IRQ_CONTEXT0)
784 csi2_isr_ctx(csi2, &csi2->contexts[0]);
786 if (csi2_irqstatus & CSI2_IRQ_ECC_CORRECTION)
787 dev_dbg(iss->dev, "CSI2: ECC correction done\n");
790 /* -----------------------------------------------------------------------------
791 * ISS video operations
795 * csi2_queue - Queues the first buffer when using memory output
796 * @video: The video node
797 * @buffer: buffer to queue
799 static int csi2_queue(struct iss_video *video, struct iss_buffer *buffer)
801 struct iss_csi2_device *csi2 = container_of(video,
802 struct iss_csi2_device, video_out);
804 csi2_set_outaddr(csi2, buffer->iss_addr);
807 * If streaming was enabled before there was a buffer queued
808 * or underrun happened in the ISR, the hardware was not enabled
809 * and DMA queue flag ISS_VIDEO_DMAQUEUE_UNDERRUN is still set.
812 if (csi2->video_out.dmaqueue_flags & ISS_VIDEO_DMAQUEUE_UNDERRUN) {
813 /* Enable / disable context 0 and IRQs */
814 csi2_if_enable(csi2, 1);
815 csi2_ctx_enable(csi2, 0, 1);
816 iss_video_dmaqueue_flags_clr(&csi2->video_out);
822 static const struct iss_video_operations csi2_issvideo_ops = {
826 /* -----------------------------------------------------------------------------
827 * V4L2 subdev operations
830 static struct v4l2_mbus_framefmt *
831 __csi2_get_format(struct iss_csi2_device *csi2,
832 struct v4l2_subdev_pad_config *cfg,
834 enum v4l2_subdev_format_whence which)
836 if (which == V4L2_SUBDEV_FORMAT_TRY)
837 return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad);
839 return &csi2->formats[pad];
843 csi2_try_format(struct iss_csi2_device *csi2,
844 struct v4l2_subdev_pad_config *cfg,
846 struct v4l2_mbus_framefmt *fmt,
847 enum v4l2_subdev_format_whence which)
850 struct v4l2_mbus_framefmt *format;
851 const struct iss_format_info *info;
856 /* Clamp the width and height to valid range (1-8191). */
857 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
858 if (fmt->code == csi2_input_fmts[i])
862 /* If not found, use SGRBG10 as default */
863 if (i >= ARRAY_SIZE(csi2_input_fmts))
864 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
866 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
867 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
870 case CSI2_PAD_SOURCE:
871 /* Source format same as sink format, except for DPCM
874 pixelcode = fmt->code;
875 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK, which);
876 memcpy(fmt, format, sizeof(*fmt));
879 * Only Allow DPCM decompression, and check that the
880 * pattern is preserved
882 info = omap4iss_video_format_info(fmt->code);
883 if (info->uncompressed == pixelcode)
884 fmt->code = pixelcode;
888 /* RGB, non-interlaced */
889 fmt->colorspace = V4L2_COLORSPACE_SRGB;
890 fmt->field = V4L2_FIELD_NONE;
894 * csi2_enum_mbus_code - Handle pixel format enumeration
895 * @sd : pointer to v4l2 subdev structure
896 * @cfg : V4L2 subdev pad config
897 * @code : pointer to v4l2_subdev_mbus_code_enum structure
898 * return -EINVAL or zero on success
900 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
901 struct v4l2_subdev_pad_config *cfg,
902 struct v4l2_subdev_mbus_code_enum *code)
904 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
905 struct v4l2_mbus_framefmt *format;
906 const struct iss_format_info *info;
908 if (code->pad == CSI2_PAD_SINK) {
909 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
912 code->code = csi2_input_fmts[code->index];
914 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SINK,
916 switch (code->index) {
918 /* Passthrough sink pad code */
919 code->code = format->code;
922 /* Uncompressed code */
923 info = omap4iss_video_format_info(format->code);
924 if (info->uncompressed == format->code)
927 code->code = info->uncompressed;
937 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
938 struct v4l2_subdev_pad_config *cfg,
939 struct v4l2_subdev_frame_size_enum *fse)
941 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
942 struct v4l2_mbus_framefmt format;
947 format.code = fse->code;
950 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
951 fse->min_width = format.width;
952 fse->min_height = format.height;
954 if (format.code != fse->code)
957 format.code = fse->code;
960 csi2_try_format(csi2, cfg, fse->pad, &format, fse->which);
961 fse->max_width = format.width;
962 fse->max_height = format.height;
968 * csi2_get_format - Handle get format by pads subdev method
969 * @sd : pointer to v4l2 subdev structure
970 * @cfg: V4L2 subdev pad config
971 * @fmt: pointer to v4l2 subdev format structure
972 * return -EINVAL or zero on success
974 static int csi2_get_format(struct v4l2_subdev *sd,
975 struct v4l2_subdev_pad_config *cfg,
976 struct v4l2_subdev_format *fmt)
978 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
979 struct v4l2_mbus_framefmt *format;
981 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
985 fmt->format = *format;
990 * csi2_set_format - Handle set format by pads subdev method
991 * @sd : pointer to v4l2 subdev structure
992 * @cfg: V4L2 subdev pad config
993 * @fmt: pointer to v4l2 subdev format structure
994 * return -EINVAL or zero on success
996 static int csi2_set_format(struct v4l2_subdev *sd,
997 struct v4l2_subdev_pad_config *cfg,
998 struct v4l2_subdev_format *fmt)
1000 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1001 struct v4l2_mbus_framefmt *format;
1003 format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
1007 csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);
1008 *format = fmt->format;
1010 /* Propagate the format from sink to source */
1011 if (fmt->pad == CSI2_PAD_SINK) {
1012 format = __csi2_get_format(csi2, cfg, CSI2_PAD_SOURCE,
1014 *format = fmt->format;
1015 csi2_try_format(csi2, cfg, CSI2_PAD_SOURCE, format, fmt->which);
1021 static int csi2_link_validate(struct v4l2_subdev *sd, struct media_link *link,
1022 struct v4l2_subdev_format *source_fmt,
1023 struct v4l2_subdev_format *sink_fmt)
1025 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1026 struct iss_pipeline *pipe = to_iss_pipeline(&csi2->subdev.entity);
1029 pipe->external = media_entity_to_v4l2_subdev(link->source->entity);
1030 rval = omap4iss_get_external_info(pipe, link);
1034 return v4l2_subdev_link_validate_default(sd, link, source_fmt,
1039 * csi2_init_formats - Initialize formats on all pads
1040 * @sd: ISS CSI2 V4L2 subdevice
1041 * @fh: V4L2 subdev file handle
1043 * Initialize all pad formats with default values. If fh is not NULL, try
1044 * formats are initialized on the file handle. Otherwise active formats are
1045 * initialized on the device.
1047 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1049 struct v4l2_subdev_format format;
1051 memset(&format, 0, sizeof(format));
1052 format.pad = CSI2_PAD_SINK;
1053 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1054 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1055 format.format.width = 4096;
1056 format.format.height = 4096;
1057 csi2_set_format(sd, fh ? fh->pad : NULL, &format);
1063 * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1064 * @sd: ISS CSI2 V4L2 subdevice
1065 * @enable: ISS pipeline stream state
1067 * Return 0 on success or a negative error code otherwise.
1069 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1071 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1072 struct iss_device *iss = csi2->iss;
1073 struct iss_video *video_out = &csi2->video_out;
1076 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED) {
1077 if (enable == ISS_PIPELINE_STREAM_STOPPED)
1080 omap4iss_subclk_enable(iss, csi2->subclk);
1084 case ISS_PIPELINE_STREAM_CONTINUOUS: {
1085 ret = omap4iss_csiphy_config(iss, sd);
1089 if (omap4iss_csiphy_acquire(csi2->phy) < 0)
1091 csi2_configure(csi2);
1092 csi2_print_status(csi2);
1095 * When outputting to memory with no buffer available, let the
1096 * buffer queue handler start the hardware. A DMA queue flag
1097 * ISS_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1098 * a buffer available.
1100 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1101 !(video_out->dmaqueue_flags & ISS_VIDEO_DMAQUEUE_QUEUED))
1103 /* Enable context 0 and IRQs */
1104 atomic_set(&csi2->stopping, 0);
1105 csi2_ctx_enable(csi2, 0, 1);
1106 csi2_if_enable(csi2, 1);
1107 iss_video_dmaqueue_flags_clr(video_out);
1110 case ISS_PIPELINE_STREAM_STOPPED:
1111 if (csi2->state == ISS_PIPELINE_STREAM_STOPPED)
1113 if (omap4iss_module_sync_idle(&sd->entity, &csi2->wait,
1116 csi2_ctx_enable(csi2, 0, 0);
1117 csi2_if_enable(csi2, 0);
1118 csi2_irq_ctx_set(csi2, 0);
1119 omap4iss_csiphy_release(csi2->phy);
1120 omap4iss_subclk_disable(iss, csi2->subclk);
1121 iss_video_dmaqueue_flags_clr(video_out);
1125 csi2->state = enable;
1129 /* subdev video operations */
1130 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1131 .s_stream = csi2_set_stream,
1134 /* subdev pad operations */
1135 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1136 .enum_mbus_code = csi2_enum_mbus_code,
1137 .enum_frame_size = csi2_enum_frame_size,
1138 .get_fmt = csi2_get_format,
1139 .set_fmt = csi2_set_format,
1140 .link_validate = csi2_link_validate,
1143 /* subdev operations */
1144 static const struct v4l2_subdev_ops csi2_ops = {
1145 .video = &csi2_video_ops,
1146 .pad = &csi2_pad_ops,
1149 /* subdev internal operations */
1150 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1151 .open = csi2_init_formats,
1154 /* -----------------------------------------------------------------------------
1155 * Media entity operations
1159 * csi2_link_setup - Setup CSI2 connections.
1160 * @entity : Pointer to media entity structure
1161 * @local : Pointer to local pad array
1162 * @remote : Pointer to remote pad array
1163 * @flags : Link flags
1164 * return -EINVAL or zero on success
1166 static int csi2_link_setup(struct media_entity *entity,
1167 const struct media_pad *local,
1168 const struct media_pad *remote, u32 flags)
1170 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1171 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1172 struct iss_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1173 unsigned int index = local->index;
1175 /* FIXME: this is actually a hack! */
1176 if (is_media_entity_v4l2_subdev(remote->entity))
1180 * The ISS core doesn't support pipelines with multiple video outputs.
1181 * Revisit this when it will be implemented, and return -EBUSY for now.
1185 case CSI2_PAD_SOURCE:
1186 if (flags & MEDIA_LNK_FL_ENABLED) {
1187 if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1189 csi2->output |= CSI2_OUTPUT_MEMORY;
1191 csi2->output &= ~CSI2_OUTPUT_MEMORY;
1195 case CSI2_PAD_SOURCE | 2 << 16:
1196 if (flags & MEDIA_LNK_FL_ENABLED) {
1197 if (csi2->output & ~CSI2_OUTPUT_IPIPEIF)
1199 csi2->output |= CSI2_OUTPUT_IPIPEIF;
1201 csi2->output &= ~CSI2_OUTPUT_IPIPEIF;
1206 /* Link from camera to CSI2 is fixed... */
1210 ctrl->vp_only_enable = csi2->output & CSI2_OUTPUT_MEMORY ? false : true;
1211 ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_IPIPEIF);
1216 /* media operations */
1217 static const struct media_entity_operations csi2_media_ops = {
1218 .link_setup = csi2_link_setup,
1219 .link_validate = v4l2_subdev_link_validate,
1222 void omap4iss_csi2_unregister_entities(struct iss_csi2_device *csi2)
1224 v4l2_device_unregister_subdev(&csi2->subdev);
1225 omap4iss_video_unregister(&csi2->video_out);
1228 int omap4iss_csi2_register_entities(struct iss_csi2_device *csi2,
1229 struct v4l2_device *vdev)
1233 /* Register the subdev and video nodes. */
1234 ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1238 ret = omap4iss_video_register(&csi2->video_out, vdev);
1245 omap4iss_csi2_unregister_entities(csi2);
1249 /* -----------------------------------------------------------------------------
1250 * ISS CSI2 initialisation and cleanup
1254 * csi2_init_entities - Initialize subdev and media entity.
1255 * @csi2: Pointer to csi2 structure.
1256 * return -ENOMEM or zero on success
1258 static int csi2_init_entities(struct iss_csi2_device *csi2, const char *subname)
1260 struct v4l2_subdev *sd = &csi2->subdev;
1261 struct media_pad *pads = csi2->pads;
1262 struct media_entity *me = &sd->entity;
1264 char name[V4L2_SUBDEV_NAME_SIZE];
1266 v4l2_subdev_init(sd, &csi2_ops);
1267 sd->internal_ops = &csi2_internal_ops;
1268 snprintf(name, sizeof(name), "CSI2%s", subname);
1269 snprintf(sd->name, sizeof(sd->name), "OMAP4 ISS %s", name);
1271 sd->grp_id = 1 << 16; /* group ID for iss subdevs */
1272 v4l2_set_subdevdata(sd, csi2);
1273 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1275 pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1276 pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1278 me->ops = &csi2_media_ops;
1279 ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
1283 csi2_init_formats(sd, NULL);
1285 /* Video device node */
1286 csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1287 csi2->video_out.ops = &csi2_issvideo_ops;
1288 csi2->video_out.bpl_alignment = 32;
1289 csi2->video_out.bpl_zero_padding = 1;
1290 csi2->video_out.bpl_max = 0x1ffe0;
1291 csi2->video_out.iss = csi2->iss;
1292 csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1294 ret = omap4iss_video_init(&csi2->video_out, name);
1301 media_entity_cleanup(&csi2->subdev.entity);
1306 * omap4iss_csi2_init - Routine for module driver init
1308 int omap4iss_csi2_init(struct iss_device *iss)
1310 struct iss_csi2_device *csi2a = &iss->csi2a;
1311 struct iss_csi2_device *csi2b = &iss->csi2b;
1315 csi2a->available = 1;
1316 csi2a->regs1 = OMAP4_ISS_MEM_CSI2_A_REGS1;
1317 csi2a->phy = &iss->csiphy1;
1318 csi2a->subclk = OMAP4_ISS_SUBCLK_CSI2_A;
1319 csi2a->state = ISS_PIPELINE_STREAM_STOPPED;
1320 init_waitqueue_head(&csi2a->wait);
1322 ret = csi2_init_entities(csi2a, "a");
1327 csi2b->available = 1;
1328 csi2b->regs1 = OMAP4_ISS_MEM_CSI2_B_REGS1;
1329 csi2b->phy = &iss->csiphy2;
1330 csi2b->subclk = OMAP4_ISS_SUBCLK_CSI2_B;
1331 csi2b->state = ISS_PIPELINE_STREAM_STOPPED;
1332 init_waitqueue_head(&csi2b->wait);
1334 ret = csi2_init_entities(csi2b, "b");
1342 * omap4iss_csi2_create_links() - CSI2 pads links creation
1343 * @iss: Pointer to ISS device
1345 * return negative error code or zero on success
1347 int omap4iss_csi2_create_links(struct iss_device *iss)
1349 struct iss_csi2_device *csi2a = &iss->csi2a;
1350 struct iss_csi2_device *csi2b = &iss->csi2b;
1353 /* Connect the CSI2a subdev to the video node. */
1354 ret = media_create_pad_link(&csi2a->subdev.entity, CSI2_PAD_SOURCE,
1355 &csi2a->video_out.video.entity, 0, 0);
1359 /* Connect the CSI2b subdev to the video node. */
1360 ret = media_create_pad_link(&csi2b->subdev.entity, CSI2_PAD_SOURCE,
1361 &csi2b->video_out.video.entity, 0, 0);
1369 * omap4iss_csi2_cleanup - Routine for module driver cleanup
1371 void omap4iss_csi2_cleanup(struct iss_device *iss)
1373 struct iss_csi2_device *csi2a = &iss->csi2a;
1374 struct iss_csi2_device *csi2b = &iss->csi2b;
1376 omap4iss_video_cleanup(&csi2a->video_out);
1377 media_entity_cleanup(&csi2a->subdev.entity);
1379 omap4iss_video_cleanup(&csi2b->video_out);
1380 media_entity_cleanup(&csi2b->subdev.entity);