2 * TI OMAP4 ISS V4L2 Driver - CSI PHY module
4 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/regmap.h>
18 #include "../../../../arch/arm/mach-omap2/control.h"
22 #include "iss_csiphy.h"
25 * csiphy_lanes_config - Configuration of CSIPHY lanes.
27 * Updates HW configuration.
28 * Called with phy->mutex taken.
30 static void csiphy_lanes_config(struct iss_csiphy *phy)
35 reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG);
37 for (i = 0; i < phy->max_data_lanes; i++) {
38 reg &= ~(CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) |
39 CSI2_COMPLEXIO_CFG_DATA_POSITION_MASK(i + 1));
40 reg |= (phy->lanes.data[i].pol ?
41 CSI2_COMPLEXIO_CFG_DATA_POL(i + 1) : 0);
42 reg |= (phy->lanes.data[i].pos <<
43 CSI2_COMPLEXIO_CFG_DATA_POSITION_SHIFT(i + 1));
46 reg &= ~(CSI2_COMPLEXIO_CFG_CLOCK_POL |
47 CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK);
48 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0;
49 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT;
51 iss_reg_write(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG, reg);
56 * @power: Power state to be set.
58 * Returns 0 if successful, or -EBUSY if the retry count is exceeded.
60 static int csiphy_set_power(struct iss_csiphy *phy, u32 power)
65 iss_reg_update(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG,
66 CSI2_COMPLEXIO_CFG_PWD_CMD_MASK,
67 power | CSI2_COMPLEXIO_CFG_PWR_AUTO);
72 reg = iss_reg_read(phy->iss, phy->cfg_regs, CSI2_COMPLEXIO_CFG)
73 & CSI2_COMPLEXIO_CFG_PWD_STATUS_MASK;
75 if (reg != power >> 2)
78 } while ((reg != power >> 2) && (retry_count < 250));
80 if (retry_count == 250) {
81 dev_err(phy->iss->dev, "CSI2 CIO set power failed!\n");
89 * csiphy_dphy_config - Configure CSI2 D-PHY parameters.
91 * Called with phy->mutex taken.
93 static void csiphy_dphy_config(struct iss_csiphy *phy)
97 /* Set up REGISTER0 */
98 reg = phy->dphy.ths_term << REGISTER0_THS_TERM_SHIFT;
99 reg |= phy->dphy.ths_settle << REGISTER0_THS_SETTLE_SHIFT;
101 iss_reg_write(phy->iss, phy->phy_regs, REGISTER0, reg);
103 /* Set up REGISTER1 */
104 reg = phy->dphy.tclk_term << REGISTER1_TCLK_TERM_SHIFT;
105 reg |= phy->dphy.tclk_miss << REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT;
106 reg |= phy->dphy.tclk_settle << REGISTER1_TCLK_SETTLE_SHIFT;
107 reg |= 0xb8 << REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT;
109 iss_reg_write(phy->iss, phy->phy_regs, REGISTER1, reg);
113 * TCLK values are OK at their reset values
117 #define TCLK_SETTLE 14
119 int omap4iss_csiphy_config(struct iss_device *iss,
120 struct v4l2_subdev *csi2_subdev)
122 struct iss_csi2_device *csi2 = v4l2_get_subdevdata(csi2_subdev);
123 struct iss_pipeline *pipe = to_iss_pipeline(&csi2_subdev->entity);
124 struct iss_v4l2_subdevs_group *subdevs = pipe->external->host_priv;
125 struct iss_csiphy_dphy_cfg csi2phy;
127 struct iss_csiphy_lanes_cfg *lanes;
128 unsigned int used_lanes = 0;
132 lanes = &subdevs->bus.csi2.lanecfg;
135 * SCM.CONTROL_CAMERA_RX
136 * - bit [31] : CSIPHY2 lane 2 enable (4460+ only)
137 * - bit [30:29] : CSIPHY2 per-lane enable (1 to 0)
138 * - bit [28:24] : CSIPHY1 per-lane enable (4 to 0)
139 * - bit [21] : CSIPHY2 CTRLCLK enable
140 * - bit [20:19] : CSIPHY2 config: 00 d-phy, 01/10 ccp2
141 * - bit [18] : CSIPHY1 CTRLCLK enable
142 * - bit [17:16] : CSIPHY1 config: 00 d-phy, 01/10 ccp2
145 * TODO: When implementing DT support specify the CONTROL_CAMERA_RX
146 * register offset in the syscon property instead of hardcoding it.
148 regmap_read(iss->syscon, 0x68, &cam_rx_ctrl);
150 if (subdevs->interface == ISS_INTERFACE_CSI2A_PHY1) {
151 cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI21_LANEENABLE_MASK |
152 OMAP4_CAMERARX_CSI21_CAMMODE_MASK);
153 /* NOTE: Leave CSIPHY1 config to 0x0: D-PHY mode */
154 /* Enable all lanes for now */
156 0x1f << OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT;
158 cam_rx_ctrl |= OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK;
161 if (subdevs->interface == ISS_INTERFACE_CSI2B_PHY2) {
162 cam_rx_ctrl &= ~(OMAP4_CAMERARX_CSI22_LANEENABLE_MASK |
163 OMAP4_CAMERARX_CSI22_CAMMODE_MASK);
164 /* NOTE: Leave CSIPHY2 config to 0x0: D-PHY mode */
165 /* Enable all lanes for now */
167 0x3 << OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT;
169 cam_rx_ctrl |= OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK;
172 regmap_write(iss->syscon, 0x68, cam_rx_ctrl);
174 /* Reset used lane count */
175 csi2->phy->used_data_lanes = 0;
177 /* Clock and data lanes verification */
178 for (i = 0; i < csi2->phy->max_data_lanes; i++) {
179 if (lanes->data[i].pos == 0)
182 if (lanes->data[i].pol > 1 ||
183 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1))
186 if (used_lanes & (1 << lanes->data[i].pos))
189 used_lanes |= 1 << lanes->data[i].pos;
190 csi2->phy->used_data_lanes++;
193 if (lanes->clk.pol > 1 ||
194 lanes->clk.pos > (csi2->phy->max_data_lanes + 1))
197 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
200 csi2_ddrclk_khz = pipe->external_rate / 1000
201 / (2 * csi2->phy->used_data_lanes)
202 * pipe->external_bpp;
205 * THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1.
206 * THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3.
208 csi2phy.ths_term = DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1;
209 csi2phy.ths_settle = DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3;
210 csi2phy.tclk_term = TCLK_TERM;
211 csi2phy.tclk_miss = TCLK_MISS;
212 csi2phy.tclk_settle = TCLK_SETTLE;
214 mutex_lock(&csi2->phy->mutex);
215 csi2->phy->dphy = csi2phy;
216 csi2->phy->lanes = *lanes;
217 mutex_unlock(&csi2->phy->mutex);
222 int omap4iss_csiphy_acquire(struct iss_csiphy *phy)
226 mutex_lock(&phy->mutex);
228 rval = omap4iss_csi2_reset(phy->csi2);
232 csiphy_dphy_config(phy);
233 csiphy_lanes_config(phy);
235 rval = csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_ON);
242 mutex_unlock(&phy->mutex);
246 void omap4iss_csiphy_release(struct iss_csiphy *phy)
248 mutex_lock(&phy->mutex);
249 if (phy->phy_in_use) {
250 csiphy_set_power(phy, CSI2_COMPLEXIO_CFG_PWD_CMD_OFF);
253 mutex_unlock(&phy->mutex);
257 * omap4iss_csiphy_init - Initialize the CSI PHY frontends
259 int omap4iss_csiphy_init(struct iss_device *iss)
261 struct iss_csiphy *phy1 = &iss->csiphy1;
262 struct iss_csiphy *phy2 = &iss->csiphy2;
265 phy1->csi2 = &iss->csi2a;
266 phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES;
267 phy1->used_data_lanes = 0;
268 phy1->cfg_regs = OMAP4_ISS_MEM_CSI2_A_REGS1;
269 phy1->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE1;
270 mutex_init(&phy1->mutex);
273 phy2->csi2 = &iss->csi2b;
274 phy2->max_data_lanes = ISS_CSIPHY2_NUM_DATA_LANES;
275 phy2->used_data_lanes = 0;
276 phy2->cfg_regs = OMAP4_ISS_MEM_CSI2_B_REGS1;
277 phy2->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE2;
278 mutex_init(&phy2->mutex);