2 * dim2_reg.h - Definitions for registers of DIM2
3 * (MediaLB, Device Interface Macro IP, OS62420)
5 * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * This file is licensed under GPLv2.
15 #ifndef DIM2_OS62420_H
16 #define DIM2_OS62420_H
18 #include <linux/types.h>
27 /* 0x01 */ u32 rsvd0[1];
28 /* 0x02 */ u32 MLBPC0;
30 /* 0x04 */ u32 rsvd1[1];
32 /* 0x06 */ u32 rsvd2[2];
35 /* 0x0A */ u32 rsvd3[1];
37 /* 0x0C */ u32 rsvd4[1];
38 /* 0x0D */ u32 MLBPC2;
39 /* 0x0E */ u32 MLBPC1;
41 /* 0x10 */ u32 rsvd5[0x10];
43 /* 0x21 */ u32 rsvd6[1];
50 /* 0x28 */ u32 rsvd7[8];
61 /* 0x3A */ u32 rsvd8[0xB6];
63 /* 0xF1 */ u32 rsvd9[3];
71 #define DIM2_MASK(n) (~((~(u32)0)<<(n)))
78 MLBC0_MLBCLK_SHIFT = 2,
79 MLBC0_MLBCLK_VAL_256FS = 0,
80 MLBC0_MLBCLK_VAL_512FS = 1,
81 MLBC0_MLBCLK_VAL_1024FS = 2,
82 MLBC0_MLBCLK_VAL_2048FS = 3,
84 MLBC0_FCNT_SHIFT = 15,
86 MLBC0_FCNT_VAL_1FPSB = 0,
87 MLBC0_FCNT_VAL_2FPSB = 1,
88 MLBC0_FCNT_VAL_4FPSB = 2,
89 MLBC0_FCNT_VAL_8FPSB = 3,
90 MLBC0_FCNT_VAL_16FPSB = 4,
91 MLBC0_FCNT_VAL_32FPSB = 5,
92 MLBC0_FCNT_VAL_64FPSB = 6,
96 MIEN_CTX_BREAK_BIT = 29,
98 MIEN_CTX_DONE_BIT = 27,
100 MIEN_CRX_BREAK_BIT = 26,
101 MIEN_CRX_PE_BIT = 25,
102 MIEN_CRX_DONE_BIT = 24,
104 MIEN_ATX_BREAK_BIT = 22,
105 MIEN_ATX_PE_BIT = 21,
106 MIEN_ATX_DONE_BIT = 20,
108 MIEN_ARX_BREAK_BIT = 19,
109 MIEN_ARX_PE_BIT = 18,
110 MIEN_ARX_DONE_BIT = 17,
112 MIEN_SYNC_PE_BIT = 16,
114 MIEN_ISOC_BUFO_BIT = 1,
115 MIEN_ISOC_PE_BIT = 0,
118 MLBC1_NDA_MASK = 0xFF,
120 MLBC1_CLKMERR_BIT = 7,
121 MLBC1_LOCKERR_BIT = 6,
123 ACTL_DMA_MODE_BIT = 2,
124 ACTL_DMA_MODE_VAL_DMA_MODE_0 = 0,
125 ACTL_DMA_MODE_VAL_DMA_MODE_1 = 1,
132 CDT1_BS_ISOC_SHIFT = 0,
133 CDT1_BS_ISOC_MASK = DIM2_MASK(9),
136 CDT3_BD_MASK = DIM2_MASK(12),
137 CDT3_BD_ISOC_MASK = DIM2_MASK(13),
150 ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11),
151 ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13),
163 CAT_CT_VAL_CONTROL = 1,
164 CAT_CT_VAL_ASYNC = 2,
168 CAT_CL_MASK = DIM2_MASK(6)
176 #endif /* DIM2_OS62420_H */