2 *************************************************************************
4 * 5F., No.36, Taiyuan St., Jhubei City,
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 *************************************************************************
31 Create and register network interface for PCI based chipsets in Linux platform.
35 -------- ---------- ----------------------------------------------
38 #include "rt_config.h"
39 #include <linux/pci.h>
40 #include <linux/slab.h>
42 /* Following information will be show when you run 'modinfo' */
43 /* *** If you have a solution for the bug in current version of driver, please mail to me. */
44 /* Otherwise post to forum in ralinktech's web site(www.ralinktech.com) and let all users help you. *** */
45 MODULE_AUTHOR("Jett Chen <jett_chen@ralinktech.com>");
46 MODULE_DESCRIPTION("RT2860/RT3090 Wireless Lan Linux Driver");
47 MODULE_LICENSE("GPL");
48 MODULE_ALIAS("rt3090sta");
51 /* Function declarations */
53 extern int rt28xx_close(IN struct net_device *net_dev);
54 extern int rt28xx_open(struct net_device *net_dev);
56 static void __devexit rt2860_remove_one(struct pci_dev *pci_dev);
57 static int __devinit rt2860_probe(struct pci_dev *pci_dev,
58 const struct pci_device_id *ent);
59 static void __exit rt2860_cleanup_module(void);
60 static int __init rt2860_init_module(void);
62 static void RTMPInitPCIeDevice(IN struct pci_dev *pci_dev,
63 struct rt_rtmp_adapter *pAd);
66 static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state);
67 static int rt2860_resume(struct pci_dev *pci_dev);
68 #endif /* CONFIG_PM // */
71 /* Ralink PCI device table, include all supported chipsets */
73 static struct pci_device_id rt2860_pci_tbl[] __devinitdata = {
75 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)}, /*RT28602.4G */
76 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCIe_DEVICE_ID)},
77 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2760_PCI_DEVICE_ID)},
78 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2790_PCIe_DEVICE_ID)},
79 {PCI_DEVICE(VEN_AWT_PCI_VENDOR_ID, VEN_AWT_PCIe_DEVICE_ID)},
80 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7708)},
81 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7728)},
82 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7758)},
83 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7727)},
84 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7738)},
85 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7748)},
86 {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7768)},
89 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3090_PCIe_DEVICE_ID)},
90 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3091_PCIe_DEVICE_ID)},
91 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3092_PCIe_DEVICE_ID)},
92 #endif /* RT3090 // */
94 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3390_PCIe_DEVICE_ID)},
95 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3391_PCIe_DEVICE_ID)},
96 {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3392_PCIe_DEVICE_ID)},
97 #endif /* RT3390 // */
98 {0,} /* terminate list */
101 MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
102 #ifdef MODULE_VERSION
103 MODULE_VERSION(STA_DRIVER_VERSION);
107 /* Our PCI driver structure */
109 static struct pci_driver rt2860_driver = {
111 id_table : rt2860_pci_tbl,
112 probe : rt2860_probe,
113 remove : __devexit_p(rt2860_remove_one),
115 suspend : rt2860_suspend,
116 resume : rt2860_resume,
120 /***************************************************************************
122 * PCI device initialization related procedures.
124 ***************************************************************************/
127 void RT2860RejectPendingPackets(struct rt_rtmp_adapter *pAd)
129 /* clear PS packets */
130 /* clear TxSw packets */
133 static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state)
135 struct net_device *net_dev = pci_get_drvdata(pci_dev);
136 struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
139 DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_suspend()\n"));
141 if (net_dev == NULL) {
142 DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
144 GET_PAD_FROM_NET_DEV(pAd, net_dev);
146 /* we can not use IFF_UP because ra0 down but ra1 up */
147 /* and 1 suspend/resume function for 1 module, not for each interface */
148 /* so Linux will call suspend/resume function once */
149 if (VIRTUAL_IF_NUM(pAd) > 0) {
150 /* avoid users do suspend after interface is down */
153 netif_carrier_off(net_dev);
154 netif_stop_queue(net_dev);
156 /* mark device as removed from system and therefore no longer available */
157 netif_device_detach(net_dev);
160 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
161 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
163 /* take down the device */
164 rt28xx_close((struct net_device *)net_dev);
166 RT_MOD_DEC_USE_COUNT();
170 /* reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html */
171 /* enable device to generate PME# when suspended */
172 /* pci_choose_state(): Choose the power state of a PCI device to be suspended */
173 retval = pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state), 1);
174 /* save the PCI configuration space of a device before suspending */
175 pci_save_state(pci_dev);
176 /* disable PCI device after use */
177 pci_disable_device(pci_dev);
179 retval = pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
181 DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_suspend()\n"));
185 static int rt2860_resume(struct pci_dev *pci_dev)
187 struct net_device *net_dev = pci_get_drvdata(pci_dev);
188 struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
191 /* set the power state of a PCI device */
192 /* PCI has 4 power states, DO (normal) ~ D3(less power) */
193 /* in include/linux/pci.h, you can find that */
194 /* #define PCI_D0 ((pci_power_t __force) 0) */
195 /* #define PCI_D1 ((pci_power_t __force) 1) */
196 /* #define PCI_D2 ((pci_power_t __force) 2) */
197 /* #define PCI_D3hot ((pci_power_t __force) 3) */
198 /* #define PCI_D3cold ((pci_power_t __force) 4) */
199 /* #define PCI_UNKNOWN ((pci_power_t __force) 5) */
200 /* #define PCI_POWER_ERROR ((pci_power_t __force) -1) */
201 retval = pci_set_power_state(pci_dev, PCI_D0);
203 /* restore the saved state of a PCI device */
204 pci_restore_state(pci_dev);
206 /* initialize device before it's used by a driver */
207 if (pci_enable_device(pci_dev)) {
208 printk("pci enable fail!\n");
212 DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_resume()\n"));
215 DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
217 GET_PAD_FROM_NET_DEV(pAd, net_dev);
220 /* we can not use IFF_UP because ra0 down but ra1 up */
221 /* and 1 suspend/resume function for 1 module, not for each interface */
222 /* so Linux will call suspend/resume function once */
223 if (VIRTUAL_IF_NUM(pAd) > 0) {
224 /* mark device as attached from system and restart if needed */
225 netif_device_attach(net_dev);
227 if (rt28xx_open((struct net_device *)net_dev) != 0) {
229 DBGPRINT(RT_DEBUG_TRACE,
230 ("<=== rt2860_resume()\n"));
233 /* increase MODULE use count */
234 RT_MOD_INC_USE_COUNT();
236 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
237 RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
239 netif_start_queue(net_dev);
240 netif_carrier_on(net_dev);
241 netif_wake_queue(net_dev);
245 DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
248 #endif /* CONFIG_PM // */
250 static int __init rt2860_init_module(void)
252 return pci_register_driver(&rt2860_driver);
256 /* Driver module unload function */
258 static void __exit rt2860_cleanup_module(void)
260 pci_unregister_driver(&rt2860_driver);
263 module_init(rt2860_init_module);
264 module_exit(rt2860_cleanup_module);
267 /* PCI device probe & initialization function */
269 static int __devinit rt2860_probe(IN struct pci_dev *pci_dev,
270 IN const struct pci_device_id *pci_id)
272 struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
273 struct net_device *net_dev;
276 unsigned long csr_addr;
278 struct rt_rtmp_os_netdev_op_hook netDevHook;
280 DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_probe\n"));
282 /*PCIDevInit============================================== */
283 /* wake up and enable device */
284 rv = pci_enable_device(pci_dev);
287 DBGPRINT(RT_DEBUG_ERROR,
288 ("Enable PCI device failed, errno=%d!\n", rv));
292 print_name = (char *)pci_name(pci_dev);
294 rv = pci_request_regions(pci_dev, print_name);
297 DBGPRINT(RT_DEBUG_ERROR,
298 ("Request PCI resource failed, errno=%d!\n", rv));
301 /* map physical address to virtual address for accessing register */
303 (unsigned long)ioremap(pci_resource_start(pci_dev, 0),
304 pci_resource_len(pci_dev, 0));
306 DBGPRINT(RT_DEBUG_ERROR,
307 ("ioremap failed for device %s, region 0x%lX @ 0x%lX\n",
308 print_name, (unsigned long)pci_resource_len(pci_dev, 0),
309 (unsigned long)pci_resource_start(pci_dev, 0)));
310 goto err_out_free_res;
312 DBGPRINT(RT_DEBUG_TRACE,
313 ("%s: at 0x%lx, VA 0x%lx, IRQ %d. \n", print_name,
314 (unsigned long)pci_resource_start(pci_dev, 0),
315 (unsigned long)csr_addr, pci_dev->irq));
319 pci_set_master(pci_dev);
321 /*RtmpDevInit============================================== */
322 /* Allocate struct rt_rtmp_adapter adapter structure */
323 handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
324 if (handle == NULL) {
325 DBGPRINT(RT_DEBUG_ERROR,
326 ("%s(): Allocate memory for os handle failed!\n",
328 goto err_out_iounmap;
331 ((struct os_cookie *)handle)->pci_dev = pci_dev;
333 rv = RTMPAllocAdapterBlock(handle, &pAd); /*shiang: we may need the pci_dev for allocate structure of "struct rt_rtmp_adapter" */
334 if (rv != NDIS_STATUS_SUCCESS)
335 goto err_out_iounmap;
336 /* Here are the struct rt_rtmp_adapter structure with pci-bus specific parameters. */
337 pAd->CSRBaseAddress = (u8 *)csr_addr;
338 DBGPRINT(RT_DEBUG_ERROR,
339 ("pAd->CSRBaseAddress =0x%lx, csr_addr=0x%lx!\n",
340 (unsigned long)pAd->CSRBaseAddress, csr_addr));
341 RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI);
343 /*NetDevInit============================================== */
344 net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
346 goto err_out_free_radev;
348 /* Here are the net_device structure with pci-bus specific parameters. */
349 net_dev->irq = pci_dev->irq; /* Interrupt IRQ number */
350 net_dev->base_addr = csr_addr; /* Save CSR virtual address and irq to device structure */
351 pci_set_drvdata(pci_dev, net_dev); /* Set driver data */
353 /* for supporting Network Manager */
354 /* Set the sysfs physical device reference for the network logical device
355 * if set prior to registration will cause a symlink during initialization.
357 SET_NETDEV_DEV(net_dev, &(pci_dev->dev));
359 /*All done, it's time to register the net device to linux kernel. */
360 /* Register this device */
361 rv = RtmpOSNetDevAttach(net_dev, &netDevHook);
363 goto err_out_free_netdev;
365 pAd->StaCfg.OriDevType = net_dev->type;
366 RTMPInitPCIeDevice(pci_dev, pAd);
368 DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_probe\n"));
370 return 0; /* probe ok */
372 /* --------------------------- ERROR HANDLE --------------------------- */
374 RtmpOSNetDevFree(net_dev);
377 /* free struct rt_rtmp_adapter strcuture and os_cookie */
378 RTMPFreeAdapter(pAd);
381 iounmap((void *)(csr_addr));
382 release_mem_region(pci_resource_start(pci_dev, 0),
383 pci_resource_len(pci_dev, 0));
386 pci_release_regions(pci_dev);
389 pci_disable_device(pci_dev);
391 DBGPRINT(RT_DEBUG_ERROR,
392 ("<=== rt2860_probe failed with rv = %d!\n", rv));
394 return -ENODEV; /* probe fail */
397 static void __devexit rt2860_remove_one(IN struct pci_dev *pci_dev)
399 struct net_device *net_dev = pci_get_drvdata(pci_dev);
400 struct rt_rtmp_adapter *pAd = NULL;
401 unsigned long csr_addr = net_dev->base_addr; /* pAd->CSRBaseAddress; */
403 GET_PAD_FROM_NET_DEV(pAd, net_dev);
405 DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n"));
408 /* Unregister/Free all allocated net_device. */
409 RtmpPhyNetDevExit(pAd, net_dev);
411 /* Unmap CSR base address */
412 iounmap((char *)(csr_addr));
414 /* release memory region */
415 release_mem_region(pci_resource_start(pci_dev, 0),
416 pci_resource_len(pci_dev, 0));
418 /* Free struct rt_rtmp_adapter related structures. */
419 RtmpRaDevCtrlExit(pAd);
422 /* Unregister network device */
423 RtmpOSNetDevDetach(net_dev);
425 /* Unmap CSR base address */
426 iounmap((char *)(net_dev->base_addr));
428 /* release memory region */
429 release_mem_region(pci_resource_start(pci_dev, 0),
430 pci_resource_len(pci_dev, 0));
433 /* Free the root net_device */
434 RtmpOSNetDevFree(net_dev);
439 ========================================================================
441 Check the chipset vendor/product ID.
444 _dev_p Point to the PCI or USB device
451 ========================================================================
453 BOOLEAN RT28XXChipsetCheck(IN void *_dev_p)
459 /***************************************************************************
461 * PCIe device initialization related procedures.
463 ***************************************************************************/
464 static void RTMPInitPCIeDevice(struct pci_dev *pci_dev, struct rt_rtmp_adapter *pAd)
467 struct os_cookie *pObj;
469 pObj = (struct os_cookie *)pAd->OS_Cookie;
470 pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id);
471 device_id = le2cpu16(device_id);
472 pObj->DeviceID = device_id;
475 (device_id == NIC2860_PCIe_DEVICE_ID) ||
476 (device_id == NIC2790_PCIe_DEVICE_ID) ||
477 (device_id == VEN_AWT_PCIe_DEVICE_ID) ||
480 (device_id == NIC3090_PCIe_DEVICE_ID) ||
481 (device_id == NIC3091_PCIe_DEVICE_ID) ||
482 (device_id == NIC3092_PCIe_DEVICE_ID) ||
483 #endif /* RT3090 // */
485 u32 MacCsr0 = 0, Index = 0;
487 RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
489 if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
493 } while (Index++ < 100);
495 /* Support advanced power save after 2892/2790. */
496 /* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */
497 if ((MacCsr0 & 0xffff0000) != 0x28600000)
498 OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
502 void RTMPInitPCIeLinkCtrlValue(struct rt_rtmp_adapter *pAd)
505 u16 reg16, data2, PCIePowerSaveLevel, Configuration;
507 BOOLEAN bFindIntel = FALSE;
508 struct os_cookie *pObj;
510 pObj = (struct os_cookie *)pAd->OS_Cookie;
512 if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
515 DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
516 /* Init EEPROM, and save settings */
517 if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
518 RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
519 pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
521 pAd->LnkCtrlBitMask = 0;
522 if ((PCIePowerSaveLevel & 0xff) == 0xff) {
523 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
524 DBGPRINT(RT_DEBUG_TRACE,
525 ("====> PCIePowerSaveLevel = 0x%x.\n",
526 PCIePowerSaveLevel));
529 PCIePowerSaveLevel &= 0x3;
530 RT28xx_EEPROM_READ16(pAd, 0x24, data2);
533 (((data2 & 0xff00) == 0x9200)
534 && ((data2 & 0x80) != 0))) {
535 if (PCIePowerSaveLevel > 1)
536 PCIePowerSaveLevel = 1;
539 DBGPRINT(RT_DEBUG_TRACE,
540 ("====> Write 0x83 = 0x%x.\n",
541 PCIePowerSaveLevel));
542 AsicSendCommandToMcu(pAd, 0x83, 0xff,
543 (u8)PCIePowerSaveLevel, 0x00);
544 RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
545 PCIePowerSaveLevel &= 0xff;
546 PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
547 switch (PCIePowerSaveLevel) {
548 case 0: /* Only support L0 */
549 pAd->LnkCtrlBitMask = 0;
551 case 1: /* Only enable L0s */
552 pAd->LnkCtrlBitMask = 1;
554 case 2: /* enable L1, L0s */
555 pAd->LnkCtrlBitMask = 3;
557 case 3: /* sync with host clk and enable L1, L0s */
558 pAd->LnkCtrlBitMask = 0x103;
561 RT28xx_EEPROM_READ16(pAd, 0x24, data2);
562 if ((PCIePowerSaveLevel & 0xff) != 0xff) {
563 PCIePowerSaveLevel &= 0x3;
566 (((data2 & 0xff00) == 0x9200)
567 && ((data2 & 0x80) != 0))) {
568 if (PCIePowerSaveLevel > 1)
569 PCIePowerSaveLevel = 1;
572 DBGPRINT(RT_DEBUG_TRACE,
573 ("====> rt28xx Write 0x83 Command = 0x%x.\n",
574 PCIePowerSaveLevel));
576 AsicSendCommandToMcu(pAd, 0x83, 0xff,
577 (u8)PCIePowerSaveLevel,
580 DBGPRINT(RT_DEBUG_TRACE,
581 ("====> LnkCtrlBitMask = 0x%x.\n",
582 pAd->LnkCtrlBitMask));
584 } else if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
585 u8 LinkCtrlSetting = 0;
587 /* Check 3090E special setting chip. */
588 RT28xx_EEPROM_READ16(pAd, 0x24, data2);
589 if ((data2 == 0x9280) && ((pAd->MACVersion & 0xffff) == 0x0211)) {
590 pAd->b3090ESpecialChip = TRUE;
591 DBGPRINT_RAW(RT_DEBUG_ERROR, ("Special 3090E chip \n"));
594 RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
595 /*enable WAKE_PCIE function, which forces to enable PCIE clock when mpu interrupt asserting. */
596 /*Force PCIE 125MHz CLK to toggle */
598 RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
599 DBGPRINT_RAW(RT_DEBUG_ERROR,
600 (" AUX_CTRL = 0x%32x\n", MacValue));
602 /* for RT30xx F and after, PCIe infterface, and for power solution 3 */
603 if ((IS_VERSION_AFTER_F(pAd))
604 && (pAd->StaCfg.PSControl.field.rt30xxPowerMode >= 2)
605 && (pAd->StaCfg.PSControl.field.rt30xxPowerMode <= 3)) {
606 RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
607 DBGPRINT_RAW(RT_DEBUG_ERROR,
608 (" Read AUX_CTRL = 0x%x\n", MacValue));
609 /* turn on bit 12. */
610 /*enable 32KHz clock mode for power saving */
612 if (MacValue != 0xffffffff) {
613 RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
614 DBGPRINT_RAW(RT_DEBUG_ERROR,
615 (" Write AUX_CTRL = 0x%x\n",
617 /* 1. if use PCIePowerSetting is 2 or 3, need to program OSC_CTRL to 0x3ff11. */
619 RTMP_IO_WRITE32(pAd, OSC_CTRL, MacValue);
620 DBGPRINT_RAW(RT_DEBUG_ERROR,
621 (" OSC_CTRL = 0x%x\n", MacValue));
622 /* 2. Write PCI register Clk ref bit */
623 RTMPrt3xSetPCIePowerLinkCtrl(pAd);
625 /* Error read Aux_Ctrl value. Force to use solution 1 */
626 DBGPRINT(RT_DEBUG_ERROR,
627 (" Error Value in AUX_CTRL = 0x%x\n",
629 pAd->StaCfg.PSControl.field.rt30xxPowerMode = 1;
630 DBGPRINT(RT_DEBUG_ERROR,
631 (" Force to use power solution1 \n"));
634 /* 1. read setting from inf file. */
637 (u16)pAd->StaCfg.PSControl.field.rt30xxPowerMode;
638 DBGPRINT(RT_DEBUG_ERROR,
639 ("====> rt30xx Read PowerLevelMode = 0x%x.\n",
640 PCIePowerSaveLevel));
641 /* 2. Check EnableNewPS. */
642 if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
643 PCIePowerSaveLevel = 1;
645 if (IS_VERSION_BEFORE_F(pAd)
646 && (pAd->b3090ESpecialChip == FALSE)) {
647 /* Chip Version E only allow 1, So force set 1. */
648 PCIePowerSaveLevel &= 0x1;
649 pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
650 DBGPRINT(RT_DEBUG_TRACE,
651 ("====> rt30xx E Write 0x83 Command = 0x%x.\n",
652 PCIePowerSaveLevel));
654 AsicSendCommandToMcu(pAd, 0x83, 0xff,
655 (u8)PCIePowerSaveLevel, 0x00);
657 /* Chip Version F and after only allow 1 or 2 or 3. This might be modified after new chip version come out. */
659 ((PCIePowerSaveLevel == 1)
660 || (PCIePowerSaveLevel == 3)))
661 PCIePowerSaveLevel = 1;
662 DBGPRINT(RT_DEBUG_ERROR,
663 ("====> rt30xx F Write 0x83 Command = 0x%x.\n",
664 PCIePowerSaveLevel));
665 pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
666 /* for 3090F , we need to add high-byte arg for 0x83 command to indicate the link control setting in */
667 /* PCI Configuration Space. Because firmware can't read PCI Configuration Space */
668 if ((pAd->Rt3xxRalinkLinkCtrl & 0x2)
669 && (pAd->Rt3xxHostLinkCtrl & 0x2)) {
672 DBGPRINT(RT_DEBUG_TRACE,
673 ("====> rt30xxF LinkCtrlSetting = 0x%x.\n",
675 AsicSendCommandToMcu(pAd, 0x83, 0xff,
676 (u8)PCIePowerSaveLevel,
680 /* Find Ralink PCIe Device's Express Capability Offset */
681 pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
684 /* Ralink PCIe Device's Link Control Register Offset */
685 pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
686 pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
688 Configuration = le2cpu16(reg16);
689 DBGPRINT(RT_DEBUG_TRACE,
690 ("Read (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
691 pAd->RLnkCtrlOffset, Configuration));
692 pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
693 Configuration &= 0xfefc;
694 Configuration |= (0x0);
696 if ((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
697 || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)) {
698 reg16 = cpu2le16(Configuration);
699 pci_write_config_word(pObj->pci_dev,
700 pAd->RLnkCtrlOffset, reg16);
701 DBGPRINT(RT_DEBUG_TRACE,
702 ("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
703 pos + PCI_EXP_LNKCTL, Configuration));
705 #endif /* RT2860 // */
707 RTMPFindHostPCIDev(pAd);
708 if (pObj->parent_pci_dev) {
711 pci_read_config_word(pObj->parent_pci_dev,
712 PCI_VENDOR_ID, &vendor_id);
713 vendor_id = le2cpu16(vendor_id);
714 if (vendor_id == PCIBUS_INTEL_VENDOR) {
716 RTMP_SET_PSFLAG(pAd, fRTMP_PS_TOGGLE_L1);
718 /* Find PCI-to-PCI Bridge Express Capability Offset */
720 pci_find_capability(pObj->parent_pci_dev,
724 BOOLEAN bChange = FALSE;
725 /* PCI-to-PCI Bridge Link Control Register Offset */
726 pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
727 pci_read_config_word(pObj->parent_pci_dev,
728 pAd->HostLnkCtrlOffset,
730 Configuration = le2cpu16(reg16);
731 DBGPRINT(RT_DEBUG_TRACE,
732 ("Read (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
733 pAd->HostLnkCtrlOffset,
735 pAd->HostLnkCtrlConfiguration =
736 (Configuration & 0x103);
737 Configuration &= 0xfefc;
738 Configuration |= (0x0);
740 switch (pObj->DeviceID) {
742 case NIC2860_PCIe_DEVICE_ID:
743 case NIC2790_PCIe_DEVICE_ID:
746 #endif /* RT2860 // */
748 case NIC3090_PCIe_DEVICE_ID:
749 case NIC3091_PCIe_DEVICE_ID:
750 case NIC3092_PCIe_DEVICE_ID:
751 if (bFindIntel == FALSE)
754 #endif /* RT3090 // */
760 reg16 = cpu2le16(Configuration);
761 pci_write_config_word(pObj->
766 DBGPRINT(RT_DEBUG_TRACE,
767 ("Write (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
768 pAd->HostLnkCtrlOffset,
772 pAd->HostLnkCtrlOffset = 0;
773 DBGPRINT(RT_DEBUG_ERROR,
774 ("%s: cannot find PCI-to-PCI Bridge PCI Express Capability!\n",
779 pAd->RLnkCtrlOffset = 0;
780 pAd->HostLnkCtrlOffset = 0;
781 DBGPRINT(RT_DEBUG_ERROR,
782 ("%s: cannot find Ralink PCIe Device's PCI Express Capability!\n",
786 if (bFindIntel == FALSE) {
787 DBGPRINT(RT_DEBUG_TRACE,
788 ("Doesn't find Intel PCI host controller. \n"));
789 /* Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff */
790 pAd->PCIePowerSaveLevel = 0xff;
791 if ((pAd->RLnkCtrlOffset != 0)
793 && ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
794 || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
795 || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
796 #endif /* RT3090 // */
798 pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
800 Configuration = le2cpu16(reg16);
801 DBGPRINT(RT_DEBUG_TRACE,
802 ("Read (Ralink 30xx PCIe Link Control Register) offset 0x%x = 0x%x\n",
803 pAd->RLnkCtrlOffset, Configuration));
804 pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
805 Configuration &= 0xfefc;
806 Configuration |= (0x0);
807 reg16 = cpu2le16(Configuration);
808 pci_write_config_word(pObj->pci_dev,
809 pAd->RLnkCtrlOffset, reg16);
810 DBGPRINT(RT_DEBUG_TRACE,
811 ("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
812 pos + PCI_EXP_LNKCTL, Configuration));
817 void RTMPFindHostPCIDev(struct rt_rtmp_adapter *pAd)
822 struct pci_dev *pPci_dev;
823 struct os_cookie *pObj;
825 pObj = (struct os_cookie *)pAd->OS_Cookie;
827 if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
830 DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
832 pObj->parent_pci_dev = NULL;
833 if (pObj->pci_dev->bus->parent) {
834 for (DevFn = 0; DevFn < 255; DevFn++) {
836 pci_get_slot(pObj->pci_dev->bus->parent, DevFn);
838 pci_read_config_word(pPci_dev, PCI_CLASS_DEVICE,
840 reg16 = le2cpu16(reg16);
841 pci_read_config_byte(pPci_dev, PCI_CB_CARD_BUS,
843 if ((reg16 == PCI_CLASS_BRIDGE_PCI)
844 && (reg8 == pObj->pci_dev->bus->number)) {
845 pObj->parent_pci_dev = pPci_dev;
853 ========================================================================
858 Level = RESTORE_HALT : Restore PCI host and Ralink PCIe Link Control field to its default value.
859 Level = Other Value : Restore from dot11 power save or radio off status. And force PCI host Link Control fields to 0x1
861 ========================================================================
863 void RTMPPCIeLinkCtrlValueRestore(struct rt_rtmp_adapter *pAd, u8 Level)
865 u16 PCIePowerSaveLevel, reg16;
867 struct os_cookie *pObj;
869 pObj = (struct os_cookie *)pAd->OS_Cookie;
871 if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
875 if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
876 || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
878 #endif /* RT2860 // */
879 /* Check PSControl Configuration */
880 if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
883 /*3090 will not execute the following codes. */
884 /* Check interface : If not PCIe interface, return. */
887 if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
888 || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
889 || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
891 #endif /* RT3090 // */
893 DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
894 PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
895 if ((PCIePowerSaveLevel & 0xff) == 0xff) {
896 DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
900 if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
901 PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
903 if ((Configuration != 0) && (Configuration != 0xFFFF)) {
904 Configuration &= 0xfefc;
905 /* If call from interface down, restore to orginial setting. */
906 if (Level == RESTORE_CLOSE)
907 Configuration |= pAd->HostLnkCtrlConfiguration;
909 Configuration |= 0x0;
910 PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
911 pAd->HostLnkCtrlOffset,
913 DBGPRINT(RT_DEBUG_TRACE,
914 ("Restore PCI host : offset 0x%x = 0x%x\n",
915 pAd->HostLnkCtrlOffset, Configuration));
917 DBGPRINT(RT_DEBUG_ERROR,
918 ("Restore PCI host : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
922 if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
923 PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
925 if ((Configuration != 0) && (Configuration != 0xFFFF)) {
926 Configuration &= 0xfefc;
927 /* If call from interface down, restore to orginial setting. */
928 if (Level == RESTORE_CLOSE)
929 Configuration |= pAd->RLnkCtrlConfiguration;
931 Configuration |= 0x0;
932 PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
934 DBGPRINT(RT_DEBUG_TRACE,
935 ("Restore Ralink : offset 0x%x = 0x%x\n",
936 pAd->RLnkCtrlOffset, Configuration));
938 DBGPRINT(RT_DEBUG_ERROR,
939 ("Restore Ralink : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
943 DBGPRINT(RT_DEBUG_TRACE, ("%s <===\n", __func__));
947 ========================================================================
952 Max : limit Host PCI and Ralink PCIe device's LINK CONTROL field's value.
953 Because now frequently set our device to mode 1 or mode 3 will cause problem.
955 ========================================================================
957 void RTMPPCIeLinkCtrlSetting(struct rt_rtmp_adapter *pAd, u16 Max)
959 u16 PCIePowerSaveLevel, reg16;
961 struct os_cookie *pObj;
963 pObj = (struct os_cookie *)pAd->OS_Cookie;
965 if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
969 if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
970 || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
972 #endif /* RT2860 // */
973 /* Check PSControl Configuration */
974 if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
977 /* Check interface : If not PCIe interface, return. */
978 /*Block 3090 to enter the following function */
981 if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
982 || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
983 || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
985 #endif /* RT3090 // */
986 if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) {
987 DBGPRINT(RT_DEBUG_INFO,
988 ("RTMPPCIePowerLinkCtrl return on fRTMP_PS_CAN_GO_SLEEP flag\n"));
992 DBGPRINT(RT_DEBUG_TRACE, ("%s===>\n", __func__));
993 PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
994 if ((PCIePowerSaveLevel & 0xff) == 0xff) {
995 DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
998 PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
1000 /* Skip non-exist deice right away */
1001 if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
1002 PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
1004 switch (PCIePowerSaveLevel) {
1006 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 */
1007 Configuration &= 0xfefc;
1010 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 */
1011 Configuration &= 0xfefc;
1012 Configuration |= 0x1;
1015 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
1016 Configuration &= 0xfefc;
1017 Configuration |= 0x3;
1020 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
1021 Configuration &= 0xfefc;
1022 Configuration |= 0x103;
1025 PCI_REG_WIRTE_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
1027 DBGPRINT(RT_DEBUG_TRACE,
1028 ("Write PCI host offset 0x%x = 0x%x\n",
1029 pAd->HostLnkCtrlOffset, Configuration));
1032 if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
1033 /* first 2892 chip not allow to frequently set mode 3. will cause hang problem. */
1034 if (PCIePowerSaveLevel > Max)
1035 PCIePowerSaveLevel = Max;
1037 PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
1039 switch (PCIePowerSaveLevel) {
1041 /* No PCI power safe */
1042 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 . */
1043 Configuration &= 0xfefc;
1047 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 . */
1048 Configuration &= 0xfefc;
1049 Configuration |= 0x1;
1053 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
1054 Configuration &= 0xfefc;
1055 Configuration |= 0x3;
1058 /* L0 , L1 and clock management. */
1059 /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
1060 Configuration &= 0xfefc;
1061 Configuration |= 0x103;
1062 pAd->bPCIclkOff = TRUE;
1065 PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
1067 DBGPRINT(RT_DEBUG_TRACE,
1068 ("Write Ralink device : offset 0x%x = 0x%x\n",
1069 pAd->RLnkCtrlOffset, Configuration));
1072 DBGPRINT(RT_DEBUG_TRACE, ("RTMPPCIePowerLinkCtrl <==============\n"));
1076 ========================================================================
1078 Routine Description:
1079 1. Write a PCI register for rt30xx power solution 3
1081 ========================================================================
1083 void RTMPrt3xSetPCIePowerLinkCtrl(struct rt_rtmp_adapter *pAd)
1086 unsigned long HostConfiguration = 0;
1087 unsigned long Configuration;
1088 struct os_cookie *pObj;
1092 pObj = (struct os_cookie *)pAd->OS_Cookie;
1094 DBGPRINT(RT_DEBUG_INFO,
1095 ("RTMPrt3xSetPCIePowerLinkCtrl.===> %lx\n",
1096 pAd->StaCfg.PSControl.word));
1098 /* Check PSControl Configuration */
1099 if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
1101 RTMPFindHostPCIDev(pAd);
1102 if (pObj->parent_pci_dev) {
1103 /* Find PCI-to-PCI Bridge Express Capability Offset */
1104 pos = pci_find_capability(pObj->parent_pci_dev, PCI_CAP_ID_EXP);
1107 pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
1109 /* If configurared to turn on L1. */
1110 HostConfiguration = 0;
1111 if (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1) {
1112 DBGPRINT(RT_DEBUG_TRACE, ("Enter,PSM : Force ASPM\n"));
1114 /* Skip non-exist deice right away */
1115 if ((pAd->HostLnkCtrlOffset != 0)) {
1116 PCI_REG_READ_WORD(pObj->parent_pci_dev,
1117 pAd->HostLnkCtrlOffset,
1119 /* Prepare Configuration to write to Host */
1120 HostConfiguration |= 0x3;
1121 PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
1122 pAd->HostLnkCtrlOffset,
1124 pAd->Rt3xxHostLinkCtrl = HostConfiguration;
1125 /* Because in rt30xxForceASPMTest Mode, Force turn on L0s, L1. */
1126 /* Fix HostConfiguration bit0:1 = 0x3 for later use. */
1127 HostConfiguration = 0x3;
1128 DBGPRINT(RT_DEBUG_TRACE,
1129 ("PSM : Force ASPM : "
1130 "Host device L1/L0s Value = 0x%lx\n",
1131 HostConfiguration));
1133 } else if (pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM ==
1136 /* Skip non-exist deice right away */
1137 if ((pAd->HostLnkCtrlOffset != 0)) {
1138 PCI_REG_READ_WORD(pObj->parent_pci_dev,
1139 pAd->HostLnkCtrlOffset,
1141 pAd->Rt3xxHostLinkCtrl = HostConfiguration;
1142 HostConfiguration &= 0x3;
1143 DBGPRINT(RT_DEBUG_TRACE,
1144 ("PSM : Follow Host ASPM : "
1145 "Host device L1/L0s Value = 0x%lx\n",
1146 HostConfiguration));
1150 /* Prepare to write Ralink setting. */
1151 /* Find Ralink PCIe Device's Express Capability Offset */
1152 pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
1155 /* Ralink PCIe Device's Link Control Register Offset */
1156 pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
1157 pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
1159 Configuration = le2cpu16(reg16);
1160 DBGPRINT(RT_DEBUG_TRACE,
1161 ("Read (Ralink PCIe Link Control Register) "
1162 "offset 0x%x = 0x%lx\n",
1163 pAd->RLnkCtrlOffset, Configuration));
1164 Configuration |= 0x100;
1165 if ((pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM == 1)
1166 || (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1)) {
1167 switch (HostConfiguration) {
1169 Configuration &= 0xffffffc;
1172 Configuration &= 0xffffffc;
1173 Configuration |= 0x1;
1176 Configuration &= 0xffffffc;
1177 Configuration |= 0x2;
1180 Configuration |= 0x3;
1184 reg16 = cpu2le16(Configuration);
1185 pci_write_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
1187 pAd->Rt3xxRalinkLinkCtrl = Configuration;
1188 DBGPRINT(RT_DEBUG_TRACE,
1189 ("PSM :Write Ralink device L1/L0s Value = 0x%lx\n",
1192 DBGPRINT(RT_DEBUG_INFO,
1193 ("PSM :RTMPrt3xSetPCIePowerLinkCtrl <==============\n"));