drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2   This is part of the rtl8180-sa2400 driver
   3   released under the GPL (See file COPYING for details).
   4   Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5
   6   This files contains programming code for the rtl8225
   7   radio frontend.
   8
   9   *Many* thanks to Realtek Corp. for their great support!
  10
  11 */
  12
  13 #include "r8180_hw.h"
  14 #include "r8180_rtl8225.h"
  15 #include "r8180_93cx6.h"
  16
  17 #include "ieee80211/dot11d.h"
  18
  19
  20 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
  21 {
  22         int i;
  23         u16 out, select;
  24         u8 bit;
  25         u32 bangdata = (data << 4) | (adr & 0xf);
  26         struct r8180_priv *priv = ieee80211_priv(dev);
  27
  28         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
  29
  30         write_nic_word(dev, RFPinsEnable,
  31                 (read_nic_word(dev, RFPinsEnable) | 0x7));
  32
  33         select = read_nic_word(dev, RFPinsSelect);
  34
  35         write_nic_word(dev, RFPinsSelect, select | 0x7 |
  36                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  37
  38         force_pci_posting(dev);
  39         udelay(10);
  40
  41         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  42
  43         force_pci_posting(dev);
  44         udelay(2);
  45
  46         write_nic_word(dev, RFPinsOutput, out);
  47
  48         force_pci_posting(dev);
  49         udelay(10);
  50
  51         for (i = 15; i >= 0; i--) {
  52                 bit = (bangdata & (1 << i)) >> i;
  53
  54                 write_nic_word(dev, RFPinsOutput, bit | out);
  55
  56                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  57                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  58
  59                 i--;
  60                 bit = (bangdata & (1 << i)) >> i;
  61
  62                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  63                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  64
  65                 write_nic_word(dev, RFPinsOutput, bit | out);
  66
  67         }
  68
  69         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  70
  71         force_pci_posting(dev);
  72         udelay(10);
  73
  74         write_nic_word(dev, RFPinsOutput, out |
  75                 ((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
  76
  77         write_nic_word(dev, RFPinsSelect, select |
  78                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  79
  80         if (priv->card_type == USB)
  81                 mdelay(2);
  82         else
  83                 rtl8185_rf_pins_enable(dev);
  84 }
  85
  86 static const u16 rtl8225bcd_rxgain[] = {
  87         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
  88         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
  89         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
  90         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
  91         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
  92         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
  93         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
  94         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
  95         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
  96         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
  97         0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
  98         0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
  99
 100 };
 101
 102 static const u8 rtl8225_agc[] = {
 103         0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
 104         0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
 105         0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
 106         0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
 107         0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
 108         0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
 109         0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
 110         0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
 111         0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
 112         0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
 113         0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
 114         0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
 115         0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
 116         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 117         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 118         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 119 };
 120
 121 static const u8 rtl8225_gain[] = {
 122         0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
 123         0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
 124         0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
 125         0x33, 0x80, 0x79, 0xc5, /* -78dBm */
 126         0x43, 0x78, 0x76, 0xc5, /* -74dBm */
 127         0x53, 0x60, 0x73, 0xc5, /* -70dBm */
 128         0x63, 0x58, 0x70, 0xc5, /* -66dBm */
 129 };
 130
 131 static const u8 rtl8225_tx_gain_cck_ofdm[] = {
 132         0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
 133 };
 134
 135 static const u8 rtl8225_tx_power_cck[] = {
 136         0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
 137         0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
 138         0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
 139         0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
 140         0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
 141         0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
 142 };
 143
 144 static const u8 rtl8225_tx_power_cck_ch14[] = {
 145         0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
 146         0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
 147         0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
 148         0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
 149         0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
 150         0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
 151 };
 152
 153 static const u8 rtl8225_tx_power_ofdm[] = {
 154         0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
 155 };
 156
 157 static const u32 rtl8225_chan[] = {
 158         0,
 159         0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
 160         0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
 161 };
 162
 163 static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
 164 {
 165         struct r8180_priv *priv = ieee80211_priv(dev);
 166         int GainIdx;
 167         int GainSetting;
 168         int i;
 169         u8 power;
 170         const u8 *cck_power_table;
 171         u8 max_cck_power_level;
 172         u8 max_ofdm_power_level;
 173         u8 min_ofdm_power_level;
 174         u8 cck_power_level = 0xff & priv->chtxpwr[ch];
 175         u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
 176
 177         if (priv->card_type == USB) {
 178                 max_cck_power_level = 11;
 179                 max_ofdm_power_level = 25;
 180                 min_ofdm_power_level = 10;
 181         } else {
 182                 max_cck_power_level = 35;
 183                 max_ofdm_power_level = 35;
 184                 min_ofdm_power_level = 0;
 185         }
 186
 187         if (cck_power_level > max_cck_power_level)
 188                 cck_power_level = max_cck_power_level;
 189
 190         GainIdx = cck_power_level % 6;
 191         GainSetting = cck_power_level / 6;
 192
 193         if (ch == 14)
 194                 cck_power_table = rtl8225_tx_power_cck_ch14;
 195         else
 196                 cck_power_table = rtl8225_tx_power_cck;
 197
 198         write_nic_byte(dev, TX_GAIN_CCK,
 199                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 200
 201         for (i = 0; i < 8; i++) {
 202                 power = cck_power_table[GainIdx * 8 + i];
 203                 write_phy_cck(dev, 0x44 + i, power);
 204         }
 205
 206         /* FIXME Is this delay really needeed ? */
 207         force_pci_posting(dev);
 208         mdelay(1);
 209
 210         if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
 211                 ofdm_power_level = max_ofdm_power_level;
 212         else
 213                 ofdm_power_level += min_ofdm_power_level;
 214
 215         if (ofdm_power_level > 35)
 216                 ofdm_power_level = 35;
 217
 218         GainIdx = ofdm_power_level % 6;
 219         GainSetting = ofdm_power_level / 6;
 220
 221         rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
 222
 223         write_phy_ofdm(dev, 2, 0x42);
 224         write_phy_ofdm(dev, 6, 0x00);
 225         write_phy_ofdm(dev, 8, 0x00);
 226
 227         write_nic_byte(dev, TX_GAIN_OFDM,
 228                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 229
 230         power = rtl8225_tx_power_ofdm[GainIdx];
 231
 232         write_phy_ofdm(dev, 5, power);
 233         write_phy_ofdm(dev, 7, power);
 234
 235         force_pci_posting(dev);
 236         mdelay(1);
 237 }
 238
 239 //2005.11.16
 240 u8 rtl8225z2_threshold[]={
 241         0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
 242 };
 243
 244 //      0xd 0x19 0x1b 0x21
 245 u8 rtl8225z2_gain_bg[]={
 246         0x23, 0x15, 0xa5, // -82-1dbm
 247         0x23, 0x15, 0xb5, // -82-2dbm
 248         0x23, 0x15, 0xc5, // -82-3dbm
 249         0x33, 0x15, 0xc5, // -78dbm
 250         0x43, 0x15, 0xc5, // -74dbm
 251         0x53, 0x15, 0xc5, // -70dbm
 252         0x63, 0x15, 0xc5, // -66dbm
 253 };
 254
 255 u8 rtl8225z2_gain_a[]={
 256         0x13,0x27,0x5a,//,0x37,// -82dbm
 257         0x23,0x23,0x58,//,0x37,// -82dbm
 258         0x33,0x1f,0x56,//,0x37,// -82dbm
 259         0x43,0x1b,0x54,//,0x37,// -78dbm
 260         0x53,0x17,0x51,//,0x37,// -74dbm
 261         0x63,0x24,0x4f,//,0x37,// -70dbm
 262         0x73,0x0f,0x4c,//,0x37,// -66dbm
 263 };
 264
 265 //-
 266 u16 rtl8225z2_rxgain[]={
 267         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 268         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 269         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
 270         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
 271         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
 272         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
 273         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
 274         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
 275         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
 276         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
 277         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
 278         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
 279
 280 };
 281
 282 //2005.11.16,
 283 u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[]={
 284         0x00,0x01,0x02,0x03,0x04,0x05,
 285         0x06,0x07,0x08,0x09,0x0a,0x0b,
 286         0x0c,0x0d,0x0e,0x0f,0x10,0x11,
 287         0x12,0x13,0x14,0x15,0x16,0x17,
 288         0x18,0x19,0x1a,0x1b,0x1c,0x1d,
 289         0x1e,0x1f,0x20,0x21,0x22,0x23,
 290 };
 291
 292 /*
 293  from 0 to 0x23
 294 u8 rtl8225_tx_gain_cck_ofdm[]={
 295         0x02,0x06,0x0e,0x1e,0x3e,0x7e
 296 };
 297 */
 298
 299 //-
 300 u8 rtl8225z2_tx_power_ofdm[]={
 301         0x42,0x00,0x40,0x00,0x40
 302 };
 303
 304
 305 //-
 306 u8 rtl8225z2_tx_power_cck_ch14[]={
 307         0x36,0x35,0x2e,0x1b,0x00,0x00,0x00,0x00
 308 };
 309
 310
 311 //-
 312 u8 rtl8225z2_tx_power_cck[]={
 313         0x36,0x35,0x2e,0x25,0x1c,0x12,0x09,0x04
 314 };
 315
 316
 317 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 318 {
 319         u8* rtl8225_gain;
 320         struct r8180_priv *priv = ieee80211_priv(dev);
 321
 322         u8 mode = priv->ieee80211->mode;
 323
 324         if(mode == IEEE_B || mode == IEEE_G)
 325                 rtl8225_gain = rtl8225z2_gain_bg;
 326         else
 327                 rtl8225_gain = rtl8225z2_gain_a;
 328
 329         //write_phy_ofdm(dev, 0x0d, rtl8225_gain[gain * 3]);
 330         //write_phy_ofdm(dev, 0x19, rtl8225_gain[gain * 3 + 1]);
 331         //write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 2]);
 332         //2005.11.17, by ch-hsu
 333         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 334         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 335         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 336         write_phy_ofdm(dev, 0x21, 0x37);
 337
 338 }
 339
 340 u32 read_rtl8225(struct net_device *dev, u8 adr)
 341 {
 342         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 343         u32 dataRead;
 344         u32 mask;
 345         u16 oval,oval2,oval3,tmp;
 346 //      ThreeWireReg twreg;
 347 //      ThreeWireReg tdata;
 348         int i;
 349         short bit, rw;
 350
 351         u8 wLength = 6;
 352         u8 rLength = 12;
 353         u8 low2high = 0;
 354
 355         oval = read_nic_word(dev, RFPinsOutput);
 356         oval2 = read_nic_word(dev, RFPinsEnable);
 357         oval3 = read_nic_word(dev, RFPinsSelect);
 358
 359         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 360         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 361
 362         dataRead = 0;
 363
 364         oval &= ~0xf;
 365
 366         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
 367
 368         write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
 369
 370         rw = 0;
 371
 372         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 373         for(i = 0; i < wLength/2; i++)
 374         {
 375                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 376                 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
 377
 378                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 379                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 380
 381                 mask = (low2high) ? (mask<<1): (mask>>1);
 382
 383                 if(i == 2)
 384                 {
 385                         rw = BB_HOST_BANG_RW;
 386                         write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 387                         write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
 388                         break;
 389                 }
 390
 391                 bit = ((data2Write&mask) != 0) ? 1: 0;
 392
 393                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 394                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 395
 396                 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
 397
 398                 mask = (low2high) ? (mask<<1) : (mask>>1);
 399         }
 400
 401         //twreg.struc.clk = 0;
 402         //twreg.struc.data = 0;
 403         write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
 404         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 405
 406         // We must set data pin to HW controled, otherwise RF can't driver it and
 407         // value RF register won't be able to read back properly. 2006.06.13, by rcnjko.
 408         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 409
 410         for(i = 0; i < rLength; i++)
 411         {
 412                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 413
 414                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 415                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 416                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 417                 tmp = read_nic_word(dev, RFPinsInput);
 418
 419                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 420
 421                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 422
 423                 mask = (low2high) ? (mask<<1) : (mask>>1);
 424         }
 425
 426         write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
 427
 428         write_nic_word(dev, RFPinsEnable, oval2);
 429         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 430         write_nic_word(dev, RFPinsOutput, 0x3a0);
 431
 432         return dataRead;
 433
 434 }
 435
 436 short rtl8225_is_V_z2(struct net_device *dev)
 437 {
 438         short vz2 = 1;
 439         //int i;
 440         /* sw to reg pg 1 */
 441         //write_rtl8225(dev, 0, 0x1b7);
 442         //write_rtl8225(dev, 0, 0x0b7);
 443
 444         /* reg 8 pg 1 = 23*/
 445         //printk(KERN_WARNING "RF Rigisters:\n");
 446
 447         if( read_rtl8225(dev, 8) != 0x588)
 448                 vz2 = 0;
 449
 450         else    /* reg 9 pg 1 = 24 */
 451                 if( read_rtl8225(dev, 9) != 0x700)
 452                         vz2 = 0;
 453
 454         /* sw back to pg 0 */
 455         write_rtl8225(dev, 0, 0xb7);
 456
 457         return vz2;
 458
 459 }
 460
 461 void rtl8225z2_rf_close(struct net_device *dev)
 462 {
 463         RF_WriteReg(dev, 0x4, 0x1f);
 464
 465         force_pci_posting(dev);
 466         mdelay(1);
 467
 468         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 469         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 470 }
 471
 472 //
 473 //      Description:
 474 //              Map dBm into Tx power index according to
 475 //              current HW model, for example, RF and PA, and
 476 //              current wireless mode.
 477 //
 478 s8
 479 DbmToTxPwrIdx(
 480         struct r8180_priv *priv,
 481         WIRELESS_MODE   WirelessMode,
 482         s32                     PowerInDbm
 483         )
 484 {
 485         bool bUseDefault = true;
 486         s8 TxPwrIdx = 0;
 487
 488         //
 489         // 071011, SD3 SY:
 490         // OFDM Power in dBm = Index * 0.5 + 0
 491         // CCK Power in dBm = Index * 0.25 + 13
 492         //
 493         if(priv->card_8185 >= VERSION_8187S_B)
 494         {
 495                 s32 tmp = 0;
 496
 497                 if(WirelessMode == WIRELESS_MODE_G)
 498                 {
 499                         bUseDefault = false;
 500                         tmp = (2 * PowerInDbm);
 501
 502                         if(tmp < 0)
 503                                 TxPwrIdx = 0;
 504                         else if(tmp > 40) // 40 means 20 dBm.
 505                                 TxPwrIdx = 40;
 506                         else
 507                                 TxPwrIdx = (s8)tmp;
 508                 }
 509                 else if(WirelessMode == WIRELESS_MODE_B)
 510                 {
 511                         bUseDefault = false;
 512                         tmp = (4 * PowerInDbm) - 52;
 513
 514                         if(tmp < 0)
 515                                 TxPwrIdx = 0;
 516                         else if(tmp > 28) // 28 means 20 dBm.
 517                                 TxPwrIdx = 28;
 518                         else
 519                                 TxPwrIdx = (s8)tmp;
 520                 }
 521         }
 522
 523         //
 524         // TRUE if we want to use a default implementation.
 525         // We shall set it to FALSE when we have exact translation formular
 526         // for target IC. 070622, by rcnjko.
 527         //
 528         if(bUseDefault)
 529         {
 530                 if(PowerInDbm < 0)
 531                         TxPwrIdx = 0;
 532                 else if(PowerInDbm > 35)
 533                         TxPwrIdx = 35;
 534                 else
 535                         TxPwrIdx = (u8)PowerInDbm;
 536         }
 537
 538         return TxPwrIdx;
 539 }
 540
 541 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 542 {
 543         struct r8180_priv *priv = ieee80211_priv(dev);
 544
 545 //      int GainIdx;
 546 //      int GainSetting;
 547         //int i;
 548         //u8 power;
 549         //u8 *cck_power_table;
 550         u8 max_cck_power_level;
 551         //u8 min_cck_power_level;
 552         u8 max_ofdm_power_level;
 553         u8 min_ofdm_power_level;
 554 //      u8 cck_power_level = 0xff & priv->chtxpwr[ch];//-by amy 080312
 555 //      u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];//-by amy 080312
 556         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);//+by amy 080312
 557         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);//+by amy 080312
 558
 559         if(IS_DOT11D_ENABLE(priv->ieee80211) &&
 560                 IS_DOT11D_STATE_DONE(priv->ieee80211) )
 561         {
 562                 //PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(priv->ieee80211);
 563                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 564                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
 565                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
 566
 567                 //printk("Max Tx Power dBm (%d) => CCK Tx power index : %d, OFDM Tx power index: %d\n", MaxTxPwrInDbm, CckMaxPwrIdx, OfdmMaxPwrIdx);
 568
 569                 //printk("EEPROM channel(%d) => CCK Tx power index: %d, OFDM Tx power index: %d\n",
 570                 //      ch, cck_power_level, ofdm_power_level);
 571
 572                 if(cck_power_level > CckMaxPwrIdx)
 573                         cck_power_level = CckMaxPwrIdx;
 574                 if(ofdm_power_level > OfdmMaxPwrIdx)
 575                         ofdm_power_level = OfdmMaxPwrIdx;
 576         }
 577
 578         //priv->CurrentCckTxPwrIdx = cck_power_level;
 579         //priv->CurrentOfdmTxPwrIdx = ofdm_power_level;
 580
 581         max_cck_power_level = 15;
 582         max_ofdm_power_level = 25; //  12 -> 25
 583         min_ofdm_power_level = 10;
 584
 585
 586         if(cck_power_level > 35)
 587         {
 588                 cck_power_level = 35;
 589         }
 590         //
 591         // Set up CCK TXAGC. suggested by SD3 SY.
 592         //
 593        write_nic_byte(dev, CCK_TXAGC, (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]) );
 594        //printk("CCK TX power is %x\n", (ZEBRA2_CCK_OFDM_GAIN_SETTING[cck_power_level]));
 595        force_pci_posting(dev);
 596         mdelay(1);
 597         /* OFDM power setting */
 598 //  Old:
 599 //      if(ofdm_power_level > max_ofdm_power_level)
 600 //              ofdm_power_level = 35;
 601 //      ofdm_power_level += min_ofdm_power_level;
 602 //  Latest:
 603 /*      if(ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
 604                 ofdm_power_level = max_ofdm_power_level;
 605         else
 606                 ofdm_power_level += min_ofdm_power_level;
 607
 608         ofdm_power_level += priv->ofdm_txpwr_base;
 609 */
 610         if(ofdm_power_level > 35)
 611                 ofdm_power_level = 35;
 612
 613 //      rtl8185_set_anaparam2(dev,RTL8225_ANAPARAM2_ON);
 614
 615         //rtl8185_set_anaparam2(dev, ANAPARM2_ASIC_ON);
 616
 617         if (priv->up == 0) {
 618                 //must add these for rtl8185B down, xiong-2006-11-21
 619                 write_phy_ofdm(dev,2,0x42);
 620                 write_phy_ofdm(dev,5,0);
 621                 write_phy_ofdm(dev,6,0x40);
 622                 write_phy_ofdm(dev,7,0);
 623                 write_phy_ofdm(dev,8,0x40);
 624         }
 625
 626         //write_nic_byte(dev, TX_GAIN_OFDM, ofdm_power_level);
 627         //2005.11.17,
 628         write_nic_byte(dev, OFDM_TXAGC, ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
 629         if(ofdm_power_level<=11)
 630         {
 631 //            write_nic_dword(dev,PHY_ADR,0x00005c87);
 632 //            write_nic_dword(dev,PHY_ADR,0x00005c89);
 633                 write_phy_ofdm(dev,0x07,0x5c);
 634                 write_phy_ofdm(dev,0x09,0x5c);
 635         }
 636         if(ofdm_power_level<=17)
 637         {
 638 //             write_nic_dword(dev,PHY_ADR,0x00005487);
 639 //             write_nic_dword(dev,PHY_ADR,0x00005489);
 640                 write_phy_ofdm(dev,0x07,0x54);
 641                 write_phy_ofdm(dev,0x09,0x54);
 642         }
 643         else
 644         {
 645 //             write_nic_dword(dev,PHY_ADR,0x00005087);
 646 //             write_nic_dword(dev,PHY_ADR,0x00005089);
 647                 write_phy_ofdm(dev,0x07,0x50);
 648                 write_phy_ofdm(dev,0x09,0x50);
 649         }
 650         force_pci_posting(dev);
 651         mdelay(1);
 652
 653 }
 654
 655 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 656 {
 657 /*
 658         short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
 659                 ieee80211_is_54g(priv->ieee80211->current_network)) ||
 660                 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
 661 */
 662         rtl8225z2_SetTXPowerLevel(dev, ch);
 663
 664         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 665
 666         //YJ,add,080828, if set channel failed, write again
 667         if((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 668         {
 669                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 670         }
 671
 672         mdelay(1);
 673
 674         force_pci_posting(dev);
 675         mdelay(10);
 676 }
 677
 678 static void rtl8225_host_pci_init(struct net_device *dev)
 679 {
 680         write_nic_word(dev, RFPinsOutput, 0x480);
 681
 682         rtl8185_rf_pins_enable(dev);
 683
 684         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
 685
 686         write_nic_byte(dev, GP_ENABLE, 0);
 687
 688         force_pci_posting(dev);
 689         mdelay(200);
 690
 691         /* bit 6 is for RF on/off detection */
 692         write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
 693 }
 694
 695 static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
 696 {
 697         struct r8180_priv *priv = ieee80211_priv(dev);
 698         short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
 699                 ieee80211_is_54g(priv->ieee80211->current_network)) ||
 700                 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
 701
 702         rtl8225_SetTXPowerLevel(dev, ch);
 703
 704         write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
 705
 706         force_pci_posting(dev);
 707         mdelay(10);
 708
 709         if (gset) {
 710                 write_nic_byte(dev, SIFS, 0x22);
 711                 write_nic_byte(dev, DIFS, 0x14);
 712         } else {
 713                 write_nic_byte(dev, SIFS, 0x44);
 714                 write_nic_byte(dev, DIFS, 0x24);
 715         }
 716
 717         if (priv->ieee80211->state == IEEE80211_LINKED &&
 718             ieee80211_is_shortslot(priv->ieee80211->current_network))
 719                 write_nic_byte(dev, SLOT, 0x9);
 720         else
 721                 write_nic_byte(dev, SLOT, 0x14);
 722
 723         if (gset) {
 724                 write_nic_byte(dev, EIFS, 81);
 725                 write_nic_byte(dev, CW_VAL, 0x73);
 726         } else {
 727                 write_nic_byte(dev, EIFS, 81);
 728                 write_nic_byte(dev, CW_VAL, 0xa5);
 729         }
 730 }
 731
 732 void rtl8225z2_rf_init(struct net_device *dev)
 733 {
 734         struct r8180_priv *priv = ieee80211_priv(dev);
 735         int i;
 736         short channel = 1;
 737         u16     brsr;
 738         u32     data,addr;
 739
 740         priv->chan = channel;
 741
 742 //      rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
 743
 744         if (priv->card_type != USB)
 745                 rtl8225_host_pci_init(dev);
 746
 747         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 748
 749         brsr = read_nic_word(dev, BRSR);
 750
 751         write_nic_word(dev, BRSR, 0xffff);
 752
 753
 754         write_nic_dword(dev, RF_PARA, 0x100044);
 755
 756         #if 1  //0->1
 757         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 758         write_nic_byte(dev, CONFIG3, 0x44);
 759         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 760         #endif
 761
 762
 763         rtl8185_rf_pins_enable(dev);
 764
 765 //              mdelay(1000);
 766
 767         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 768
 769
 770         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 771
 772         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 773
 774         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 775
 776
 777         write_rtl8225(dev, 0x4, 0x8c3);mdelay(1);
 778
 779
 780
 781         write_rtl8225(dev, 0x5, 0xc72);mdelay(1);
 782 //      }
 783
 784         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 785
 786         write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel]));  mdelay(1);
 787
 788         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 789
 790         write_rtl8225(dev, 0x9, 0x335);  mdelay(1);
 791
 792         write_rtl8225(dev, 0xa, 0x9d4);  mdelay(1);
 793
 794         write_rtl8225(dev, 0xb, 0x7bb);  mdelay(1);
 795
 796         write_rtl8225(dev, 0xc, 0x850);  mdelay(1);
 797
 798
 799         write_rtl8225(dev, 0xd, 0xcdf);   mdelay(1);
 800
 801         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 802
 803         write_rtl8225(dev, 0xf, 0x114);
 804
 805
 806         mdelay(100);
 807
 808
 809         //if(priv->card_type != USB) /* maybe not needed even for 8185 */
 810 //      write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
 811
 812         write_rtl8225(dev, 0x0, 0x1b7);
 813
 814         for(i=0;i<95;i++){
 815                 write_rtl8225(dev, 0x1, (u8)(i+1));
 816
 817                 /* version B & C & D*/
 818
 819                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 820         }
 821         write_rtl8225(dev, 0x3, 0x80);
 822         write_rtl8225(dev, 0x5, 0x4);
 823
 824         write_rtl8225(dev, 0x0, 0xb7);
 825
 826         write_rtl8225(dev, 0x2, 0xc4d);
 827
 828         if(priv->card_type == USB){
 829         //      force_pci_posting(dev);
 830                 mdelay(200);
 831
 832                 write_rtl8225(dev, 0x2, 0x44d);
 833
 834         //      force_pci_posting(dev);
 835                 mdelay(100);
 836
 837         }//End of if(priv->card_type == USB)
 838         /* FIXME!! rtl8187 we have to check if calibrarion
 839          * is successful and eventually cal. again (repeat
 840          * the two write on reg 2)
 841         */
 842         // Check for calibration status, 2005.11.17,
 843         data = read_rtl8225(dev, 6);
 844         if (!(data&0x00000080))
 845         {
 846                 write_rtl8225(dev, 0x02, 0x0c4d);
 847                 force_pci_posting(dev); mdelay(200);
 848                 write_rtl8225(dev, 0x02, 0x044d);
 849                 force_pci_posting(dev); mdelay(100);
 850                 data = read_rtl8225(dev, 6);
 851                 if (!(data&0x00000080))
 852                         {
 853                                 DMESGW("RF Calibration Failed!!!!\n");
 854                         }
 855         }
 856         //force_pci_posting(dev);
 857
 858         mdelay(200); //200 for 8187
 859
 860
 861 //      //if(priv->card_type != USB){
 862 //              write_rtl8225(dev, 0x2, 0x44d);
 863 //              write_rtl8225(dev, 0x7, rtl8225_chan[channel]);
 864 //              write_rtl8225(dev, 0x2, 0x47d);
 865 //
 866 //              force_pci_posting(dev);
 867 //              mdelay(100);
 868 //
 869 //              write_rtl8225(dev, 0x2, 0x44d);
 870 //      //}
 871
 872         write_rtl8225(dev, 0x0, 0x2bf);
 873
 874         if(priv->card_type != USB)
 875                 rtl8185_rf_pins_enable(dev);
 876         //set up ZEBRA AGC table, 2005.11.17,
 877         for(i=0;i<128;i++){
 878                 data = rtl8225_agc[i];
 879
 880                 addr = i + 0x80; //enable writing AGC table
 881                 write_phy_ofdm(dev, 0xb, data);
 882
 883                 mdelay(1);
 884                 write_phy_ofdm(dev, 0xa, addr);
 885
 886                 mdelay(1);
 887         }
 888
 889         force_pci_posting(dev);
 890         mdelay(1);
 891
 892         write_phy_ofdm(dev, 0x0, 0x1); mdelay(1);
 893         write_phy_ofdm(dev, 0x1, 0x2); mdelay(1);
 894         write_phy_ofdm(dev, 0x2, ((priv->card_type == USB)? 0x42 : 0x62)); mdelay(1);
 895         write_phy_ofdm(dev, 0x3, 0x0); mdelay(1);
 896         write_phy_ofdm(dev, 0x4, 0x0); mdelay(1);
 897         write_phy_ofdm(dev, 0x5, 0x0); mdelay(1);
 898         write_phy_ofdm(dev, 0x6, 0x40); mdelay(1);
 899         write_phy_ofdm(dev, 0x7, 0x0); mdelay(1);
 900         write_phy_ofdm(dev, 0x8, 0x40); mdelay(1);
 901         write_phy_ofdm(dev, 0x9, 0xfe); mdelay(1);
 902
 903         write_phy_ofdm(dev, 0xa, 0x8); mdelay(1);
 904
 905         //write_phy_ofdm(dev, 0x18, 0xef);
 906         //      }
 907         //}
 908         write_phy_ofdm(dev, 0xb, 0x80); mdelay(1);
 909
 910         write_phy_ofdm(dev, 0xc, 0x1);mdelay(1);
 911
 912
 913         //if(priv->card_type != USB)
 914         write_phy_ofdm(dev, 0xd, 0x43);
 915
 916         write_phy_ofdm(dev, 0xe, 0xd3);mdelay(1);
 917
 918
 919         write_phy_ofdm(dev, 0xf, 0x38);mdelay(1);
 920 /*ver D & 8187*/
 921 //      }
 922
 923 //      if(priv->card_8185 == 1 && priv->card_8185_Bversion)
 924 //              write_phy_ofdm(dev, 0x10, 0x04);/*ver B*/
 925 //      else
 926         write_phy_ofdm(dev, 0x10, 0x84);mdelay(1);
 927 /*ver C & D & 8187*/
 928
 929         write_phy_ofdm(dev, 0x11, 0x07);mdelay(1);
 930 /*agc resp time 700*/
 931
 932
 933 //      if(priv->card_8185 == 2){
 934         /* Ver D & 8187*/
 935         write_phy_ofdm(dev, 0x12, 0x20);mdelay(1);
 936
 937         write_phy_ofdm(dev, 0x13, 0x20);mdelay(1);
 938
 939         write_phy_ofdm(dev, 0x14, 0x0); mdelay(1);
 940         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
 941         write_phy_ofdm(dev, 0x16, 0x0); mdelay(1);
 942         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
 943
 944 //      if (priv->card_type == USB)
 945 //              write_phy_ofdm(dev, 0x18, 0xef);
 946
 947         write_phy_ofdm(dev, 0x18, 0xef);mdelay(1);
 948
 949
 950         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
 951         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
 952         write_phy_ofdm(dev, 0x1b, 0x15);mdelay(1);
 953
 954         write_phy_ofdm(dev, 0x1c, 0x4);mdelay(1);
 955
 956         write_phy_ofdm(dev, 0x1d, 0xc5);mdelay(1); //2005.11.17,
 957
 958         write_phy_ofdm(dev, 0x1e, 0x95);mdelay(1);
 959
 960         write_phy_ofdm(dev, 0x1f, 0x75);        mdelay(1);
 961
 962 //      }
 963
 964         write_phy_ofdm(dev, 0x20, 0x1f);mdelay(1);
 965
 966         write_phy_ofdm(dev, 0x21, 0x17);mdelay(1);
 967
 968         write_phy_ofdm(dev, 0x22, 0x16);mdelay(1);
 969
 970 //      if(priv->card_type != USB)
 971         write_phy_ofdm(dev, 0x23, 0x80);mdelay(1); //FIXME maybe not needed // <>
 972
 973         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
 974         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
 975         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
 976
 977         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
 978
 979
 980         // <> Set init. gain to m74dBm.
 981
 982         rtl8225z2_set_gain(dev,4);
 983
 984         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
 985         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
 986         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
 987         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
 988         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
 989
 990         write_phy_cck(dev, 0x7, 0x78);mdelay(1);
 991  /* Ver C & D & 8187*/
 992
 993         write_phy_cck(dev, 0x8, 0x2e);mdelay(1);
 994
 995         write_phy_cck(dev, 0x10, ((priv->card_type == USB) ? 0x9b: 0x93)); mdelay(1);
 996         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
 997         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
 998         write_phy_cck(dev, 0x13, 0xd0); /* Ver C & D & 8187*/
 999
1000         write_phy_cck(dev, 0x19, 0x0);
1001         write_phy_cck(dev, 0x1a, 0xa0);
1002         write_phy_cck(dev, 0x1b, 0x8);
1003         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
1004
1005         write_phy_cck(dev, 0x41, 0x8d);mdelay(1);
1006
1007
1008         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
1009         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
1010
1011
1012         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
1013         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
1014         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
1015         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
1016         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
1017         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
1018         write_phy_cck(dev, 0x4a, 0x9); mdelay(1);
1019         write_phy_cck(dev, 0x4b, 0x4); mdelay(1);
1020         write_phy_cck(dev, 0x4c, 0x5);mdelay(1);
1021
1022
1023         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
1024
1025
1026
1027 // <>
1028 //      // TESTR 0xb 8187
1029 //      write_phy_cck(dev, 0x10, 0x93);// & 0xfb);
1030 //
1031 //      //if(priv->card_type != USB){
1032 //              write_phy_ofdm(dev, 0x2, 0x62);
1033 //              write_phy_ofdm(dev, 0x6, 0x0);
1034 //              write_phy_ofdm(dev, 0x8, 0x0);
1035 //      //}
1036
1037         rtl8225z2_SetTXPowerLevel(dev, channel);
1038         write_phy_cck(dev, 0x11, 0x9b); mdelay(1); /* Rx ant A, 0xdb for B */
1039         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1); /* Rx ant A, 0x10 for B */
1040
1041         rtl8185_tx_antenna(dev, 0x3); /* TX ant A, 0x0 for B */
1042
1043         /* switch to high-speed 3-wire
1044          * last digit. 2 for both cck and ofdm
1045          */
1046         if(priv->card_type == USB)
1047                 write_nic_dword(dev, 0x94, 0x3dc00002);
1048         else{
1049                 write_nic_dword(dev, 0x94, 0x15c00002);
1050                 rtl8185_rf_pins_enable(dev);
1051         }
1052
1053 //       rtl8225_set_mode(dev, 1); /* FIXME start in B mode */ // <>
1054 //
1055 //      /* make sure is waken up! */
1056 //      write_rtl8225(dev,0x4, 0x9ff);
1057 //      rtl8180_set_anaparam(dev, RTL8225_ANAPARAM_ON);
1058 //      rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
1059
1060         rtl8225_rf_set_chan(dev, priv->chan);
1061
1062         //write_nic_word(dev,BRSR,brsr);
1063
1064         //rtl8225z2_rf_set_mode(dev);
1065 }
1066
1067 void rtl8225z2_rf_set_mode(struct net_device *dev)
1068 {
1069         struct r8180_priv *priv = ieee80211_priv(dev);
1070
1071         if(priv->ieee80211->mode == IEEE_A)
1072         {
1073                 write_rtl8225(dev, 0x5, 0x1865);
1074                 write_nic_dword(dev, RF_PARA, 0x10084);
1075                 write_nic_dword(dev, RF_TIMING, 0xa8008);
1076                 write_phy_ofdm(dev, 0x0, 0x0);
1077                 write_phy_ofdm(dev, 0xa, 0x6);
1078                 write_phy_ofdm(dev, 0xb, 0x99);
1079                 write_phy_ofdm(dev, 0xf, 0x20);
1080                 write_phy_ofdm(dev, 0x11, 0x7);
1081
1082                 rtl8225z2_set_gain(dev,4);
1083
1084                 write_phy_ofdm(dev,0x15, 0x40);
1085                 write_phy_ofdm(dev,0x17, 0x40);
1086
1087                 write_nic_dword(dev, 0x94,0x10000000);
1088         }else{
1089
1090                 write_rtl8225(dev, 0x5, 0x1864);
1091                 write_nic_dword(dev, RF_PARA, 0x10044);
1092                 write_nic_dword(dev, RF_TIMING, 0xa8008);
1093                 write_phy_ofdm(dev, 0x0, 0x1);
1094                 write_phy_ofdm(dev, 0xa, 0x6);
1095                 write_phy_ofdm(dev, 0xb, 0x99);
1096                 write_phy_ofdm(dev, 0xf, 0x20);
1097                 write_phy_ofdm(dev, 0x11, 0x7);
1098
1099                 rtl8225z2_set_gain(dev,4);
1100
1101                 write_phy_ofdm(dev,0x15, 0x40);
1102                 write_phy_ofdm(dev,0x17, 0x40);
1103
1104                 write_nic_dword(dev, 0x94,0x04000002);
1105         }
1106 }
1107
1108 //lzm mod 080826
1109 //#define MAX_DOZE_WAITING_TIMES_85B 64
1110 //#define MAX_POLLING_24F_TIMES_87SE    5
1111 #define MAX_DOZE_WAITING_TIMES_85B              20
1112 #define MAX_POLLING_24F_TIMES_87SE                      10
1113 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
1114
1115 bool
1116 SetZebraRFPowerState8185(
1117         struct net_device *dev,
1118         RT_RF_POWER_STATE       eRFPowerState
1119         )
1120 {
1121         struct r8180_priv *priv = ieee80211_priv(dev);
1122         u8                      btCR9346, btConfig3;
1123         bool bActionAllowed= true, bTurnOffBB = true;//lzm mod 080826
1124         //u32                   DWordContent;
1125         u8                      u1bTmp;
1126         int                     i;
1127         //u16                   u2bTFPC = 0;
1128         bool            bResult = true;
1129         u8                      QueueID;
1130
1131         if(priv->SetRFPowerStateInProgress == true)
1132                 return false;
1133
1134         priv->SetRFPowerStateInProgress = true;
1135
1136         // enable EEM0 and EEM1 in 9346CR
1137         btCR9346 = read_nic_byte(dev, CR9346);
1138         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
1139         // enable PARM_En in Config3
1140         btConfig3 = read_nic_byte(dev, CONFIG3);
1141         write_nic_byte(dev, CONFIG3, (btConfig3|CONFIG3_PARM_En) );
1142
1143         switch( priv->rf_chip )
1144         {
1145         case RF_ZEBRA2:
1146                 switch( eRFPowerState )
1147                 {
1148                 case eRfOn:
1149                         RF_WriteReg(dev,0x4,0x9FF);
1150
1151                         write_nic_dword(dev, ANAPARAM, ANAPARM_ON);
1152                         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON);
1153
1154                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
1155
1156                         //Follow 87B, Isaiah 2007-04-27
1157                         u1bTmp = read_nic_byte(dev, 0x24E);
1158                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );// 070124 SD1 Alex: turn on CCK and OFDM.
1159                         break;
1160
1161                 case eRfSleep:
1162                         break;
1163
1164                 case eRfOff:
1165                         break;
1166
1167                 default:
1168                         bResult = false;
1169                         break;
1170                 }
1171                 break;
1172
1173         case RF_ZEBRA4:
1174                 switch( eRFPowerState )
1175                 {
1176                 case eRfOn:
1177                         //printk("===================================power on@jiffies:%d\n",jiffies);
1178                         write_nic_word(dev, 0x37C, 0x00EC);
1179
1180                         //turn on AFE
1181                         write_nic_byte(dev, 0x54, 0x00);
1182                         write_nic_byte(dev, 0x62, 0x00);
1183
1184                         //lzm mod 080826
1185                         //turn on RF
1186                         //RF_WriteReg(dev, 0x0, 0x009f); //mdelay(1);
1187                         //RF_WriteReg(dev, 0x4, 0x0972); //mdelay(1);
1188                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1189                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1190                         //turn on RF again, suggested by SD3 stevenl.
1191                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
1192                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
1193
1194                         //turn on BB
1195 //                      write_nic_dword(dev, PhyAddr, 0x4090); //ofdm 10=00
1196 //                      write_nic_dword(dev, PhyAddr, 0x4092); //ofdm 12=00
1197                         write_phy_ofdm(dev,0x10,0x40);
1198                         write_phy_ofdm(dev,0x12,0x40);
1199                         //Avoid power down at init time.
1200                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
1201
1202                         u1bTmp = read_nic_byte(dev, 0x24E);
1203                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5|BIT6))) );
1204
1205                         break;
1206
1207                 case eRfSleep:
1208                         // Make sure BusyQueue is empty befor turn off RFE pwoer.
1209                         //printk("===================================power sleep@jiffies:%d\n",jiffies);
1210
1211                         for(QueueID = 0, i = 0; QueueID < 6; )
1212                         {
1213                                 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1214                                 {
1215                                         QueueID++;
1216                                         continue;
1217                                 }
1218                                 else//lzm mod 080826
1219                                 {
1220                                         priv->TxPollingTimes ++;
1221                                         if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1222                                                 {
1223                                                         //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B():eRfSleep:  %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", LPS_MAX_SLEEP_WAITING_TIMES_87SE, QueueID));
1224                                                         bActionAllowed=false;
1225                                                         break;
1226                                                 }
1227                                                 else
1228                                                 {
1229                                                         udelay(10);  // Windows may delay 3~16ms actually.
1230                                                         //RT_TRACE(COMP_POWER, DBG_LOUD, ("eRfSleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (pMgntInfo->TxPollingTimes), QueueID));
1231                                                 }
1232                                 }
1233
1234                                 //lzm del 080826
1235                                 //if(i >= MAX_DOZE_WAITING_TIMES_85B)
1236                                 //{
1237                                         //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1238                                         //break;
1239                                 //}
1240                         }
1241
1242                         if(bActionAllowed)//lzm add 080826
1243                         {
1244                                 //turn off BB RXIQ matrix to cut off rx signal
1245 //                              write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1246 //                              write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1247                                 write_phy_ofdm(dev,0x10,0x00);
1248                                 write_phy_ofdm(dev,0x12,0x00);
1249                                 //turn off RF
1250                                 RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1251                                 RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1252                                 //turn off AFE except PLL
1253                                 write_nic_byte(dev, 0x62, 0xff);
1254                                 write_nic_byte(dev, 0x54, 0xec);
1255 //                              mdelay(10);
1256
1257 #if 1
1258                                 mdelay(1);
1259                                 {
1260                                         int i = 0;
1261                                         while (true)
1262                                         {
1263                                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
1264                                                 if ((tmp24F == 0x01) || (tmp24F == 0x09))
1265                                                 {
1266                                                         bTurnOffBB = true;
1267                                                         break;
1268                                                 }
1269                                                 else//lzm mod 080826
1270                                                 {
1271                                                         udelay(10);
1272                                                         i++;
1273                                                         priv->TxPollingTimes++;
1274
1275                                                         if(priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE)
1276                                                         {
1277                                                                 //RT_TRACE(COMP_POWER, DBG_WARNING, ("\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times Rx Mac0x24F=0x%x !!!\n\n\n", i, u1bTmp24F));
1278                                                                 bTurnOffBB=false;
1279                                                                 break;
1280                                                         }
1281                                                         else
1282                                                         {
1283                                                                 udelay(10);// Windows may delay 3~16ms actually.
1284                                                                 //RT_TRACE(COMP_POWER, DBG_LOUD,("(%d)eRfSleep- u1bTmp24F= 0x%X\n", i, u1bTmp24F));
1285
1286                                                         }
1287                                                 }
1288
1289                                                 //lzm del 080826
1290                                                 //if (i > MAX_POLLING_24F_TIMES_87SE)
1291                                                 //      break;
1292                                         }
1293                                 }
1294 #endif
1295                                 if (bTurnOffBB)//lzm mod 080826
1296                                 {
1297                                 //turn off BB
1298                                 u1bTmp = read_nic_byte(dev, 0x24E);
1299                                 write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1300
1301                                 //turn off AFE PLL
1302                                 //write_nic_byte(dev, 0x54, 0xec);
1303                                 //write_nic_word(dev, 0x37C, 0x00ec);
1304                                 write_nic_byte(dev, 0x54, 0xFC);  //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1305                                 write_nic_word(dev, 0x37C, 0x00FC);//[ECS] FC-> EC->FC, asked by SD3 Stevenl
1306                                 }
1307                         }
1308                         break;
1309
1310                 case eRfOff:
1311                         // Make sure BusyQueue is empty befor turn off RFE pwoer.
1312                         //printk("===================================power off@jiffies:%d\n",jiffies);
1313                         for(QueueID = 0, i = 0; QueueID < 6; )
1314                         {
1315                                 if(get_curr_tx_free_desc(dev,QueueID) == priv->txringcount)
1316                                 {
1317                                         QueueID++;
1318                                         continue;
1319                                 }
1320                                 else
1321                                 {
1322                                         udelay(10);
1323                                         i++;
1324                                 }
1325
1326                                 if(i >= MAX_DOZE_WAITING_TIMES_85B)
1327                                 {
1328                                         //printk("\n\n\n SetZebraRFPowerState8185B(): %d times BusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_85B, QueueID);
1329                                         break;
1330                                 }
1331                         }
1332
1333                         //turn off BB RXIQ matrix to cut off rx signal
1334 //                      write_nic_dword(dev, PhyAddr, 0x0090); //ofdm 10=00
1335 //                      write_nic_dword(dev, PhyAddr, 0x0092); //ofdm 12=00
1336                         write_phy_ofdm(dev,0x10,0x00);
1337                         write_phy_ofdm(dev,0x12,0x00);
1338                         //turn off RF
1339                         RF_WriteReg(dev, 0x4, 0x0000); //mdelay(1);
1340                         RF_WriteReg(dev, 0x0, 0x0000); //mdelay(1);
1341                         //turn off AFE except PLL
1342                         write_nic_byte(dev, 0x62, 0xff);
1343                         write_nic_byte(dev, 0x54, 0xec);
1344 //                      mdelay(10);
1345 #if 1
1346                         mdelay(1);
1347                         {
1348                                 int i = 0;
1349                                 while (true)
1350                                 {
1351                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
1352                                         if ((tmp24F == 0x01) || (tmp24F == 0x09))
1353                                         {
1354                                                 bTurnOffBB = true;
1355                                                 break;
1356                                         }
1357                                         else
1358                                         {
1359                                                 bTurnOffBB = false;
1360                                                 udelay(10);
1361                                                 i++;
1362                                         }
1363                                         if (i > MAX_POLLING_24F_TIMES_87SE)
1364                                                 break;
1365                                 }
1366                         }
1367 #endif
1368                         if (bTurnOffBB)//lzm mod 080826
1369                         {
1370
1371                         //turn off BB
1372                         u1bTmp = read_nic_byte(dev, 0x24E);
1373                         write_nic_byte(dev, 0x24E, (u1bTmp|BIT5|BIT6));
1374                         //turn off AFE PLL (80M)
1375                         //write_nic_byte(dev, 0x54, 0xec);
1376                         //write_nic_word(dev, 0x37C, 0x00ec);
1377                         write_nic_byte(dev, 0x54, 0xFC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1378                         write_nic_word(dev, 0x37C, 0x00FC); //[ECS] FC-> EC->FC, asked by SD3 Stevenl
1379                         }
1380
1381                         break;
1382
1383                 default:
1384                         bResult = false;
1385                         printk("SetZebraRFPowerState8185(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1386                         break;
1387                 }
1388                 break;
1389         }
1390
1391         // disable PARM_En in Config3
1392         btConfig3 &= ~(CONFIG3_PARM_En);
1393         write_nic_byte(dev, CONFIG3, btConfig3);
1394         // disable EEM0 and EEM1 in 9346CR
1395         btCR9346 &= ~(0xC0);
1396         write_nic_byte(dev, CR9346, btCR9346);
1397
1398         if(bResult && bActionAllowed)//lzm mod 080826
1399         {
1400                 // Update current RF state variable.
1401                 priv->eRFPowerState = eRFPowerState;
1402         }
1403
1404         priv->SetRFPowerStateInProgress = false;
1405
1406         return (bResult && bActionAllowed) ;
1407 }
1408 void rtl8225z4_rf_sleep(struct net_device *dev)
1409 {
1410         //
1411         // Turn off RF power.
1412         //
1413         //printk("=========>%s()\n", __func__);
1414         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1415         //mdelay(2);    //FIXME
1416 }
1417 void rtl8225z4_rf_wakeup(struct net_device *dev)
1418 {
1419         //
1420         // Turn on RF power.
1421         //
1422         //printk("=========>%s()\n", __func__);
1423         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1424 }
1425