drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When            Who                             What
  12         ----------      ---------------         -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28
  29 #include "ieee80211/dot11d.h"
  30
  31
  32 /* #define CONFIG_RTL8180_IO_MAP */
  33
  34 #define TC_3W_POLL_MAX_TRY_CNT 5
  35 static u8 MAC_REG_TABLE[][2] =  {
  36                         /*PAGA 0:       */
  37                                                 /* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()   */
  38                                                 /* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().                                   */
  39                                                 /* 0x1F0~0x1F8  set in MacConfig_85BASIC()                                                                                              */
  40                                                 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  41                                                 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  42                                                 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  43                                                 {0x94, 0x0F}, {0x95, 0x32},
  44                                                 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  45                                                 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  46                                                 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  47                                                 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  48                                                 {0xff, 0x00},
  49
  50                                                 /*PAGE 1:       */
  51                                                 /* For Flextronics system Logo PCIHCT failure:  */
  52                                 /* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1     */
  53                                                 {0x5e, 0x01},
  54                                                 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  55                                                 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  56                                                 {0x82, 0xFF}, {0x83, 0x03},
  57                                                 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
  58                                                 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},/* lzm add 080826 */
  59                                                 {0xe2, 0x00},
  60
  61
  62                                                 /* PAGE 2: */
  63                                                 {0x5e, 0x02},
  64                                                 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  65                                                 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  66                                                 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  67                                                 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  68                                                 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  69                                                 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  70                                                 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  71
  72                                                 /* PAGA 0: */
  73                                                 {0x5e, 0x00}, {0x9f, 0x03}
  74                         };
  75
  76
  77 static u8  ZEBRA_AGC[]  =       {
  78                         0,
  79                         0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
  80                         0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
  81                         0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
  82                         0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  83                         0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
  84                         0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
  85                         0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
  86                         0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
  87                         };
  88
  89 static u32 ZEBRA_RF_RX_GAIN_TABLE[]     =       {
  90                         0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
  91                         0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
  92                         0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
  93                         0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
  94                         0x0183, 0x0163, 0x0143, 0x0123, 0x0103
  95         };
  96
  97 static u8 OFDM_CONFIG[] =       {
  98                         /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX                               */
  99                         /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode                                    */
 100                         /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test   */
 101
 102                         /* 0x00 */
 103                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 104                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 105                         /* 0x10 */
 106                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 107                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 108                         /* 0x20 */
 109                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 110                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 111                         /* 0x30 */
 112                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 113                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 114                 };
 115
 116 /*      ---------------------------------------------------------------
 117         *       Hardware IO
 118         *       the code is ported from Windows source code
 119         ----------------------------------------------------------------*/
 120
 121 void
 122 PlatformIOWrite1Byte(
 123         struct net_device *dev,
 124         u32             offset,
 125         u8              data
 126         )
 127 {
 128         write_nic_byte(dev, offset, data);
 129         read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko.        */
 130
 131 }
 132
 133 void
 134 PlatformIOWrite2Byte(
 135         struct net_device *dev,
 136         u32             offset,
 137         u16             data
 138         )
 139 {
 140         write_nic_word(dev, offset, data);
 141         read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 142
 143
 144 }
 145 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 146
 147 void
 148 PlatformIOWrite4Byte(
 149         struct net_device *dev,
 150         u32             offset,
 151         u32             data
 152         )
 153 {
 154 /* {by amy 080312 */
 155 if (offset == PhyAddr)  {
 156 /* For Base Band configuration. */
 157                 unsigned char   cmdByte;
 158                 unsigned long   dataBytes;
 159                 unsigned char   idx;
 160                 u8      u1bTmp;
 161
 162                 cmdByte = (u8)(data & 0x000000ff);
 163                 dataBytes = data>>8;
 164
 165                 /*
 166                         071010, rcnjko:
 167                         The critical section is only BB read/write race condition.
 168                         Assumption:
 169                         1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 170                         acquiring the spinlock in such context.
 171                         2. PlatformIOWrite4Byte() MUST NOT be recursive.
 172                 */
 173 /*              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );  */
 174
 175                 for (idx = 0; idx < 30; idx++)  {
 176                 /* Make sure command bit is clear before access it.     */
 177                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 178                         if ((u1bTmp & BIT7) == 0)
 179                                 break;
 180                         else
 181                                 mdelay(10);
 182                 }
 183
 184                 for (idx = 0; idx < 3; idx++)
 185                         PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
 186
 187                 write_nic_byte(dev, offset, cmdByte);
 188
 189 /*              NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
 190         }
 191 /* by amy 080312} */
 192         else    {
 193                 write_nic_dword(dev, offset, data);
 194                 read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 195         }
 196 }
 197
 198 u8
 199 PlatformIORead1Byte(
 200         struct net_device *dev,
 201         u32             offset
 202         )
 203 {
 204         u8      data = 0;
 205
 206         data = read_nic_byte(dev, offset);
 207
 208
 209         return data;
 210 }
 211
 212 u16
 213 PlatformIORead2Byte(
 214         struct net_device *dev,
 215         u32             offset
 216         )
 217 {
 218         u16     data = 0;
 219
 220         data = read_nic_word(dev, offset);
 221
 222
 223         return data;
 224 }
 225
 226 u32
 227 PlatformIORead4Byte(
 228         struct net_device *dev,
 229         u32             offset
 230         )
 231 {
 232         u32     data = 0;
 233
 234         data = read_nic_dword(dev, offset);
 235
 236
 237         return data;
 238 }
 239
 240 void SetOutputEnableOfRfPins(struct net_device *dev)
 241 {
 242         write_nic_word(dev, RFPinsEnable, 0x1bff);
 243 }
 244
 245 static int
 246 HwHSSIThreeWire(
 247         struct net_device *dev,
 248         u8                      *pDataBuf,
 249         u8                      nDataBufBitCnt,
 250         int                     bSI,
 251         int                     bWrite
 252         )
 253 {
 254         int     bResult = 1;
 255         u8      TryCnt;
 256         u8      u1bTmp;
 257
 258         do      {
 259                 /* Check if WE and RE are cleared. */
 260                 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)     {
 261                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 262                         if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
 263                                 break;
 264
 265                         udelay(10);
 266                 }
 267                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 268                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 269
 270                 /* RTL8187S HSSI Read/Write Function */
 271                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 272
 273                 if (bSI)
 274                         u1bTmp |=   RF_SW_CFG_SI;   /* reg08[1]=1 Serial Interface(SI)  */
 275
 276                 else
 277                         u1bTmp &= ~RF_SW_CFG_SI;  /* reg08[1]=0 Parallel Interface(PI)  */
 278
 279
 280                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 281
 282                 if (bSI)        {
 283                         /* jong: HW SI read must set reg84[3]=0. */
 284                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 285                         u1bTmp &= ~BIT3;
 286                         write_nic_byte(dev, RFPinsSelect, u1bTmp);
 287                 }
 288                 /*  Fill up data buffer for write operation. */
 289
 290                 if (bWrite)     {
 291                         if (nDataBufBitCnt == 16)       {
 292                                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 293                         }       else if (nDataBufBitCnt == 64)  {
 294                         /* RTL8187S shouldn't enter this case */
 295                                 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 296                                 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 297                         }       else    {
 298                                 int idx;
 299                                 int ByteCnt = nDataBufBitCnt / 8;
 300                                                                 /* printk("%d\n",nDataBufBitCnt); */
 301                                 if ((nDataBufBitCnt % 8) != 0)
 302                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 303                                 nDataBufBitCnt);
 304
 305                                if (nDataBufBitCnt > 64)
 306                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 307                                 nDataBufBitCnt);
 308
 309                                 for (idx = 0; idx < ByteCnt; idx++)
 310                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 311
 312                         }
 313                 }       else    {       /* read */
 314                         if (bSI)        {
 315                                 /* SI - reg274[3:0] : RF register's Address     */
 316                                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 317                         }       else    {
 318                                 /*  PI - reg274[15:12] : RF register's Address */
 319                                 write_nic_word(dev, SW_3W_DB0, (*((u16 *)pDataBuf)) << 12);
 320                         }
 321                 }
 322
 323                 /* Set up command: WE or RE. */
 324                 if (bWrite)
 325                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 326
 327                 else
 328                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 329
 330
 331                 /* Check if DONE is set. */
 332                 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)     {
 333                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 334                         if ((u1bTmp & SW_3W_CMD1_DONE) != 0)
 335                                 break;
 336
 337                         udelay(10);
 338                 }
 339
 340                 write_nic_byte(dev, SW_3W_CMD1, 0);
 341
 342                 /* Read back data for read operation.   */
 343                 if (bWrite == 0)        {
 344                         if (bSI)                {
 345                                 /* Serial Interface : reg363_362[11:0] */
 346                                 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 347                         }       else    {
 348                                 /* Parallel Interface : reg361_360[11:0] */
 349                                 *((u16 *)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 350                         }
 351
 352                         *((u16 *)pDataBuf) &= 0x0FFF;
 353                 }
 354
 355         }       while (0);
 356
 357         return bResult;
 358 }
 359
 360 void
 361 RF_WriteReg(struct net_device *dev, u8 offset, u32 data)
 362 {
 363         u32 data2Write;
 364         u8 len;
 365
 366         /* Pure HW 3-wire. */
 367         data2Write = (data << 4) | (u32)(offset & 0x0f);
 368         len = 16;
 369
 370         HwHSSIThreeWire(dev, (u8 *)(&data2Write), len, 1, 1);
 371 }
 372
 373 u32 RF_ReadReg(struct net_device *dev, u8 offset)
 374 {
 375         u32 data2Write;
 376         u8 wlen;
 377         u32 dataRead;
 378
 379         data2Write = ((u32)(offset & 0x0f));
 380         wlen = 16;
 381         HwHSSIThreeWire(dev, (u8 *)(&data2Write), wlen, 1, 0);
 382         dataRead = data2Write;
 383
 384         return dataRead;
 385 }
 386
 387
 388 /* by Owen on 04/07/14 for writing BB register successfully */
 389 void
 390 WriteBBPortUchar(
 391         struct net_device *dev,
 392         u32             Data
 393         )
 394 {
 395         /* u8   TimeoutCounter; */
 396         u8      RegisterContent;
 397         u8      UCharData;
 398
 399         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 400         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 401         /* for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--) */
 402         {
 403                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 404                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 405                 /*if(UCharData == RegisterContent)      */
 406                 /*      break;  */
 407         }
 408 }
 409
 410 u8
 411 ReadBBPortUchar(
 412         struct net_device *dev,
 413         u32             addr
 414         )
 415 {
 416         /*u8    TimeoutCounter; */
 417         u8      RegisterContent;
 418
 419         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 420         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 421
 422         return RegisterContent;
 423 }
 424 /* {by amy 080312 */
 425 /*
 426         Description:
 427         Perform Antenna settings with antenna diversity on 87SE.
 428                 Created by Roger, 2008.01.25.
 429 */
 430 bool
 431 SetAntennaConfig87SE(
 432         struct net_device *dev,
 433         u8                      DefaultAnt,             /* 0: Main, 1: Aux.                     */
 434         bool            bAntDiversity   /* 1:Enable, 0: Disable.        */
 435 )
 436 {
 437         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 438         bool   bAntennaSwitched = true;
 439
 440         /* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
 441
 442         /* Threshold for antenna diversity.     */
 443         write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
 444
 445         if (bAntDiversity)      {       /*      Enable Antenna Diversity.       */
 446                 if (DefaultAnt == 1)    {       /* aux antenna                  */
 447
 448                         /* Mac register, aux antenna    */
 449                         write_nic_byte(dev, ANTSEL, 0x00);
 450
 451                         /* Config CCK RX antenna.               */
 452                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
 453                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 454
 455                         /* Config OFDM RX antenna.      */
 456                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54   */
 457                         write_phy_ofdm(dev, 0x18, 0xb2);        /* Reg18 : b2           */
 458                 }       else    {       /*  use main antenna    */
 459                         /* Mac register, main antenna           */
 460                         write_nic_byte(dev, ANTSEL, 0x03);
 461                         /* base band                            */
 462                         /*  Config CCK RX antenna.      */
 463                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b   */
 464                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7   */
 465
 466                         /* Config OFDM RX antenna. */
 467                         write_phy_ofdm(dev, 0x0d, 0x5c);  /* Reg0d : 5c */
 468                         write_phy_ofdm(dev, 0x18, 0xb2);  /* Reg18 : b2 */
 469                 }
 470         }       else    {
 471                 /* Disable Antenna Diversity. */
 472                 if (DefaultAnt == 1)    {       /* aux Antenna */
 473                         /* Mac register, aux antenna */
 474                         write_nic_byte(dev, ANTSEL, 0x00);
 475
 476                         /* Config CCK RX antenna. */
 477                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb   */
 478                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47   */
 479
 480                         /* Config OFDM RX antenna. */
 481                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54   */
 482                         write_phy_ofdm(dev, 0x18, 0x32);        /* Reg18 : 32   */
 483                 }       else    {       /* main Antenna */
 484                         /* Mac register, main antenna */
 485                         write_nic_byte(dev, ANTSEL, 0x03);
 486
 487                         /* Config CCK RX antenna.       */
 488                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
 489                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 490
 491                         /* Config OFDM RX antenna.              */
 492                         write_phy_ofdm(dev, 0x0D, 0x5c);        /* Reg0d : 5c   */
 493                         write_phy_ofdm(dev, 0x18, 0x32);        /*Reg18 : 32    */
 494                 }
 495         }
 496         priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
 497         return  bAntennaSwitched;
 498 }
 499 /* by amy 080312 */
 500 /*
 501 ---------------------------------------------------------------
 502         *       Hardware Initialization.
 503         *       the code is ported from Windows source code
 504 ----------------------------------------------------------------*/
 505
 506 void
 507 ZEBRA_Config_85BASIC_HardCode(
 508         struct net_device *dev
 509         )
 510 {
 511
 512         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 513         u32                     i;
 514         u32     addr, data;
 515         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
 516         u8                      u1b24E;
 517         int d_cut = 0;
 518
 519
 520 /*
 521 =============================================================================
 522         87S_PCIE :: RADIOCFG.TXT
 523 =============================================================================
 524 */
 525
 526
 527         /* Page1 : reg16-reg30 */
 528         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); /* switch to page1 */
 529         u4bRF23 = RF_ReadReg(dev, 0x08);                        mdelay(1);
 530         u4bRF24 = RF_ReadReg(dev, 0x09);                        mdelay(1);
 531
 532         if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
 533                 d_cut = 1;
 534                 printk(KERN_INFO "rtl8187se: card type changed from C- to D-cut\n");
 535         }
 536
 537         /* Page0 : reg0-reg15   */
 538
 539         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1);/* 1  */
 540
 541         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
 542
 543         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);/* 2  */
 544
 545         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);/* 3  */
 546
 547         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
 548         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
 549         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
 550         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
 551         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
 552         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
 553         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
 554         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
 555         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
 556         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
 557         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
 558         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
 559
 560
 561         /*  Page1 : reg16-reg30 */
 562         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
 563
 564         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
 565
 566         RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
 567         RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
 568         RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
 569
 570
 571         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
 572 /* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
 573         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
 574         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
 575
 576         if (d_cut) {
 577                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
 578                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
 579                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); /* RX LO buffer */
 580         }       else    {
 581                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
 582                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
 583                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); /* RX LO buffer */
 584         }
 585
 586         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
 587
 588         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1); /* 6 */
 589
 590         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
 591         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
 592         for (i = 0; i <= 36; i++)       {
 593                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
 594                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
 595         }
 596
 597         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /* 203, 343     */
 598         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      /* 400          */
 599
 600         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      /* switch to reg16-reg30, and HSSI disable 137  */
 601         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 602
 603         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      /* Z4 synthesizer loop filter setting, 392              */
 604         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 605
 606         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      /* switch to reg0-reg15, and HSSI disable               */
 607         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 608
 609         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      /* CBC on, Tx Rx disable, High gain                             */
 610         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 611
 612         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      /* Z4 setted channel 1                                                  */
 613         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 614
 615         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      /* LC calibration                                                               */
 616         mdelay(200);    /* Deay 200 ms. */      /* 0xfd */
 617         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 618         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 619
 620         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      /* switch to reg16-reg30 137, and HSSI disable 137      */
 621         mdelay(10);             /* Deay 10 ms.  */      /* 0xfd */
 622
 623         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
 624         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
 625         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
 626         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
 627
 628         /* DAC calibration off 20070702 */
 629         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
 630         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
 631 /* {by amy 080312 */
 632         /* For crystal calibration, added by Roger, 2007.12.11. */
 633         if (priv->bXtalCalibration)     {       /* reg 30.      */
 634          /* enable crystal calibration.
 635                         RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
 636                         (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
 637                         (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
 638                         So we should minus 4 BITs offset.               */
 639                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);                        mdelay(1);
 640                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
 641                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
 642         }       else    {
 643                 /* using default value. Xin=6, Xout=6.  */
 644                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
 645         }
 646 /* by amy 080312 */
 647
 648         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); /* switch to reg0-reg15, and HSSI enable     */
 649         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); /* Rx BB start calibration, 00c//+edward     */
 650         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); /* temperature meter off                                     */
 651         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); /* Rx mode                                                           */
 652         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 653         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 654         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 655         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); /* Rx mode*/ /*+edward       */
 656         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); /* Rx mode*/ /*+edward       */
 657         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); /* Rx mode*/ /*+edward       */
 658
 659         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); /* Rx mode*/ /*+edward       */
 660         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); /* Rx mode*/ /*+edward       */
 661         /* power save parameters.       */
 662         u1b24E = read_nic_byte(dev, 0x24E);
 663         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
 664
 665         /*=============================================================================
 666
 667         =============================================================================
 668         CCKCONF.TXT
 669         =============================================================================
 670         */
 671         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
 672                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
 673                 CCK reg0x00[6]=1'b1: power saving for RX (default)
 674                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
 675                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
 676                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
 677         */
 678
 679         write_phy_cck(dev, 0x00, 0xc8);
 680         write_phy_cck(dev, 0x06, 0x1c);
 681         write_phy_cck(dev, 0x10, 0x78);
 682         write_phy_cck(dev, 0x2e, 0xd0);
 683         write_phy_cck(dev, 0x2f, 0x06);
 684         write_phy_cck(dev, 0x01, 0x46);
 685
 686         /* power control        */
 687         write_nic_byte(dev, CCK_TXAGC, 0x10);
 688         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
 689         write_nic_byte(dev, ANTSEL, 0x03);
 690
 691
 692
 693         /*
 694         =============================================================================
 695                 AGC.txt
 696         =============================================================================
 697         */
 698
 699         write_phy_ofdm(dev, 0x00, 0x12);
 700
 701         for (i = 0; i < 128; i++)       {
 702
 703                 data = ZEBRA_AGC[i+1];
 704                 data = data << 8;
 705                 data = data | 0x0000008F;
 706
 707                 addr = i + 0x80; /* enable writing AGC table */
 708                 addr = addr << 8;
 709                 addr = addr | 0x0000008E;
 710
 711                 WriteBBPortUchar(dev, data);
 712                 WriteBBPortUchar(dev, addr);
 713                 WriteBBPortUchar(dev, 0x0000008E);
 714         }
 715
 716         PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
 717
 718         /*
 719         =============================================================================
 720
 721         =============================================================================
 722         OFDMCONF.TXT
 723         =============================================================================
 724         */
 725
 726         for (i = 0; i < 60; i++)        {
 727                 u4bRegOffset = i;
 728                 u4bRegValue = OFDM_CONFIG[i];
 729
 730                 WriteBBPortUchar(dev,
 731                                                 (0x00000080 |
 732                                                 (u4bRegOffset & 0x7f) |
 733                                                 ((u4bRegValue & 0xff) << 8)));
 734         }
 735
 736         /*
 737         =============================================================================
 738         by amy for antenna
 739         =============================================================================
 740         */
 741 /* {by amy 080312 */
 742         /* Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.   */
 743         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
 744 /* by amy 080312} */
 745 /* by amy for antenna */
 746 }
 747
 748
 749 void
 750 UpdateInitialGain(
 751         struct net_device *dev
 752         )
 753 {
 754         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 755
 756         /* lzm add 080826 */
 757         if (priv->eRFPowerState != eRfOn)       {
 758                 /*      Don't access BB/RF under disable PLL situation.
 759                         RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
 760                         Back to the original state
 761                 */
 762                 priv->InitialGain = priv->InitialGainBackUp;
 763                 return;
 764         }
 765
 766         switch (priv->InitialGain) {
 767         case 1: /* m861dBm */
 768                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 769                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 770                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 771                 break;
 772
 773         case 2: /* m862dBm */
 774                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 775                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 776                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 777                 break;
 778
 779         case 3: /* m863dBm */
 780                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 781                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 782                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 783                 break;
 784
 785         case 4: /* m864dBm */
 786                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 787                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 788                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 789                 break;
 790
 791         case 5: /* m82dBm */
 792                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 793                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 794                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 795                 break;
 796
 797         case 6: /* m78dBm */
 798                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 799                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 800                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 801                 break;
 802
 803         case 7: /* m74dBm */
 804                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 805                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
 806                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 807                 break;
 808
 809         case 8:
 810                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
 811                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
 812                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 813                 break;
 814
 815         default:        /* MP */
 816                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 817                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 818                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 819                 break;
 820         }
 821 }
 822 /*
 823         Description:
 824                 Tx Power tracking mechanism routine on 87SE.
 825         Created by Roger, 2007.12.11.
 826 */
 827 void
 828 InitTxPwrTracking87SE(
 829         struct net_device *dev
 830 )
 831 {
 832         u32     u4bRfReg;
 833
 834         u4bRfReg = RF_ReadReg(dev, 0x02);
 835
 836         /* Enable Thermal meter indication.     */
 837         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
 838 }
 839
 840 void
 841 PhyConfig8185(
 842         struct net_device *dev
 843         )
 844 {
 845         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 846                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
 847            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
 848         /*  RF config */
 849         ZEBRA_Config_85BASIC_HardCode(dev);
 850 /* {by amy 080312 */
 851         /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. */
 852         if (priv->bDigMechanism)        {
 853                 if (priv->InitialGain == 0)
 854                         priv->InitialGain = 4;
 855         }
 856
 857         /*
 858                 Enable thermal meter indication to implement TxPower tracking on 87SE.
 859                 We initialize thermal meter here to avoid unsuccessful configuration.
 860                 Added by Roger, 2007.12.11.
 861         */
 862         if (priv->bTxPowerTrack)
 863                 InitTxPwrTracking87SE(dev);
 864
 865 /* by amy 080312} */
 866         priv->InitialGainBackUp = priv->InitialGain;
 867         UpdateInitialGain(dev);
 868
 869         return;
 870 }
 871
 872 void
 873 HwConfigureRTL8185(
 874                 struct net_device *dev
 875                 )
 876 {
 877         /* RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. */
 878         u8              bUNIVERSAL_CONTROL_RL = 0;
 879         u8              bUNIVERSAL_CONTROL_AGC = 1;
 880         u8              bUNIVERSAL_CONTROL_ANT = 1;
 881         u8              bAUTO_RATE_FALLBACK_CTL = 1;
 882         u8              val8;
 883         write_nic_word(dev, BRSR, 0x0fff);
 884         /* Retry limit */
 885         val8 = read_nic_byte(dev, CW_CONF);
 886
 887         if (bUNIVERSAL_CONTROL_RL)
 888                 val8 = val8 & 0xfd;
 889         else
 890                 val8 = val8 | 0x02;
 891
 892         write_nic_byte(dev, CW_CONF, val8);
 893
 894         /* Tx AGC */
 895         val8 = read_nic_byte(dev, TXAGC_CTL);
 896         if (bUNIVERSAL_CONTROL_AGC)     {
 897                 write_nic_byte(dev, CCK_TXAGC, 128);
 898                 write_nic_byte(dev, OFDM_TXAGC, 128);
 899                 val8 = val8 & 0xfe;
 900         }       else    {
 901                 val8 = val8 | 0x01 ;
 902         }
 903
 904
 905         write_nic_byte(dev, TXAGC_CTL, val8);
 906
 907         /* Tx Antenna including Feedback control        */
 908         val8 = read_nic_byte(dev, TXAGC_CTL);
 909
 910         if (bUNIVERSAL_CONTROL_ANT)     {
 911                 write_nic_byte(dev, ANTSEL, 0x00);
 912                 val8 = val8 & 0xfd;
 913         }       else    {
 914                 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
 915         }
 916
 917         write_nic_byte(dev, TXAGC_CTL, val8);
 918
 919         /* Auto Rate fallback control   */
 920         val8 = read_nic_byte(dev, RATE_FALLBACK);
 921         val8 &= 0x7c;
 922         if (bAUTO_RATE_FALLBACK_CTL)    {
 923                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
 924
 925                 /* <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. */
 926                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
 927         }
 928         write_nic_byte(dev, RATE_FALLBACK, val8);
 929 }
 930
 931 static void
 932 MacConfig_85BASIC_HardCode(
 933         struct net_device *dev)
 934 {
 935         /*
 936         ============================================================================
 937         MACREG.TXT
 938         ============================================================================
 939         */
 940         int                     nLinesRead = 0;
 941
 942         u32     u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
 943         int     i;
 944
 945         nLinesRead = sizeof(MAC_REG_TABLE)/2;
 946
 947         for (i = 0; i < nLinesRead; i++)        {       /* nLinesRead=101 */
 948                 u4bRegOffset = MAC_REG_TABLE[i][0];
 949                 u4bRegValue = MAC_REG_TABLE[i][1];
 950
 951                                 if (u4bRegOffset == 0x5e)
 952                                         u4bPageIndex = u4bRegValue;
 953
 954                                 else
 955                                                 u4bRegOffset |= (u4bPageIndex << 8);
 956
 957                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
 958         }
 959         /* ============================================================================ */
 960 }
 961
 962 static void
 963 MacConfig_85BASIC(
 964         struct net_device *dev)
 965 {
 966
 967         u8                      u1DA;
 968         MacConfig_85BASIC_HardCode(dev);
 969
 970         /* ============================================================================ */
 971
 972         /* Follow TID_AC_MAP of WMac. */
 973         write_nic_word(dev, TID_AC_MAP, 0xfa50);
 974
 975         /* Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. */
 976         write_nic_word(dev, IntMig, 0x0000);
 977
 978         /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
 979         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
 980         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
 981         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
 982
 983         /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.      */
 984         /* power save parameter based on "87SE power save parameters 20071127.doc", as follow.  */
 985
 986         /* Enable DA10 TX power saving */
 987         u1DA = read_nic_byte(dev, PHYPR);
 988         write_nic_byte(dev, PHYPR, (u1DA | BIT2));
 989
 990         /* POWER:       */
 991         write_nic_word(dev, 0x360, 0x1000);
 992         write_nic_word(dev, 0x362, 0x1000);
 993
 994         /* AFE.         */
 995         write_nic_word(dev, 0x370, 0x0560);
 996         write_nic_word(dev, 0x372, 0x0560);
 997         write_nic_word(dev, 0x374, 0x0DA4);
 998         write_nic_word(dev, 0x376, 0x0DA4);
 999         write_nic_word(dev, 0x378, 0x0560);
1000         write_nic_word(dev, 0x37A, 0x0560);
1001         write_nic_word(dev, 0x37C, 0x00EC);
1002         write_nic_word(dev, 0x37E, 0x00EC);     /*+edward       */
1003         write_nic_byte(dev, 0x24E, 0x01);
1004 }
1005
1006 u8
1007 GetSupportedWirelessMode8185(
1008         struct net_device *dev
1009 )
1010 {
1011         u8                      btSupportedWirelessMode = 0;
1012
1013         btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1014         return btSupportedWirelessMode;
1015 }
1016
1017 void
1018 ActUpdateChannelAccessSetting(
1019         struct net_device *dev,
1020         WIRELESS_MODE                   WirelessMode,
1021         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1022         )
1023 {
1024         struct r8180_priv *priv = ieee80211_priv(dev);
1025         struct ieee80211_device *ieee = priv->ieee80211;
1026         AC_CODING       eACI;
1027         AC_PARAM        AcParam;
1028         u8      bFollowLegacySetting = 0;
1029         u8   u1bAIFS;
1030
1031         /*
1032                 <RJ_TODO_8185B>
1033                 TODO: We still don't know how to set up these registers, just follow WMAC to
1034                 verify 8185B FPAG.
1035
1036                 <RJ_TODO_8185B>
1037                 Jong said CWmin/CWmax register are not functional in 8185B,
1038                 so we shall fill channel access realted register into AC parameter registers,
1039                 even in nQBss.
1040         */
1041         ChnlAccessSetting->SIFS_Timer = 0x22; /* Suggested by Jong, 2005.12.08. */
1042         ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko.                 */
1043         ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko.                 */
1044         ChnlAccessSetting->EIFS_Timer = 0x5B; /* Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.      */
1045         ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko.                    */
1046         ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko.                    */
1047
1048         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1049         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    /* Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. */
1050
1051         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer);
1052
1053         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1054
1055         write_nic_byte(dev, AckTimeOutReg, 0x5B); /* <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
1056
1057         { /* Legacy 802.11. */
1058                 bFollowLegacySetting = 1;
1059
1060         }
1061
1062         /* this setting is copied from rtl8187B.  xiong-2006-11-13 */
1063         if (bFollowLegacySetting)       {
1064
1065                 /*
1066                         Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1067                         2005.12.01, by rcnjko.
1068                 */
1069                 AcParam.longData = 0;
1070                 AcParam.f.AciAifsn.f.AIFSN = 2; /* Follow 802.11 DIFS.  */
1071                 AcParam.f.AciAifsn.f.ACM = 0;
1072                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; /*      Follow 802.11 CWmin.    */
1073                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; /*      Follow 802.11 CWmax.    */
1074                 AcParam.f.TXOPLimit = 0;
1075
1076                 /* lzm reserved 080826 */
1077                 /* For turbo mode setting. port from 87B by Isaiah 2008-08-01 */
1078                 if (ieee->current_network.Turbo_Enable == 1)
1079                         AcParam.f.TXOPLimit = 0x01FF;
1080                 /* For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB) */
1081                 if (ieee->iw_mode == IW_MODE_ADHOC)
1082                         AcParam.f.TXOPLimit = 0x0020;
1083
1084                 for (eACI = 0; eACI < AC_MAX; eACI++)   {
1085                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1086                         {
1087                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1088                                 AC_CODING       eACI;
1089                                 u8              u1bAIFS;
1090                                 u32             u4bAcParam;
1091
1092                                 /*  Retrive paramters to udpate. */
1093                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1094                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1095                                 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)    |
1096                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1097                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1098                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1099
1100                                 switch (eACI)   {
1101                                 case AC1_BK:
1102                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
1103                                         break;
1104
1105                                 case AC0_BE:
1106                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
1107                                         break;
1108
1109                                 case AC2_VI:
1110                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
1111                                         break;
1112
1113                                 case AC3_VO:
1114                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
1115                                         break;
1116
1117                                 default:
1118                                         DMESGW("SetHwReg8185(): invalid ACI: %d !\n", eACI);
1119                                         break;
1120                                 }
1121
1122                                 /* Cehck ACM bit.       */
1123                                 /* If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. */
1124                                 {
1125                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1126                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1127
1128                                         /*modified Joseph                               */
1129                                         /*for 8187B AsynIORead issue    */
1130                                         u8      AcmCtrl = 0;
1131                                         if (pAciAifsn->f.ACM)   {
1132                                                 /* ACM bit is 1. */
1133                                                 switch (eACI)   {
1134                                                 case AC0_BE:
1135                                                         AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  /* or 0x21 */
1136                                                         break;
1137
1138                                                 case AC2_VI:
1139                                                         AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  /* or 0x42      */
1140                                                         break;
1141
1142                                                 case AC3_VO:
1143                                                         AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  /* or 0x84 */
1144                                                         break;
1145
1146                                                 default:
1147                                                         DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI);
1148                                                         break;
1149                                                 }
1150                                         }       else    {
1151                                                 /* ACM bit is 0. */
1152                                                 switch (eACI)   {
1153                                                 case AC0_BE:
1154                                                         AcmCtrl &= ((~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN));     /* and 0xDE */
1155                                                         break;
1156
1157                                                 case AC2_VI:
1158                                                         AcmCtrl &= ((~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN));     /* and 0xBD */
1159                                                         break;
1160
1161                                                 case AC3_VO:
1162                                                         AcmCtrl &= ((~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN));     /* and 0x7B */
1163                                                         break;
1164
1165                                                 default:
1166                                                         break;
1167                                                 }
1168                                         }
1169                                         write_nic_byte(dev, ACM_CONTROL, 0);
1170                                 }
1171                         }
1172                 }
1173         }
1174 }
1175
1176 void
1177 ActSetWirelessMode8185(
1178         struct net_device *dev,
1179         u8                              btWirelessMode
1180         )
1181 {
1182         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1183         struct ieee80211_device *ieee = priv->ieee80211;
1184         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1185
1186         if ((btWirelessMode & btSupportedWirelessMode) == 0)    {
1187                 /* Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.    */
1188                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1189                         btWirelessMode, btSupportedWirelessMode);
1190                 return;
1191         }
1192
1193         /* 1. Assign wireless mode to swtich if necessary.      */
1194         if (btWirelessMode == WIRELESS_MODE_AUTO)       {
1195                 if ((btSupportedWirelessMode & WIRELESS_MODE_A))        {
1196                         btWirelessMode = WIRELESS_MODE_A;
1197                 }       else if (btSupportedWirelessMode & WIRELESS_MODE_G)     {
1198                                 btWirelessMode = WIRELESS_MODE_G;
1199
1200                 }       else if ((btSupportedWirelessMode & WIRELESS_MODE_B))   {
1201                                 btWirelessMode = WIRELESS_MODE_B;
1202                 }       else    {
1203                                 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1204                                                 btSupportedWirelessMode);
1205                                 btWirelessMode = WIRELESS_MODE_B;
1206                 }
1207         }
1208
1209         /* 2. Swtich band: RF or BB specific actions,
1210          * for example, refresh tables in omc8255, or change initial gain if necessary.
1211          * Nothing to do for Zebra to switch band.
1212          * Update current wireless mode if we swtich to specified band successfully. */
1213
1214         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1215
1216         /* 3. Change related setting.   */
1217         if( ieee->mode == WIRELESS_MODE_A )     {
1218                 DMESG("WIRELESS_MODE_A\n");
1219         }       else if( ieee->mode == WIRELESS_MODE_B )        {
1220                         DMESG("WIRELESS_MODE_B\n");
1221         }       else if( ieee->mode == WIRELESS_MODE_G )        {
1222                         DMESG("WIRELESS_MODE_G\n");
1223         }
1224         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1225 }
1226
1227 void rtl8185b_irq_enable(struct net_device *dev)
1228 {
1229         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1230
1231         priv->irq_enabled = 1;
1232         write_nic_dword(dev, IMR, priv->IntrMask);
1233 }
1234 /* by amy for power save */
1235 void
1236 DrvIFIndicateDisassociation(
1237         struct net_device *dev,
1238         u16                     reason
1239         )
1240 {
1241                 /* nothing is needed after disassociation request. */
1242         }
1243 void
1244 MgntDisconnectIBSS(
1245         struct net_device *dev
1246 )
1247 {
1248         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1249         u8                      i;
1250
1251         DrvIFIndicateDisassociation(dev, unspec_reason);
1252
1253         for (i = 0; i < 6 ; i++)
1254                 priv->ieee80211->current_network.bssid[i] = 0x55;
1255
1256
1257
1258         priv->ieee80211->state = IEEE80211_NOLINK;
1259         /*
1260                 Stop Beacon.
1261
1262                 Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1263                 Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1264                 Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1265
1266                 Disable Beacon Queue Own bit, suggested by jong */
1267         ieee80211_stop_send_beacons(priv->ieee80211);
1268
1269         priv->ieee80211->link_change(dev);
1270         notify_wx_assoc_event(priv->ieee80211);
1271 }
1272 void
1273 MlmeDisassociateRequest(
1274         struct net_device *dev,
1275         u8 *asSta,
1276         u8      asRsn
1277         )
1278 {
1279         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1280         u8 i;
1281
1282         SendDisassociation(priv->ieee80211, asSta, asRsn);
1283
1284         if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0)      {
1285                 /*ShuChen TODO: change media status.                    */
1286                 /*ShuChen TODO: What to do when disassociate.   */
1287                 DrvIFIndicateDisassociation(dev, unspec_reason);
1288
1289
1290
1291                 for (i = 0; i < 6; i++)
1292                         priv->ieee80211->current_network.bssid[i] = 0x22;
1293
1294                 ieee80211_disassociate(priv->ieee80211);
1295         }
1296
1297 }
1298
1299 void
1300 MgntDisconnectAP(
1301         struct net_device *dev,
1302         u8                      asRsn
1303 )
1304 {
1305         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1306
1307         /*
1308         Commented out by rcnjko, 2005.01.27:
1309         I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1310
1311                 2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
1312
1313                 In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
1314                 2004.10.11, by rcnjko. */
1315         MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid, asRsn);
1316
1317         priv->ieee80211->state = IEEE80211_NOLINK;
1318 }
1319 bool
1320 MgntDisconnect(
1321         struct net_device *dev,
1322         u8                      asRsn
1323 )
1324 {
1325         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1326         /*
1327                 Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1328         */
1329
1330         if (IS_DOT11D_ENABLE(priv->ieee80211))
1331                 Dot11d_Reset(priv->ieee80211);
1332         /* In adhoc mode, update beacon frame.  */
1333         if (priv->ieee80211->state == IEEE80211_LINKED) {
1334                 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1335                         MgntDisconnectIBSS(dev);
1336
1337                 if (priv->ieee80211->iw_mode == IW_MODE_INFRA)  {
1338                         /*      We clear key here instead of MgntDisconnectAP() because that
1339                                 MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
1340                                 e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
1341                                 used to handle disassociation related things to AP, e.g. send Disassoc
1342                                 frame to AP.  2005.01.27, by rcnjko.    */
1343                         MgntDisconnectAP(dev, asRsn);
1344                 }
1345                 /* Inidicate Disconnect, 2005.02.23, by rcnjko. */
1346         }
1347         return true;
1348 }
1349 /*
1350         Description:
1351                 Chang RF Power State.
1352                 Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
1353
1354         Assumption:
1355                 PASSIVE LEVEL.
1356 */
1357 bool
1358 SetRFPowerState(
1359         struct net_device *dev,
1360         RT_RF_POWER_STATE       eRFPowerState
1361         )
1362 {
1363         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1364         bool                    bResult = false;
1365
1366         if (eRFPowerState == priv->eRFPowerState)
1367                 return bResult;
1368
1369          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1370
1371         return bResult;
1372 }
1373 void
1374 HalEnableRx8185Dummy(
1375         struct net_device *dev
1376         )
1377 {
1378 }
1379 void
1380 HalDisableRx8185Dummy(
1381         struct net_device *dev
1382         )
1383 {
1384 }
1385
1386 bool
1387 MgntActSet_RF_State(
1388         struct net_device *dev,
1389         RT_RF_POWER_STATE       StateToSet,
1390         u32     ChangeSource
1391         )
1392 {
1393         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1394         bool                            bActionAllowed = false;
1395         bool                            bConnectBySSID = false;
1396         RT_RF_POWER_STATE       rtState;
1397         u16                             RFWaitCounter = 0;
1398         unsigned long flag;
1399         /*
1400                 Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1401                 Only one thread can change the RF state at one time, and others should wait to be executed.
1402         */
1403         while (true)    {
1404                 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1405                 if (priv->RFChangeInProgress)   {
1406                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1407                         /*  Set RF after the previous action is done.   */
1408                         while (priv->RFChangeInProgress)        {
1409                                 RFWaitCounter++;
1410                                 udelay(1000); /* 1 ms   */
1411
1412                                 /* Wait too long, return FALSE to avoid to be stuck here.       */
1413                                 if (RFWaitCounter > 1000)       {       /* 1sec */
1414                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1415                                         /* TODO: Reset RF state?        */
1416                                         return false;
1417                                 }
1418                         }
1419                 }       else    {
1420                         priv->RFChangeInProgress = true;
1421                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1422                         break;
1423                 }
1424         }
1425         rtState = priv->eRFPowerState;
1426
1427         switch (StateToSet)     {
1428         case eRfOn:
1429                 /*
1430                         Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
1431                         the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
1432                 */
1433                 priv->RfOffReason &= (~ChangeSource);
1434
1435                 if (!priv->RfOffReason) {
1436                         priv->RfOffReason = 0;
1437                         bActionAllowed = true;
1438
1439                         if (rtState == eRfOff && ChangeSource >= RF_CHANGE_BY_HW && !priv->bInHctTest)
1440                                 bConnectBySSID = true;
1441
1442                 }       else
1443                                 ;
1444                 break;
1445
1446         case eRfOff:
1447                  /* 070125, rcnjko: we always keep connected in AP mode.        */
1448
1449                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)       {
1450                                 /*
1451                                         060808, Annie:
1452                                         Disconnect to current BSS when radio off. Asked by QuanTa.
1453
1454                                         Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
1455                                         because we do NOT need to set ssid to dummy ones.
1456                                 */
1457                                 MgntDisconnect(dev, disas_lv_ss);
1458
1459                                 /* Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.     */
1460                         }
1461
1462                 priv->RfOffReason |= ChangeSource;
1463                 bActionAllowed = true;
1464                 break;
1465         case eRfSleep:
1466                 priv->RfOffReason |= ChangeSource;
1467                 bActionAllowed = true;
1468                 break;
1469         default:
1470                 break;
1471         }
1472
1473         if (bActionAllowed)     {
1474                                 /* Config HW to the specified mode.     */
1475                 SetRFPowerState(dev, StateToSet);
1476
1477                 /* Turn on RF.  */
1478                 if (StateToSet == eRfOn)                {
1479                         HalEnableRx8185Dummy(dev);
1480                         if (bConnectBySSID)     {
1481                                 /* by amy not supported */
1482                         }
1483                 }
1484                 /* Turn off RF. */
1485                 else if (StateToSet == eRfOff)
1486                         HalDisableRx8185Dummy(dev);
1487
1488         }
1489
1490         /* Release RF spinlock  */
1491         spin_lock_irqsave(&priv->rf_ps_lock, flag);
1492         priv->RFChangeInProgress = false;
1493         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1494         return bActionAllowed;
1495 }
1496 void
1497 InactivePowerSave(
1498         struct net_device *dev
1499         )
1500 {
1501         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1502         /*
1503                 This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
1504                 is really scheduled.
1505                 The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
1506                 previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
1507                 blocks the IPS procedure of switching RF.
1508         */
1509         priv->bSwRfProcessing = true;
1510
1511         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1512
1513         /*
1514                 To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
1515         */
1516
1517         priv->bSwRfProcessing = false;
1518 }
1519
1520 /*
1521         Description:
1522                 Enter the inactive power save mode. RF will be off
1523 */
1524 void
1525 IPSEnter(
1526         struct net_device *dev
1527         )
1528 {
1529         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1530         RT_RF_POWER_STATE rtState;
1531         if (priv->bInactivePs)  {
1532                 rtState = priv->eRFPowerState;
1533
1534                 /*
1535                         Do not enter IPS in the following conditions:
1536                         (1) RF is already OFF or Sleep
1537                         (2) bSwRfProcessing (indicates the IPS is still under going)
1538                         (3) Connectted (only disconnected can trigger IPS)
1539                         (4) IBSS (send Beacon)
1540                         (5) AP mode (send Beacon)
1541                 */
1542                 if (rtState == eRfOn && !priv->bSwRfProcessing
1543                         && (priv->ieee80211->state != IEEE80211_LINKED))        {
1544                         priv->eInactivePowerState = eRfOff;
1545                         InactivePowerSave(dev);
1546                 }
1547         }
1548 }
1549 void
1550 IPSLeave(
1551         struct net_device *dev
1552         )
1553 {
1554         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1555         RT_RF_POWER_STATE rtState;
1556         if (priv->bInactivePs)  {
1557                 rtState = priv->eRFPowerState;
1558                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)    {
1559                         priv->eInactivePowerState = eRfOn;
1560                         InactivePowerSave(dev);
1561                 }
1562         }
1563 }
1564
1565 void rtl8185b_adapter_start(struct net_device *dev)
1566 {
1567         struct r8180_priv *priv = ieee80211_priv(dev);
1568         struct ieee80211_device *ieee = priv->ieee80211;
1569
1570         u8 SupportedWirelessMode;
1571         u8                      InitWirelessMode;
1572         u8                      bInvalidWirelessMode = 0;
1573         u8 tmpu8;
1574         u8 btCR9346;
1575         u8 TmpU1b;
1576         u8 btPSR;
1577
1578         write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1579         rtl8180_reset(dev);
1580
1581         priv->dma_poll_mask = 0;
1582         priv->dma_poll_stop_mask = 0;
1583
1584         HwConfigureRTL8185(dev);
1585         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1586         write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1587         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       /* default network type to 'No  Link'   */
1588         write_nic_word(dev, BcnItv, 100);
1589         write_nic_word(dev, AtimWnd, 2);
1590         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1591         write_nic_byte(dev, WPA_CONFIG, 0);
1592         MacConfig_85BASIC(dev);
1593         /*      Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. */
1594         /*      BT_DEMO_BOARD type      */
1595         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1596
1597         /*
1598         -----------------------------------------------------------------------------
1599                 Set up PHY related.
1600         -----------------------------------------------------------------------------
1601         */
1602         /* Enable Config3.PARAM_En to revise AnaaParm.  */
1603         write_nic_byte(dev, CR9346, 0xc0);      /* enable config register write */
1604         tmpu8 = read_nic_byte(dev, CONFIG3);
1605         write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1606         /* Turn on Analog power.        */
1607         /* Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.       */
1608         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1609         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1610         write_nic_word(dev, ANAPARAM3, 0x0010);
1611
1612         write_nic_byte(dev, CONFIG3, tmpu8);
1613         write_nic_byte(dev, CR9346, 0x00);
1614         /* enable EEM0 and EEM1 in 9346CR                       */
1615         btCR9346 = read_nic_byte(dev, CR9346);
1616         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1617
1618         /* B cut use LED1 to control HW RF on/off       */
1619         TmpU1b = read_nic_byte(dev, CONFIG5);
1620         TmpU1b = TmpU1b & ~BIT3;
1621         write_nic_byte(dev, CONFIG5, TmpU1b);
1622
1623         /* disable EEM0 and EEM1 in 9346CR      */
1624         btCR9346 &= ~(0xC0);
1625         write_nic_byte(dev, CR9346, btCR9346);
1626
1627         /* Enable Led (suggested by Jong)       */
1628         /* B-cut RF Radio on/off  5e[3]=0       */
1629         btPSR = read_nic_byte(dev, PSR);
1630         write_nic_byte(dev, PSR, (btPSR | BIT3));
1631         /* setup initial timing for RFE.        */
1632         write_nic_word(dev, RFPinsOutput, 0x0480);
1633         SetOutputEnableOfRfPins(dev);
1634         write_nic_word(dev, RFPinsSelect, 0x2488);
1635
1636         /* PHY config.  */
1637         PhyConfig8185(dev);
1638
1639         /*
1640                 We assume RegWirelessMode has already been initialized before,
1641                 however, we has to validate the wireless mode here and provide a
1642                 reasonable initialized value if necessary. 2005.01.13, by rcnjko.
1643         */
1644         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1645         if ((ieee->mode != WIRELESS_MODE_B) &&
1646                 (ieee->mode != WIRELESS_MODE_G) &&
1647                 (ieee->mode != WIRELESS_MODE_A) &&
1648                 (ieee->mode != WIRELESS_MODE_AUTO))     {
1649                 /* It should be one of B, G, A, or AUTO.        */
1650                 bInvalidWirelessMode = 1;
1651         }       else    {
1652         /* One of B, G, A, or AUTO.     */
1653                 /* Check if the wireless mode is supported by RF.       */
1654                 if      ((ieee->mode != WIRELESS_MODE_AUTO) &&
1655                         (ieee->mode & SupportedWirelessMode) == 0)      {
1656                         bInvalidWirelessMode = 1;
1657                 }
1658         }
1659
1660         if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO)   {
1661                 /* Auto or other invalid value.                         */
1662                 /* Assigne a wireless mode to initialize.       */
1663                 if ((SupportedWirelessMode & WIRELESS_MODE_A))  {
1664                         InitWirelessMode = WIRELESS_MODE_A;
1665                 }       else if ((SupportedWirelessMode & WIRELESS_MODE_G))     {
1666                         InitWirelessMode = WIRELESS_MODE_G;
1667                 }       else if ((SupportedWirelessMode & WIRELESS_MODE_B))     {
1668                         InitWirelessMode = WIRELESS_MODE_B;
1669                 }       else    {
1670                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1671                                  SupportedWirelessMode);
1672                         InitWirelessMode = WIRELESS_MODE_B;
1673                 }
1674
1675                 /* Initialize RegWirelessMode if it is not a valid one. */
1676                 if (bInvalidWirelessMode)
1677                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1678
1679         }       else    {
1680         /* One of B, G, A.      */
1681                 InitWirelessMode = ieee->mode;
1682         }
1683 /* by amy for power save        */
1684         priv->eRFPowerState = eRfOff;
1685         priv->RfOffReason = 0;
1686         {
1687                 MgntActSet_RF_State(dev, eRfOn, 0);
1688         }
1689                 /*
1690                         If inactive power mode is enabled, disable rf while in disconnected state.
1691                 */
1692         if (priv->bInactivePs)
1693                 MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
1694
1695 /* by amy for power save        */
1696
1697         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1698
1699         /* ----------------------------------------------------------------------------- */
1700
1701         rtl8185b_irq_enable(dev);
1702
1703         netif_start_queue(dev);
1704         }
1705
1706 void rtl8185b_rx_enable(struct net_device *dev)
1707 {
1708         u8 cmd;
1709         /* for now we accept data, management & ctl frame*/
1710         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1711
1712
1713         if (dev->flags & IFF_PROMISC)
1714                 DMESG("NIC in promisc mode");
1715
1716         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1717            dev->flags & IFF_PROMISC)    {
1718                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1719                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1720         }
1721
1722         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1723                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
1724
1725
1726         if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1727                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1728
1729         write_nic_dword(dev, RCR, priv->ReceiveConfig);
1730
1731         fix_rx_fifo(dev);
1732
1733         cmd = read_nic_byte(dev, CMD);
1734         write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1735
1736 }
1737
1738 void rtl8185b_tx_enable(struct net_device *dev)
1739 {
1740         u8 cmd;
1741         u8 byte;
1742         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1743
1744         write_nic_dword(dev, TCR, priv->TransmitConfig);
1745         byte = read_nic_byte(dev, MSR);
1746         byte |= MSR_LINK_ENEDCA;
1747         write_nic_byte(dev, MSR, byte);
1748
1749         fix_tx_fifo(dev);
1750
1751         cmd = read_nic_byte(dev, CMD);
1752         write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));
1753 }
1754