2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
8 Hardware Initialization and Hardware IO for RTL8185B
12 ---------- --------------- -------------------------------
13 2006-11-15 Xiong Created
16 This file is ported from RTL8185B Windows driver.
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
26 #include "r8180_93cx6.h" /* Card EEPROM */
29 #include "ieee80211/dot11d.h"
32 //#define CONFIG_RTL8180_IO_MAP
34 #define TC_3W_POLL_MAX_TRY_CNT 5
35 static u8 MAC_REG_TABLE[][2]={
37 // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
38 // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
39 // 0x1F0~0x1F8 set in MacConfig_85BASIC()
40 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
41 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
42 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
43 {0x94, 0x0F}, {0x95, 0x32},
44 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
45 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
46 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
47 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
51 // For Flextronics system Logo PCIHCT failure:
52 // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
54 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
55 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
56 {0x82, 0xFF}, {0x83, 0x03},
57 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
58 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
64 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
65 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
66 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
67 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
68 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
69 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
70 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
73 {0x5e, 0x00},{0x9f, 0x03}
77 static u8 ZEBRA_AGC[]={
79 0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
80 0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
81 0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
82 0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
83 0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
84 0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
85 0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
86 0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
89 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
90 0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
91 0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
92 0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
93 0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
94 0x0183,0x0163,0x0143,0x0123,0x0103
97 static u8 OFDM_CONFIG[]={
98 // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
99 // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
100 // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
103 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
104 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
106 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
107 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
109 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
110 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
112 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
113 0xD8, 0x3C, 0x7B, 0x10, 0x10
116 /*---------------------------------------------------------------
118 * the code is ported from Windows source code
119 ----------------------------------------------------------------*/
122 PlatformIOWrite1Byte(
123 struct net_device *dev,
128 write_nic_byte(dev, offset, data);
129 read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
134 PlatformIOWrite2Byte(
135 struct net_device *dev,
140 write_nic_word(dev, offset, data);
141 read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
145 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
148 PlatformIOWrite4Byte(
149 struct net_device *dev,
155 if (offset == PhyAddr)
156 {//For Base Band configuration.
157 unsigned char cmdByte;
158 unsigned long dataBytes;
162 cmdByte = (u8)(data & 0x000000ff);
167 // The critical section is only BB read/write race condition.
169 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
170 // acquiring the spinlock in such context.
171 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
173 // NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
175 for(idx = 0; idx < 30; idx++)
176 { // Make sure command bit is clear before access it.
177 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
178 if((u1bTmp & BIT7) == 0)
184 for(idx=0; idx < 3; idx++)
186 PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
188 write_nic_byte(dev, offset, cmdByte);
190 // NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
194 write_nic_dword(dev, offset, data);
195 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
201 struct net_device *dev,
207 data = read_nic_byte(dev, offset);
215 struct net_device *dev,
221 data = read_nic_word(dev, offset);
229 struct net_device *dev,
235 data = read_nic_dword(dev, offset);
242 SetOutputEnableOfRfPins(
243 struct net_device *dev
246 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
248 switch(priv->rf_chip)
250 case RFCHIPID_RTL8225:
253 write_nic_word(dev, RFPinsEnable, 0x1bff);
254 //write_nic_word(dev, RFPinsEnable, 0x1fff);
261 struct net_device *dev,
269 u16 oval,oval2,oval3;
274 // RTL8187S HSSI Read/Write Function
275 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
276 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
277 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
278 UshortBuffer = read_nic_word(dev, RFPinsOutput);
279 oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
281 oval2 = read_nic_word(dev, RFPinsEnable);
282 oval3 = read_nic_word(dev, RFPinsSelect);
284 // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
287 write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
288 write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
291 // Add this to avoid hardware and software 3-wire conflict.
292 // 2005.03.01, by rcnjko.
294 twreg.struc.enableB = 1;
295 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
297 twreg.struc.enableB = 0;
298 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
301 mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
303 for(i=0; i<totalLength/2; i++)
305 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
306 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
308 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
309 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
311 mask = (low2high)?(mask<<1):(mask>>1);
312 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
313 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
314 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
316 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
317 mask = (low2high)?(mask<<1):(mask>>1);
320 twreg.struc.enableB = 1;
322 twreg.struc.data = 0;
323 write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
326 write_nic_word(dev, RFPinsOutput, oval|0x0004);
327 write_nic_word(dev, RFPinsSelect, oval3|0x0000);
329 SetOutputEnableOfRfPins(dev);
336 struct net_device *dev,
349 // Check if WE and RE are cleared.
350 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
352 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
353 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
359 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
360 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
362 // RTL8187S HSSI Read/Write Function
363 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
367 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
370 u1bTmp &= ~RF_SW_CFG_SI; //reg08[1]=0 Parallel Interface(PI)
373 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
377 // jong: HW SI read must set reg84[3]=0.
378 u1bTmp = read_nic_byte(dev, RFPinsSelect);
380 write_nic_byte(dev, RFPinsSelect, u1bTmp );
382 // Fill up data buffer for write operation.
386 if(nDataBufBitCnt == 16)
388 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
390 else if(nDataBufBitCnt == 64) // RTL8187S shouldn't enter this case
392 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
393 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
398 int ByteCnt = nDataBufBitCnt / 8;
399 //printk("%d\n",nDataBufBitCnt);
400 if ((nDataBufBitCnt % 8) != 0)
401 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
404 if (nDataBufBitCnt > 64)
405 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
408 for(idx = 0; idx < ByteCnt; idx++)
410 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
418 // SI - reg274[3:0] : RF register's Address
419 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
423 // PI - reg274[15:12] : RF register's Address
424 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
428 // Set up command: WE or RE.
431 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
435 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
438 // Check if DONE is set.
439 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
441 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
442 if( (u1bTmp & SW_3W_CMD1_DONE) != 0 )
449 write_nic_byte(dev, SW_3W_CMD1, 0);
451 // Read back data for read operation.
456 //Serial Interface : reg363_362[11:0]
457 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
461 //Parallel Interface : reg361_360[11:0]
462 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
465 *((u16*)pDataBuf) &= 0x0FFF;
476 struct net_device *dev,
489 // Check if WE and RE are cleared.
490 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
492 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
493 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
499 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
500 panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
502 // Fill up data buffer for write operation.
503 if(nDataBufBitCnt == 16)
505 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
507 else if(nDataBufBitCnt == 64)
509 write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
510 write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
515 int ByteCnt = nDataBufBitCnt / 8;
517 if ((nDataBufBitCnt % 8) != 0)
518 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
521 if (nDataBufBitCnt > 64)
522 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
525 for(idx = 0; idx < ByteCnt; idx++)
527 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
531 // Fill up length field.
532 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
534 u1bTmp |= SW_3W_CMD0_HOLD;
535 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
537 // Set up command: WE or RE.
540 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
544 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
547 // Check if WE and RE are cleared and DONE is set.
548 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
550 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
551 if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
552 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
558 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
560 //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
561 // ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
562 // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
563 write_nic_byte(dev, SW_3W_CMD1, 0);
566 // Read back data for read operation.
567 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
570 if(nDataBufBitCnt == 16)
572 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
574 else if(nDataBufBitCnt == 64)
576 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
577 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
582 int ByteCnt = nDataBufBitCnt / 8;
584 if ((nDataBufBitCnt % 8) != 0)
585 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
588 if (nDataBufBitCnt > 64)
589 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
592 for(idx = 0; idx < ByteCnt; idx++)
594 *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
607 struct net_device *dev,
617 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
620 switch(priv->rf_chip)
622 case RFCHIPID_RTL8225:
623 case RF_ZEBRA2: // Annie 2006-05-12.
624 case RF_ZEBRA4: //by amy
625 switch(priv->RegThreeWireMode)
628 { // Perform SW 3-wire programming by driver.
629 data2Write = (data << 4) | (u32)(offset & 0x0f);
632 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
638 data2Write = (data << 4) | (u32)(offset & 0x0f);
642 (u8 *)(&data2Write), // pDataBuf,
643 len, // nDataBufBitCnt,
648 case HW_THREE_WIRE_PI: //Parallel Interface
650 data2Write = (data << 4) | (u32)(offset & 0x0f);
654 (u8*)(&data2Write), // pDataBuf,
655 len, // nDataBufBitCnt,
663 case HW_THREE_WIRE_SI: //Serial Interface
665 data2Write = (data << 4) | (u32)(offset & 0x0f);
667 // printk(" enter ZEBRA_RFSerialWrite\n ");
669 // ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
673 (u8*)(&data2Write), // pDataBuf,
674 len, // nDataBufBitCnt,
678 // printk(" exit ZEBRA_RFSerialWrite\n ");
684 DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
690 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
698 struct net_device *dev,
708 u16 oval,oval2,oval3,tmp, wReg80;
712 //PHAL_DATA_8187 pHalData = GetHalData8187(pAdapter);
713 { // RTL8187S HSSI Read/Write Function
714 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
715 u1bTmp |= RF_SW_CFG_SI; //reg08[1]=1 Serial Interface(SI)
716 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
719 wReg80 = oval = read_nic_word(dev, RFPinsOutput);
720 oval2 = read_nic_word(dev, RFPinsEnable);
721 oval3 = read_nic_word(dev, RFPinsSelect);
723 write_nic_word(dev, RFPinsEnable, oval2|0xf);
724 write_nic_word(dev, RFPinsSelect, oval3|0xf);
728 // We must clear BIT0-3 here, otherwise,
729 // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
730 // which will cause the value read become 0. 2005.04.11, by rcnjko.
733 // Avoid collision with hardware three-wire.
735 twreg.struc.enableB = 1;
736 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
739 twreg.struc.enableB = 0;
741 twreg.struc.read_write = 0;
742 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
744 mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
745 for(i = 0; i < wLength/2; i++)
747 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
748 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
750 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
751 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
753 mask = (low2high) ? (mask<<1): (mask>>1);
757 // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
758 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe); // turn off data enable
759 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
761 twreg.struc.read_write=1;
762 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
764 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
767 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
768 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
769 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
772 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
774 mask = (low2high) ? (mask<<1) : (mask>>1);
778 twreg.struc.data = 0;
779 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
780 mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
783 // 061016, by rcnjko:
784 // We must set data pin to HW controled, otherwise RF can't driver it and
785 // value RF register won't be able to read back properly.
787 write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
789 for(i = 0; i < rLength; i++)
791 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
793 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
794 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
795 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
796 tmp = read_nic_word(dev, RFPinsInput);
797 tdata.longData = tmp;
798 *data2Read |= tdata.struc.clk ? mask : 0;
801 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
803 mask = (low2high) ? (mask<<1) : (mask>>1);
805 twreg.struc.enableB = 1;
807 twreg.struc.data = 0;
808 twreg.struc.read_write = 1;
809 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
811 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8); // Set To Output Enable
812 write_nic_word(dev, RFPinsEnable, oval2); // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
813 //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
814 write_nic_word(dev, RFPinsSelect, oval3); // Set To SW Switch
815 //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
816 write_nic_word(dev, RFPinsOutput, 0x3a0);
817 //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
823 struct net_device *dev,
827 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
834 switch(priv->rf_chip)
836 case RFCHIPID_RTL8225:
839 switch(priv->RegThreeWireMode)
841 case HW_THREE_WIRE_PI: // For 87S Parallel Interface.
843 data2Write = ((u32)(offset&0x0f));
847 (u8*)(&data2Write), // pDataBuf,
848 wlen, // nDataBufBitCnt,
851 dataRead= data2Write;
855 case HW_THREE_WIRE_SI: // For 87S Serial Interface.
857 data2Write = ((u32)(offset&0x0f)) ;
861 (u8*)(&data2Write), // pDataBuf,
862 wlen, // nDataBufBitCnt,
866 dataRead= data2Write;
870 // Perform SW 3-wire programming by driver.
873 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
877 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
891 // by Owen on 04/07/14 for writing BB register successfully
894 struct net_device *dev,
902 UCharData = (u8)((Data & 0x0000ff00) >> 8);
903 PlatformIOWrite4Byte(dev, PhyAddr, Data);
904 //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
906 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
907 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
908 //if(UCharData == RegisterContent)
915 struct net_device *dev,
922 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
923 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
925 return RegisterContent;
930 // Perform Antenna settings with antenna diversity on 87SE.
931 // Created by Roger, 2008.01.25.
934 SetAntennaConfig87SE(
935 struct net_device *dev,
936 u8 DefaultAnt, // 0: Main, 1: Aux.
937 bool bAntDiversity // 1:Enable, 0: Disable.
940 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
941 bool bAntennaSwitched = true;
943 //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
945 // Threshold for antenna diversity.
946 write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
948 if( bAntDiversity ) // Enable Antenna Diversity.
950 if( DefaultAnt == 1 ) // aux antenna
952 // Mac register, aux antenna
953 write_nic_byte(dev, ANTSEL, 0x00);
955 // Config CCK RX antenna.
956 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
957 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
959 // Config OFDM RX antenna.
960 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
961 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
963 else // use main antenna
965 // Mac register, main antenna
966 write_nic_byte(dev, ANTSEL, 0x03);
968 // Config CCK RX antenna.
969 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
970 write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
972 // Config OFDM RX antenna.
973 write_phy_ofdm(dev, 0x0d, 0x5c); // Reg0d : 5c
974 write_phy_ofdm(dev, 0x18, 0xb2); // Reg18 : b2
977 else // Disable Antenna Diversity.
979 if( DefaultAnt == 1 ) // aux Antenna
981 // Mac register, aux antenna
982 write_nic_byte(dev, ANTSEL, 0x00);
984 // Config CCK RX antenna.
985 write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
986 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
988 // Config OFDM RX antenna.
989 write_phy_ofdm(dev, 0x0D, 0x54); // Reg0d : 54
990 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
994 // Mac register, main antenna
995 write_nic_byte(dev, ANTSEL, 0x03);
997 // Config CCK RX antenna.
998 write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
999 write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1001 // Config OFDM RX antenna.
1002 write_phy_ofdm(dev, 0x0D, 0x5c); // Reg0d : 5c
1003 write_phy_ofdm(dev, 0x18, 0x32); // Reg18 : 32
1006 priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1007 return bAntennaSwitched;
1010 /*---------------------------------------------------------------
1011 * Hardware Initialization.
1012 * the code is ported from Windows source code
1013 ----------------------------------------------------------------*/
1016 ZEBRA_Config_85BASIC_HardCode(
1017 struct net_device *dev
1021 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1024 u32 u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1029 //=============================================================================
1030 // 87S_PCIE :: RADIOCFG.TXT
1031 //=============================================================================
1034 // Page1 : reg16-reg30
1035 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); // switch to page1
1036 u4bRF23= RF_ReadReg(dev, 0x08); mdelay(1);
1037 u4bRF24= RF_ReadReg(dev, 0x09); mdelay(1);
1039 if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
1041 printk(KERN_INFO "rtl8187se: card type changed from C- to D-cut\n");
1044 // Page0 : reg0-reg15
1046 // RF_WriteReg(dev, 0x00, 0x003f); mdelay(1);//1
1047 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);// 1
1049 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
1051 // RF_WriteReg(dev, 0x02, 0x004c); mdelay(1);//2
1052 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);// 2
1054 // RF_WriteReg(dev, 0x03, 0x0000); mdelay(1);//3
1055 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);// 3
1057 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
1058 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
1059 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
1060 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
1061 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
1062 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
1063 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
1064 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
1065 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
1066 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
1067 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
1068 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
1071 // Page1 : reg16-reg30
1072 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
1074 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
1076 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
1077 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
1078 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
1081 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
1082 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1083 // RF_WriteReg(dev, 0x08, 0x0597); mdelay(1);
1084 // RF_WriteReg(dev, 0x09, 0x050a); mdelay(1);
1085 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1086 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
1089 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1090 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1091 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1); // RX LO buffer
1093 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
1094 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
1095 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1); // RX LO buffer
1098 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1100 // RF_WriteReg(dev, 0x00, 0x017f); mdelay(1);//6
1101 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1);// 6
1103 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
1104 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
1107 RF_WriteReg(dev, 0x01, i); mdelay(1);
1108 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1109 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1112 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /// 203, 343
1113 //RF_WriteReg(dev, 0x06, 0x0300); mdelay(1); // 400
1114 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); // 400
1116 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30, and HSSI disable 137
1117 mdelay(10); // Deay 10 ms. //0xfd
1119 // RF_WriteReg(dev, 0x0c, 0x09be); mdelay(1); // 7
1120 //RF_WriteReg(dev, 0x0c, 0x07be); mdelay(1);
1121 //mdelay(10); // Deay 10 ms. //0xfd
1123 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1); // Z4 synthesizer loop filter setting, 392
1124 mdelay(10); // Deay 10 ms. //0xfd
1126 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1); // switch to reg0-reg15, and HSSI disable
1127 mdelay(10); // Deay 10 ms. //0xfd
1129 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1); // CBC on, Tx Rx disable, High gain
1130 mdelay(10); // Deay 10 ms. //0xfd
1132 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1); // Z4 setted channel 1
1133 mdelay(10); // Deay 10 ms. //0xfd
1135 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); // LC calibration
1136 mdelay(200); // Deay 200 ms. //0xfd
1137 mdelay(10); // Deay 10 ms. //0xfd
1138 mdelay(10); // Deay 10 ms. //0xfd
1140 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1); // switch to reg16-reg30 137, and HSSI disable 137
1141 mdelay(10); // Deay 10 ms. //0xfd
1143 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
1144 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
1145 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
1146 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
1148 // DAC calibration off 20070702
1149 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
1150 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
1152 // For crystal calibration, added by Roger, 2007.12.11.
1153 if( priv->bXtalCalibration ) // reg 30.
1154 { // enable crystal calibration.
1155 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
1156 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1157 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1158 // So we should minus 4 BITs offset.
1159 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9); mdelay(1);
1160 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1161 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1164 { // using default value. Xin=6, Xout=6.
1165 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
1168 // RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1); //-by amy 080312
1170 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1); // switch to reg0-reg15, and HSSI enable
1171 // RF_WriteReg(dev, 0x0d, 0x009f); mdelay(1); // Rx BB start calibration, 00c//-edward
1172 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1); // Rx BB start calibration, 00c//+edward
1173 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1); // temperature meter off
1174 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); // Rx mode
1175 mdelay(10); // Deay 10 ms. //0xfe
1176 mdelay(10); // Deay 10 ms. //0xfe
1177 mdelay(10); // Deay 10 ms. //0xfe
1178 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1); // Rx mode//+edward
1179 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1); // Rx mode//+edward
1180 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1); // Rx mode//+edward
1182 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1); // Rx mode//+edward
1183 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1); // Rx mode//+edward
1184 //power save parameters.
1185 u1b24E = read_nic_byte(dev, 0x24E);
1186 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1188 //=============================================================================
1190 //=============================================================================
1192 //=============================================================================
1194 /* [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1195 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1196 CCK reg0x00[6]=1'b1: power saving for RX (default)
1197 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1198 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1199 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1202 write_phy_cck(dev,0x00,0xc8);
1203 write_phy_cck(dev,0x06,0x1c);
1204 write_phy_cck(dev,0x10,0x78);
1205 write_phy_cck(dev,0x2e,0xd0);
1206 write_phy_cck(dev,0x2f,0x06);
1207 write_phy_cck(dev,0x01,0x46);
1210 write_nic_byte(dev, CCK_TXAGC, 0x10);
1211 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1212 write_nic_byte(dev, ANTSEL, 0x03);
1216 //=============================================================================
1218 //=============================================================================
1220 // PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280); // Annie, 2006-05-05
1221 write_phy_ofdm(dev, 0x00, 0x12);
1222 //WriteBBPortUchar(dev, 0x00001280);
1224 for (i=0; i<128; i++)
1226 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1228 data = ZEBRA_AGC[i+1];
1230 data = data | 0x0000008F;
1232 addr = i + 0x80; //enable writing AGC table
1234 addr = addr | 0x0000008E;
1236 WriteBBPortUchar(dev, data);
1237 WriteBBPortUchar(dev, addr);
1238 WriteBBPortUchar(dev, 0x0000008E);
1241 PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080); // Annie, 2006-05-05
1242 //WriteBBPortUchar(dev, 0x00001080);
1244 //=============================================================================
1246 //=============================================================================
1248 //=============================================================================
1253 u4bRegValue=OFDM_CONFIG[i];
1255 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1257 WriteBBPortUchar(dev,
1259 (u4bRegOffset & 0x7f) |
1260 ((u4bRegValue & 0xff) << 8)));
1263 //=============================================================================
1264 //by amy for antenna
1265 //=============================================================================
1267 // Config Sw/Hw Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1268 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1270 //by amy for antenna
1276 struct net_device *dev
1279 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1280 //unsigned char* IGTable;
1281 //u8 DIG_CurrentInitialGain = 4;
1282 //unsigned char u1Tmp;
1285 if(priv->eRFPowerState != eRfOn)
1287 //Don't access BB/RF under disable PLL situation.
1288 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1289 // Back to the original state
1290 priv->InitialGain= priv->InitialGainBackUp;
1294 switch(priv->rf_chip)
1297 // Dynamic set initial gain, follow 87B
1298 switch(priv->InitialGain)
1301 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1302 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1303 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1304 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1308 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1309 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1310 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1311 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1315 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1316 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
1317 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1318 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1322 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1323 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1324 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1325 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1329 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1330 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
1331 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1332 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
1336 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1337 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1338 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
1339 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1343 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1344 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
1345 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
1346 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1350 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1351 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
1352 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
1353 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
1358 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1359 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
1360 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
1361 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
1368 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1374 // Tx Power tracking mechanism routine on 87SE.
1375 // Created by Roger, 2007.12.11.
1378 InitTxPwrTracking87SE(
1379 struct net_device *dev
1382 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1385 u4bRfReg = RF_ReadReg(dev, 0x02);
1387 // Enable Thermal meter indication.
1388 //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1389 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
1394 struct net_device *dev
1397 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1398 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1399 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1401 switch(priv->rf_chip)
1405 ZEBRA_Config_85BASIC_HardCode( dev);
1409 // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1410 if(priv->bDigMechanism)
1412 if(priv->InitialGain == 0)
1413 priv->InitialGain = 4;
1414 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1418 // Enable thermal meter indication to implement TxPower tracking on 87SE.
1419 // We initialize thermal meter here to avoid unsuccessful configuration.
1420 // Added by Roger, 2007.12.11.
1422 if(priv->bTxPowerTrack)
1423 InitTxPwrTracking87SE(dev);
1426 priv->InitialGainBackUp= priv->InitialGain;
1427 UpdateInitialGain(dev);
1437 struct net_device *dev
1440 //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1441 // u8 bUNIVERSAL_CONTROL_RL = 1;
1442 u8 bUNIVERSAL_CONTROL_RL = 0;
1444 u8 bUNIVERSAL_CONTROL_AGC = 1;
1445 u8 bUNIVERSAL_CONTROL_ANT = 1;
1446 u8 bAUTO_RATE_FALLBACK_CTL = 1;
1448 //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1449 //struct ieee80211_device *ieee = priv->ieee80211;
1450 //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1451 //{by amy 080312 if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1453 // write_nic_word(dev, BRSR, 0xffff);
1457 // write_nic_word(dev, BRSR, 0x000f);
1460 write_nic_word(dev, BRSR, 0x0fff);
1462 val8 = read_nic_byte(dev, CW_CONF);
1464 if(bUNIVERSAL_CONTROL_RL)
1469 write_nic_byte(dev, CW_CONF, val8);
1472 val8 = read_nic_byte(dev, TXAGC_CTL);
1473 if(bUNIVERSAL_CONTROL_AGC)
1475 write_nic_byte(dev, CCK_TXAGC, 128);
1476 write_nic_byte(dev, OFDM_TXAGC, 128);
1481 val8 = val8 | 0x01 ;
1485 write_nic_byte(dev, TXAGC_CTL, val8);
1487 // Tx Antenna including Feedback control
1488 val8 = read_nic_byte(dev, TXAGC_CTL );
1490 if(bUNIVERSAL_CONTROL_ANT)
1492 write_nic_byte(dev, ANTSEL, 0x00);
1497 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1500 write_nic_byte(dev, TXAGC_CTL, val8);
1502 // Auto Rate fallback control
1503 val8 = read_nic_byte(dev, RATE_FALLBACK);
1505 if( bAUTO_RATE_FALLBACK_CTL )
1507 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1509 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1510 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1512 // Aadded by Roger, 2007.11.15.
1513 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1519 write_nic_byte(dev, RATE_FALLBACK, val8);
1525 MacConfig_85BASIC_HardCode(
1526 struct net_device *dev)
1528 //============================================================================
1530 //============================================================================
1533 u32 u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1536 nLinesRead=sizeof(MAC_REG_TABLE)/2;
1538 for(i = 0; i < nLinesRead; i++) //nLinesRead=101
1540 u4bRegOffset=MAC_REG_TABLE[i][0];
1541 u4bRegValue=MAC_REG_TABLE[i][1];
1543 if(u4bRegOffset == 0x5e)
1545 u4bPageIndex = u4bRegValue;
1549 u4bRegOffset |= (u4bPageIndex << 8);
1551 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1552 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1554 //============================================================================
1561 struct net_device *dev)
1565 MacConfig_85BASIC_HardCode(dev);
1567 //============================================================================
1569 // Follow TID_AC_MAP of WMac.
1570 write_nic_word(dev, TID_AC_MAP, 0xfa50);
1572 // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1573 write_nic_word(dev, IntMig, 0x0000);
1575 // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1576 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1577 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1578 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1580 // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1581 //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1583 // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1585 //Enable DA10 TX power saving
1586 u1DA = read_nic_byte(dev, PHYPR);
1587 write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1590 write_nic_word(dev, 0x360, 0x1000);
1591 write_nic_word(dev, 0x362, 0x1000);
1594 write_nic_word(dev, 0x370, 0x0560);
1595 write_nic_word(dev, 0x372, 0x0560);
1596 write_nic_word(dev, 0x374, 0x0DA4);
1597 write_nic_word(dev, 0x376, 0x0DA4);
1598 write_nic_word(dev, 0x378, 0x0560);
1599 write_nic_word(dev, 0x37A, 0x0560);
1600 write_nic_word(dev, 0x37C, 0x00EC);
1601 // write_nic_word(dev, 0x37E, 0x00FE);//-edward
1602 write_nic_word(dev, 0x37E, 0x00EC);//+edward
1603 write_nic_byte(dev, 0x24E,0x01);
1612 GetSupportedWirelessMode8185(
1613 struct net_device *dev
1616 u8 btSupportedWirelessMode = 0;
1617 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1619 switch(priv->rf_chip)
1623 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1626 btSupportedWirelessMode = WIRELESS_MODE_B;
1630 return btSupportedWirelessMode;
1634 ActUpdateChannelAccessSetting(
1635 struct net_device *dev,
1636 WIRELESS_MODE WirelessMode,
1637 PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1640 struct r8180_priv *priv = ieee80211_priv(dev);
1641 struct ieee80211_device *ieee = priv->ieee80211;
1644 //PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
1645 u8 bFollowLegacySetting = 0;
1650 // TODO: We still don't know how to set up these registers, just follow WMAC to
1651 // verify 8185B FPAG.
1654 // Jong said CWmin/CWmax register are not functional in 8185B,
1655 // so we shall fill channel access realted register into AC parameter registers,
1658 ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1659 ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1660 ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1661 ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1662 ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1663 ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1665 write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1666 //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer ); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1667 write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1669 u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1671 //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1672 //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1673 //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1674 //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1676 write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1678 write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1681 // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1682 if( pStaQos->CurrentQosMode > QOS_DISABLE )
1684 if(pStaQos->QBssWirelessMode == WirelessMode)
1686 // Follow AC Parameters of the QBSS.
1687 for(eACI = 0; eACI < AC_MAX; eACI++)
1689 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1694 // Follow Default WMM AC Parameters.
1695 bFollowLegacySetting = 1;
1701 bFollowLegacySetting = 1;
1705 // this setting is copied from rtl8187B. xiong-2006-11-13
1706 if(bFollowLegacySetting)
1711 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1712 // 2005.12.01, by rcnjko.
1714 AcParam.longData = 0;
1715 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1716 AcParam.f.AciAifsn.f.ACM = 0;
1717 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1718 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1719 AcParam.f.TXOPLimit = 0;
1721 //lzm reserved 080826
1723 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1724 if( ieee->current_network.Turbo_Enable == 1 )
1725 AcParam.f.TXOPLimit = 0x01FF;
1726 // For 87SE with Intel 4965 Ad-Hoc mode have poor throughput (19MB)
1727 if (ieee->iw_mode == IW_MODE_ADHOC)
1728 AcParam.f.TXOPLimit = 0x0020;
1731 for(eACI = 0; eACI < AC_MAX; eACI++)
1733 AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1735 PAC_PARAM pAcParam = (PAC_PARAM)(&AcParam);
1740 // Retrive paramters to udpate.
1741 eACI = pAcParam->f.AciAifsn.f.ACI;
1742 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1743 u4bAcParam = ( (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET) |
1744 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET) |
1745 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET) |
1746 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1751 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1755 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1759 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1763 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1767 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1772 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1773 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1775 PACI_AIFSN pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1776 AC_CODING eACI = pAciAifsn->f.ACI;
1779 //for 8187B AsynIORead issue
1781 u8 AcmCtrl = pHalData->AcmControl;
1785 if( pAciAifsn->f.ACM )
1790 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); // or 0x21
1794 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); // or 0x42
1798 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); // or 0x84
1802 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1811 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xDE
1815 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0xBD
1819 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) ); // and 0x7B
1827 //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1830 pHalData->AcmControl = AcmCtrl;
1832 //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1833 write_nic_byte(dev, ACM_CONTROL, 0);
1843 ActSetWirelessMode8185(
1844 struct net_device *dev,
1848 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1849 struct ieee80211_device *ieee = priv->ieee80211;
1850 //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
1851 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1853 if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1854 { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1855 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1856 btWirelessMode, btSupportedWirelessMode);
1860 // 1. Assign wireless mode to swtich if necessary.
1861 if (btWirelessMode == WIRELESS_MODE_AUTO)
1863 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1865 btWirelessMode = WIRELESS_MODE_A;
1867 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1869 btWirelessMode = WIRELESS_MODE_G;
1871 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1873 btWirelessMode = WIRELESS_MODE_B;
1877 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1878 btSupportedWirelessMode);
1879 btWirelessMode = WIRELESS_MODE_B;
1884 // 2. Swtich band: RF or BB specific actions,
1885 // for example, refresh tables in omc8255, or change initial gain if necessary.
1886 switch(priv->rf_chip)
1891 // Nothing to do for Zebra to switch band.
1892 // Update current wireless mode if we swtich to specified band successfully.
1893 ieee->mode = (WIRELESS_MODE)btWirelessMode;
1898 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
1902 // 3. Change related setting.
1903 if( ieee->mode == WIRELESS_MODE_A ){
1904 DMESG("WIRELESS_MODE_A\n");
1906 else if( ieee->mode == WIRELESS_MODE_B ){
1907 DMESG("WIRELESS_MODE_B\n");
1909 else if( ieee->mode == WIRELESS_MODE_G ){
1910 DMESG("WIRELESS_MODE_G\n");
1913 ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1916 void rtl8185b_irq_enable(struct net_device *dev)
1918 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1920 priv->irq_enabled = 1;
1921 write_nic_dword(dev, IMR, priv->IntrMask);
1923 //by amy for power save
1925 DrvIFIndicateDisassociation(
1926 struct net_device *dev,
1930 //printk("==> DrvIFIndicateDisassociation()\n");
1932 // nothing is needed after disassociation request.
1934 //printk("<== DrvIFIndicateDisassociation()\n");
1938 struct net_device *dev
1941 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1944 //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1946 DrvIFIndicateDisassociation(dev, unspec_reason);
1948 // PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1949 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x55;
1951 priv->ieee80211->state = IEEE80211_NOLINK;
1955 // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1956 // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1957 // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1959 // Disable Beacon Queue Own bit, suggested by jong
1960 // Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1961 ieee80211_stop_send_beacons(priv->ieee80211);
1963 priv->ieee80211->link_change(dev);
1964 notify_wx_assoc_event(priv->ieee80211);
1966 // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1968 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1972 MlmeDisassociateRequest(
1973 struct net_device *dev,
1978 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1981 SendDisassociation(priv->ieee80211, asSta, asRsn );
1983 if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
1984 //ShuChen TODO: change media status.
1985 //ShuChen TODO: What to do when disassociate.
1986 DrvIFIndicateDisassociation(dev, unspec_reason);
1989 // pMgntInfo->AsocTimestamp = 0;
1990 for(i=0;i<6;i++) priv->ieee80211->current_network.bssid[i] = 0x22;
1991 // pMgntInfo->mBrates.Length = 0;
1992 // Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
1994 ieee80211_disassociate(priv->ieee80211);
2003 struct net_device *dev,
2007 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2010 // Commented out by rcnjko, 2005.01.27:
2011 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2013 // //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2014 // SecClearAllKeys(Adapter);
2016 // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2018 if( pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2019 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) ) // In CCKM mode will Clear key
2021 SecClearAllKeys(Adapter);
2022 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2025 // 2004.10.11, by rcnjko.
2026 //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2027 MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2029 priv->ieee80211->state = IEEE80211_NOLINK;
2030 // pMgntInfo->AsocTimestamp = 0;
2034 struct net_device *dev,
2038 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2040 // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2043 if(pMgntInfo->mPss != eAwake)
2046 // Using AwkaeTimer to prevent mismatch ps state.
2047 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2049 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2050 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2054 // Indication of disassociation event.
2055 //DrvIFIndicateDisassociation(Adapter, asRsn);
2056 if(IS_DOT11D_ENABLE(priv->ieee80211))
2057 Dot11d_Reset(priv->ieee80211);
2058 // In adhoc mode, update beacon frame.
2059 if( priv->ieee80211->state == IEEE80211_LINKED )
2061 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2063 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2064 //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2065 MgntDisconnectIBSS(dev);
2067 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2069 // We clear key here instead of MgntDisconnectAP() because that
2070 // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2071 // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2072 // used to handle disassociation related things to AP, e.g. send Disassoc
2073 // frame to AP. 2005.01.27, by rcnjko.
2074 // SecClearAllKeys(Adapter);
2076 // RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2077 //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2078 MgntDisconnectAP(dev, asRsn);
2081 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2082 // MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2089 // Chang RF Power State.
2090 // Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2097 struct net_device *dev,
2098 RT_RF_POWER_STATE eRFPowerState
2101 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2102 bool bResult = false;
2104 // printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2105 if(eRFPowerState == priv->eRFPowerState)
2107 // printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2111 switch(priv->rf_chip)
2115 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2119 printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2122 // printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2127 HalEnableRx8185Dummy(
2128 struct net_device *dev
2133 HalDisableRx8185Dummy(
2134 struct net_device *dev
2140 MgntActSet_RF_State(
2141 struct net_device *dev,
2142 RT_RF_POWER_STATE StateToSet,
2146 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2147 bool bActionAllowed = false;
2148 bool bConnectBySSID = false;
2149 RT_RF_POWER_STATE rtState;
2150 u16 RFWaitCounter = 0;
2152 // printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2154 // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2155 // Only one thread can change the RF state at one time, and others should wait to be executed.
2160 // down(&priv->rf_state);
2161 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2162 if(priv->RFChangeInProgress)
2164 // printk("====================>haha111111111\n");
2165 // up(&priv->rf_state);
2166 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2167 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2168 // Set RF after the previous action is done.
2169 while(priv->RFChangeInProgress)
2172 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2173 udelay(1000); // 1 ms
2175 // Wait too long, return FALSE to avoid to be stuck here.
2176 if(RFWaitCounter > 1000) // 1sec
2178 // RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2179 printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2180 // TODO: Reset RF state?
2187 // printk("========================>haha2\n");
2188 priv->RFChangeInProgress = true;
2189 // up(&priv->rf_state);
2190 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2195 rtState = priv->eRFPowerState;
2202 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2203 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2205 priv->RfOffReason &= (~ChangeSource);
2207 if(! priv->RfOffReason)
2209 priv->RfOffReason = 0;
2210 bActionAllowed = true;
2212 if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2214 bConnectBySSID = true;
2218 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2223 // 070125, rcnjko: we always keep connected in AP mode.
2225 if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2229 // Disconnect to current BSS when radio off. Asked by QuanTa.
2233 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2234 // because we do NOT need to set ssid to dummy ones.
2235 // Revised by Roger, 2007.12.04.
2237 MgntDisconnect( dev, disas_lv_ss );
2239 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2240 // 2007.05.28, by shien chang.
2241 // PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2242 // pMgntInfo->NumBssDesc = 0;
2243 // PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2244 // pMgntInfo->NumBssDesc4Query = 0;
2249 priv->RfOffReason |= ChangeSource;
2250 bActionAllowed = true;
2254 priv->RfOffReason |= ChangeSource;
2255 bActionAllowed = true;
2264 // RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2265 // Config HW to the specified mode.
2266 // printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2267 SetRFPowerState(dev, StateToSet);
2270 if(StateToSet == eRfOn)
2272 HalEnableRx8185Dummy(dev);
2275 // by amy not supported
2276 // MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2280 else if(StateToSet == eRfOff)
2282 HalDisableRx8185Dummy(dev);
2287 // printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2290 // Release RF spinlock
2291 // down(&priv->rf_state);
2292 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2293 priv->RFChangeInProgress = false;
2294 // up(&priv->rf_state);
2295 spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2296 // printk("<===MgntActSet_RF_State()\n");
2297 return bActionAllowed;
2301 struct net_device *dev
2304 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2308 // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2309 // is really scheduled.
2310 // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2311 // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2312 // blocks the IPS procedure of switching RF.
2313 // By Bruce, 2007-12-25.
2315 priv->bSwRfProcessing = true;
2317 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2320 // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2323 priv->bSwRfProcessing = false;
2328 // Enter the inactive power save mode. RF will be off
2329 // 2007.08.17, by shien chang.
2333 struct net_device *dev
2336 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2337 RT_RF_POWER_STATE rtState;
2338 //printk("==============================>enter IPS\n");
2339 if (priv->bInactivePs)
2341 rtState = priv->eRFPowerState;
2344 // Added by Bruce, 2007-12-25.
2345 // Do not enter IPS in the following conditions:
2346 // (1) RF is already OFF or Sleep
2347 // (2) bSwRfProcessing (indicates the IPS is still under going)
2348 // (3) Connectted (only disconnected can trigger IPS)
2349 // (4) IBSS (send Beacon)
2350 // (5) AP mode (send Beacon)
2352 if (rtState == eRfOn && !priv->bSwRfProcessing
2353 && (priv->ieee80211->state != IEEE80211_LINKED ))
2355 // printk("IPSEnter(): Turn off RF.\n");
2356 priv->eInactivePowerState = eRfOff;
2357 InactivePowerSave(dev);
2360 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2364 struct net_device *dev
2367 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2368 RT_RF_POWER_STATE rtState;
2369 //printk("===================================>leave IPS\n");
2370 if (priv->bInactivePs)
2372 rtState = priv->eRFPowerState;
2373 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2375 // printk("IPSLeave(): Turn on RF.\n");
2376 priv->eInactivePowerState = eRfOn;
2377 InactivePowerSave(dev);
2380 // printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2382 //by amy for power save
2383 void rtl8185b_adapter_start(struct net_device *dev)
2385 struct r8180_priv *priv = ieee80211_priv(dev);
2386 struct ieee80211_device *ieee = priv->ieee80211;
2388 u8 SupportedWirelessMode;
2389 u8 InitWirelessMode;
2390 u8 bInvalidWirelessMode = 0;
2398 //rtl8180_rtx_disable(dev);
2400 write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2404 priv->dma_poll_mask = 0;
2405 priv->dma_poll_stop_mask = 0;
2407 //rtl8180_beacon_tx_disable(dev);
2409 HwConfigureRTL8185(dev);
2411 write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2412 write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2414 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); // default network type to 'No Link'
2416 //write_nic_byte(dev, BRSR, 0x0); // Set BRSR= 1M
2418 write_nic_word(dev, BcnItv, 100);
2419 write_nic_word(dev, AtimWnd, 2);
2421 //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2422 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2424 write_nic_byte(dev, WPA_CONFIG, 0);
2426 MacConfig_85BASIC(dev);
2428 // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2429 // BT_DEMO_BOARD type
2430 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2432 //#ifdef CONFIG_RTL818X_S
2433 // for jong required
2434 // PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2438 //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2440 //-----------------------------------------------------------------------------
2441 // Set up PHY related.
2442 //-----------------------------------------------------------------------------
2443 // Enable Config3.PARAM_En to revise AnaaParm.
2444 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2446 tmpu8 = read_nic_byte(dev, CONFIG3);
2447 write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2449 // Turn on Analog power.
2450 // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2451 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2452 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2454 write_nic_word(dev, ANAPARAM3, 0x0010);
2457 write_nic_byte(dev, CONFIG3, tmpu8);
2458 write_nic_byte(dev, CR9346, 0x00);
2459 //{by amy 080312 for led
2460 // enable EEM0 and EEM1 in 9346CR
2461 btCR9346 = read_nic_byte(dev, CR9346);
2462 write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2464 // B cut use LED1 to control HW RF on/off
2465 TmpU1b = read_nic_byte(dev, CONFIG5);
2466 TmpU1b = TmpU1b & ~BIT3;
2467 write_nic_byte(dev,CONFIG5, TmpU1b);
2469 // disable EEM0 and EEM1 in 9346CR
2470 btCR9346 &= ~(0xC0);
2471 write_nic_byte(dev, CR9346, btCR9346);
2473 //Enable Led (suggested by Jong)
2474 // B-cut RF Radio on/off 5e[3]=0
2475 btPSR = read_nic_byte(dev, PSR);
2476 write_nic_byte(dev, PSR, (btPSR | BIT3));
2477 //by amy 080312 for led}
2478 // setup initial timing for RFE.
2479 write_nic_word(dev, RFPinsOutput, 0x0480);
2480 SetOutputEnableOfRfPins(dev);
2481 write_nic_word(dev, RFPinsSelect, 0x2488);
2486 // We assume RegWirelessMode has already been initialized before,
2487 // however, we has to validate the wireless mode here and provide a
2488 // reasonable initialized value if necessary. 2005.01.13, by rcnjko.
2489 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2490 if( (ieee->mode != WIRELESS_MODE_B) &&
2491 (ieee->mode != WIRELESS_MODE_G) &&
2492 (ieee->mode != WIRELESS_MODE_A) &&
2493 (ieee->mode != WIRELESS_MODE_AUTO))
2494 { // It should be one of B, G, A, or AUTO.
2495 bInvalidWirelessMode = 1;
2498 { // One of B, G, A, or AUTO.
2499 // Check if the wireless mode is supported by RF.
2500 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2501 (ieee->mode & SupportedWirelessMode) == 0 )
2503 bInvalidWirelessMode = 1;
2507 if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2508 { // Auto or other invalid value.
2509 // Assigne a wireless mode to initialize.
2510 if((SupportedWirelessMode & WIRELESS_MODE_A))
2512 InitWirelessMode = WIRELESS_MODE_A;
2514 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2516 InitWirelessMode = WIRELESS_MODE_G;
2518 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2520 InitWirelessMode = WIRELESS_MODE_B;
2524 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2525 SupportedWirelessMode);
2526 InitWirelessMode = WIRELESS_MODE_B;
2529 // Initialize RegWirelessMode if it is not a valid one.
2530 if(bInvalidWirelessMode)
2532 ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2536 { // One of B, G, A.
2537 InitWirelessMode = ieee->mode;
2539 //by amy for power save
2540 // printk("initialize ENABLE_IPS\n");
2541 priv->eRFPowerState = eRfOff;
2542 priv->RfOffReason = 0;
2545 // u32 tmp = jiffies;
2546 MgntActSet_RF_State(dev, eRfOn, 0);
2548 // printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2550 // DrvIFIndicateCurrentPhyStatus(priv);
2552 // If inactive power mode is enabled, disable rf while in disconnected state.
2553 // 2007.07.16, by shien chang.
2555 if (priv->bInactivePs)
2558 // u32 tmp = jiffies;
2559 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2561 // printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2565 //by amy for power save
2567 // Turn off RF if necessary. 2005.08.23, by rcnjko.
2568 // We shall turn off RF after setting CMDR, otherwise,
2569 // RF will be turnned on after we enable MAC Tx/Rx.
2570 if(Adapter->MgntInfo.RegRfOff == TRUE)
2572 SetRFPowerState8185(Adapter, RF_OFF);
2576 SetRFPowerState8185(Adapter, RF_ON);
2580 /* //these is equal with above TODO.
2581 write_nic_byte(dev, CR9346, 0xc0); // enable config register write
2582 write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2583 RF_WriteReg(dev, 0x4, 0x9FF);
2584 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2585 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2586 write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2587 write_nic_byte(dev, CR9346, 0x00);
2590 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2592 //-----------------------------------------------------------------------------
2594 rtl8185b_irq_enable(dev);
2596 netif_start_queue(dev);
2601 void rtl8185b_rx_enable(struct net_device *dev)
2605 /* for now we accept data, management & ctl frame*/
2606 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2608 if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2610 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2611 dev->flags & IFF_PROMISC){
2612 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2613 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2616 /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2617 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2618 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2621 if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2622 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2625 if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2626 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2628 write_nic_dword(dev, RCR, priv->ReceiveConfig);
2633 DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2635 cmd=read_nic_byte(dev,CMD);
2636 write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2640 void rtl8185b_tx_enable(struct net_device *dev)
2646 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2648 write_nic_dword(dev, TCR, priv->TransmitConfig);
2649 byte = read_nic_byte(dev, MSR);
2650 byte |= MSR_LINK_ENEDCA;
2651 write_nic_byte(dev, MSR, byte);
2656 DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2659 cmd=read_nic_byte(dev,CMD);
2660 write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2662 //write_nic_dword(dev,TX_CONF,txconf);
2666 rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2667 write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2668 rtl8180_set_mode(dev,EPROM_CMD_NORMAL);