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19 ******************************************************************************/
21 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
27 Implement HW Power sequence configuration CMD handling routine for Realtek devices.
31 ---------- --------------- -------------------------------
32 2011-10-26 Lucas Modify to be compatible with SD4-CE driver.
33 2011-07-07 Roger Create.
37 #include <HalPwrSeqCmd.h>
40 /* This routine deals with the Power Configuration CMDs parsing
41 * for RTL8723/RTL8188E Series IC.
43 * We should follow specific format which was released from HW SD.
45 u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 cut_vers, u8 fab_vers,
46 u8 ifacetype, struct wl_pwr_cfg pwrseqcmd[])
48 struct wl_pwr_cfg pwrcfgcmd = {0};
53 u32 poll_count = 0; /* polling autoload done. */
54 u32 max_poll_count = 5000;
57 pwrcfgcmd = pwrseqcmd[aryidx];
59 RT_TRACE(_module_hal_init_c_ , _drv_info_,
60 ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
61 GET_PWR_CFG_OFFSET(pwrcfgcmd),
62 GET_PWR_CFG_CUT_MASK(pwrcfgcmd),
63 GET_PWR_CFG_FAB_MASK(pwrcfgcmd),
64 GET_PWR_CFG_INTF_MASK(pwrcfgcmd),
65 GET_PWR_CFG_BASE(pwrcfgcmd),
66 GET_PWR_CFG_CMD(pwrcfgcmd),
67 GET_PWR_CFG_MASK(pwrcfgcmd),
68 GET_PWR_CFG_VALUE(pwrcfgcmd)));
70 /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */
71 if ((GET_PWR_CFG_FAB_MASK(pwrcfgcmd) & fab_vers) &&
72 (GET_PWR_CFG_CUT_MASK(pwrcfgcmd) & cut_vers) &&
73 (GET_PWR_CFG_INTF_MASK(pwrcfgcmd) & ifacetype)) {
74 switch (GET_PWR_CFG_CMD(pwrcfgcmd)) {
76 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
79 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
80 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
82 /* Read the value from system register */
83 value = rtw_read8(padapter, offset);
85 value &= ~(GET_PWR_CFG_MASK(pwrcfgcmd));
86 value |= (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd));
88 /* Write the value back to system register */
89 rtw_write8(padapter, offset, value);
92 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
95 offset = GET_PWR_CFG_OFFSET(pwrcfgcmd);
97 value = rtw_read8(padapter, offset);
99 value &= GET_PWR_CFG_MASK(pwrcfgcmd);
100 if (value == (GET_PWR_CFG_VALUE(pwrcfgcmd) & GET_PWR_CFG_MASK(pwrcfgcmd)))
105 if (poll_count++ > max_poll_count) {
106 DBG_88E("Fail to polling Offset[%#x]\n", offset);
112 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
113 if (GET_PWR_CFG_VALUE(pwrcfgcmd) == PWRSEQ_DELAY_US)
114 rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd));
116 rtw_udelay_os(GET_PWR_CFG_OFFSET(pwrcfgcmd)*1000);
119 /* When this command is parsed, end the process */
120 RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
124 RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
129 aryidx++;/* Add Array Index */